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Built-in Self Test

Panpan Hu

[email protected]

Built-in self-test is a DFT scheme in which all the components of anexternal tester are essentially integrated into the chip so that either an

external tester is eliminated or a much simpler one will do.

1



Outlines

Overview of BISTBackground

The Economic Case

BIST in Logic CircuitMemory BISTGeneral info

March test

A Case Study :

An Efficient BIST for Testing Virtex-4 block RAMs

2



Background

Usually, we have assumed that testing of logic circuits is done byexternally applying the test inputs and comparing the results withthe expected behavior of the circuit. This requires connectingexternal equipment to the circuit under test.

An interesting question is whether it is possible to incorporate thetesting capability within the circuit itself so that no externalequipment is need.

A possible BIST arrangement

Test vector

generator

Circuit under

test

Test result

compressor

Chip boundary 3



Built-in self-test cost

This table shows the relative BIST costs at the chip,board,andsystem levels of packaging

5



BIST in Logic Circuit

Generating the test vectors on-chip

:preudorandom test

LFSRs(Linear feedback shift registers)

Single/multiple-input compressor

circuit(SIC/MIC)

Built-in Logic Block Observer(BILBO)Signature analysis

Boundary scan

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BIST is currently used extensively in memory designs but not

as much in logic designs. 7



Memory BIST

Embedded RAM memories are perhaps the hardest typeof digital circuit to test, because memory testing requiresdelivery of a huge number of pattern stimuli to thememory and the readout of an enormous amount of cell

information.With memory design for testability (DFT), the most time-

consuming part of a memory test algorithm isimplemented on-chip, and reduces the memory test timeby an order of magnitude.

Most memory BIST schemes exploit the parallelism withinthe memory device to achieve a massive reduction in testtime (and therefore cost).

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LFSR

memory BIST requires an address generator

(often an LFSR). An LFSR is better for march

test BIST than a binary counter,because

it uses substantially less area and can easily be madeself-testable.

the LSFR can be adjusted to provide the all-zero pattern

and the forward and exact reverse LSFR SEQUENCES.

Another advantage is that the probability of an addressbit changing is equal for all address bits.

9



Comparator

The comparator eliminates the need to

generate the good machine response and

implicitly assumes that only a minority of

the memory array outputs are incorrect atany given time.

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March Test

The march tests are appropriate for

SRAM testing.

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MATS+ March Test RAM BIST

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MATS+ March Test RAM BIST

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A Case Study :

An Efficient BIST for Testing Configurable

Embedded Memories in FPGAsUsing the latest Virtex 4 (V4) FPGA

from Xilinx as model

At 9,936Kbits of block RAM (18Keach), the V 4 FX140 is quite possiblethe largest FPGA currentlymanufactured

It is a true dual-port memory coreThe wider memory configurations are

512 x 36, 1K x 18, and 2K x 9 .

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TPG Port Model

The TPG for this BIST architecture must be able togenerate a sequence of different march tests. Thisfigure illustrates the input and output ports of such a TPG.

The mode bit vector allows theuser to set the march test tobe performed.

The addition of dual addressand data lines providessupport for the needed dual

port testing. Varying active levels should

be tested during the many BIST cycles the TPG will generate.

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Overview of March Algorithms

March LR [2]

March LR with DBS[3]

MarchS+

S2PF and D2PF[1]

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March LR [2]

transition faults (TF)

idempotent coupling faults(CFid)

state coupling faults (CFst)

disturb faults (CFdst) data retention faults (DRF)

Therefore, this table shows that this test sequence is superior to March C-18



March LR with DBS[3]

In [3], Goor describes a method for efficiently converting a bit-orientedmemory march test such as MarchLR to word-oriented memory(WOM) tests.

WOM march tests can detect inter-word faults and intra-word faults.

V4 block RAMs have the ability toaddress words within a line of memory. In a 512 x 36

configuration, there are four wordsand a parity bit for each word. Instead of zeros and ones, Goor

describes a sequence of bits that iscalled a background data sequence(BDS).

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MarchS+

We have discussed it before.

The MATS+ memory test algorithm is thesimplest march test to detect all AFs

(address decoder faults) for memoryresource.

MATS+ is needed to exercise the

programmable address decoder in each of the remaining configurations (16k x 1).

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S2PF and D2PF[1] Cont.

March d2PF

March d2PF uses a double-addressing scheme.

Note that C and R in Figure 4 are the number of

address location on each port of the block RAM.

22



Application to Virtex 4 Block Rams

As in all testing algorithms, the goal is to maximize faultcoverage while minimizing the test time.

In order to test the V4 block RAMs efficiently, it is

proposed that the testing should take place in threedistinct phases.

STEP1: detect faults in the 18K memory cells.

STEP2: target faults in the programmable address decoder ineach of the remaining memory modes.

STEP3: target faults in the dual-port functionality.

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STEP1

the March LR algorithm with BDS is used to verify that theRAM matrix (containing the memory cells) is fault-free.

A procedure is given in [3] for converting March LR to aword-oriented test by incorporat-ing BDS.

The two widest memory configurations (512×36-bit and1K×18-bit) have the ability of writing byte-wise to thememory locations.

After March LR with BDS testing, the RAM matrix isassumed to be fault-free if the ORAs did not detect anymismatch during the circular comparison.

As a result, BDS is applied only during the first BISTconfiguration since once tested there is no need to repeatpattern sensitivity and coupling fault tests in the RAMmatrix.

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Performance Analysis

Virtex-4 block RAMs share many

similarities with the block RAMs in Virtex 2

As such, a comparison of the expected

performance should be beneficial.

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As can be seen from Table 1 and 2 where the total test time, in

terms of BIST clock cycles, is compared with that for similar blockRAMs in Virtex 2 using the BIST approach including March LR.

In that BIST approach, the March LR algorithm was used to test allsingle-port RAM modes of operation

As a result, it required about 2.5 times more BIST execution clock

cycles compared to what we have currently developed for Virtex-4.

Performance Analysis Cont.

27



References

[1] Hamdioui, Said and van de Goor, A.J. Efficient Test for Realistic Faults in Dual-Port SRAMS. IEEE Transactions on Computers, VOL.51. NO. 5, 2002

[2] van de Goor, A.J. et al. March LR: A Test for Realistic Linked Faults. 14th VLSI Test Symposium, pp. 272-281, 1996

[3] van de Goor, A.J. and Tlili, I.B.S. March tests for word-oriented

memories. Design, Automation and Test in Europe, 1998.,Proceedings, pp 501 – 508, . 1998 [4] van de Goor, A.J. Testing Semiconductor Memories: Theory

and Practice. Comtex Publishing: Gouda, Netherlands, 1998 [5] “Virtex-4 User Guide,” UG070 (v1.4), Xilinx, Inc., 2005, available

at www.xilinx.com [6] C. Stroud, A Designer’s Guide to Built-In Self-Test , Kluwer

Academic Publishers, Boston, 2002 [7] “Virtex 1 Data Sheet, “DS112 (v1.5), Xilinx, Inc., 2001, available at

www.xilinx.com [8] C. Stroud and S. Garimella, “BIST and Diagnosis of Multiple

Embedded Cores in SoCs,” Proc. Int’l Conf. on Embedded Systems & Applications, pp. 130-136, 2005

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