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6. S. Jin, Y. Han, H. Li, Xiaowei Li, “Unified Capture Scheme for Small Delay Defect Detection and

Aging Prediction”, IEEE Transactions on VLSI Systems, Vol.21, No.5, May 2013, pp.821-833

7. Y. Chen, L. Zhang, Y. Han, Xiaowei Li, “TSV Minimization for Circuit—Partitioned 3D SoC Test

Wrapper DesignTSV Minimization for Circuit—Partitioned 3D SoC Test Wrapper Design”, Journal of

Computer Science and Technology, 28(1): 119-128, Jan. 2013

8. Y. Chen, L. Zhang, Y. Han, Xiaowei Li, “Thermal-Constrained Scheduling for Interconnect Energy

Reduction in 3D Homogeneous MPSoCs”, IEEE Transactions on VLSI Systems, Vol.21, No.2, Feb.

2013, pp.239-249

9. S. Pei, H. Li, Xiaowei Li, “Flip-flop Selection for Partial Enhanced Scan to Reduce Transition Test

Pattern Volume”, IEEE Transactions on VLSI Systems, Vol.20, No.12, Dec. 2012, pp.2157-2169

10. S. Pei, H. Li, Xiaowei Li, “A High-Precision On-Chip Path Delay Measurement Architecture”, IEEE

Transactions on VLSI Systems, Vol.20, No.09, Sept 2012, pp.1565-1577

11. S. Pan, Y. Hu, Xiaowei Li, “IVF: Characterizing the Vulnerability of Microprocessor Structures to

Intermittent Faults”, IEEE Transactions on VLSI Systems, Vol.20, No.05, May 2012, pp.777-790

12. H. Zhu, X. Li, Y. Xu, Xiaowei Li, “An Energy-Efficient Link Quality Monitoring Scheme for Wireless

Networks”, Wireless Communications and Mobile Computing, Volume 12, Issue 4, March 2012,

pp.333-344

13. X. Fu, H. Li, Xiaowei Li, “Testable Path Selection and Grouping for Faster Than At-Speed Testing”,

IEEE Transactions on VLSI Systems, Vol.20, No.02, February 2012, pp.236-247

14. M. Zhang, H. Li, Xiaowei Li, “Path Delay Test Generation Toward Activation of Worst Case Coupling

Effects”, IEEE Transactions on VLSI Systems, Vol.19, No.11, November 2011, pp.1969-1982

15. Y. Zhang, H. Li, Y. Min, Xiaowei Li, “Selected Transition Time Adjustment for Tolerating Crosstalk

Effects on Network-on-Chip Interconnects”, IEEE Transactions on VLSI Systems, Vol.19, No.10,

October 2011, pp.1787-1800

16. G. Yan, Y. Han, Xiaowei Li, “SVFD: A Versatile Online Fault Detection Scheme via Checking of

Stability Violation”, IEEE Transactions on VLSI Systems, Vol.19, No.9, September 2011, pp.1627-1640

17. G. Yan, Y. Han, Xiaowei Li, “ReviveNet: A Self-adaptive Architecture for Improving Lifetime

Reliability via Localized Timing Adaptation”, IEEE Transactions on Computers, Volume 60, Issue 9,

September 2011, pp.1219-1232

18. D. Fan, Xiaowei Li, G. Li, “New Methodologies for Parallel Architecture”, Journal of Computer Science

and Technology, 26(4): 578-584, July 2011

19. B. Fu, Y. Han, H. Li, Xiaowei Li, “A New Multiple-Round Dimension-Order Routing for

Networks-on-Chip”, IEICE Transactions, Volume 94-D, Number 4, April 2011, pp.809-821

20. G. Yan, Y. Han, H. Liu, X. Liang, Xiaowei Li, “Microfix: Using timing interpolation and delay sensors

for power reduction”, ACM Transactions on Design Automation of Electronic Systems, March 2011,

Vol. 16, No. 2, Article 16:1-21

21. J. Zhou, Y. Xu, Xiaowei Li, “A Security Mechanism for RFID with Dependable Proxy”, Intelligent

Automation and Soft Computing, 17(6), 2011, pp.815-825

22. Y. Hu, Z. Chen, Xiaowei Li, “OWARE: Operand Width Aware Redundant Execution for

Whole-Processor Error Detection”, Intelligent Automation and Soft Computing, Volume 6, Issue 11,

2011, pp.771-780

23. Z. An, H. Zhu, C. Xu, Y. Xu, Xiaowei Li, “Synchronization of Linear Pulse-coupled Oscillators with

Different Frequency”, IEEE Transactions on Industry Electronics, Vol.58, No.6, June 2011, pp.

2205-2215

24. Y. Yang, Y. Xu, Xiaowei Li, “A Loss Inference Algorithm for Wireless Sensor Networks to Improve

Data Reliability of Digital Ecosystems”, IEEE Transactions on Industry Electronics, Vol.58, No.6, June

3

2011, pp. 2126-2137

25. J. Li, X. Liu, Y. Zhang, Y. Hu, Xiaowei Li, Q. Xu, “Capture-power-aware test data compression using

selective encoding”, INTEGRATION, the VLSI journal, Volume 44, Issue 3, June 2011, pp. 205-216

26. S. Jin, Y. Han, H. Li, Xiaowei Li, “Statistical Lifetime Reliability Optimization Considering Joint Effect

of Process Variation and Aging”, INTEGRATION, the VLSI journal, Volume 44, Issue 3, June 2011,

Pages 185-191

27. J. Li, Y. Hu, Xiaowei Li, “Scan Chain Design for Shift Power Reduction in Scan-based Testing”,

Science in China, Series F, Inf. Sci, 54(4), April 2011, pp.767-777

28. J. Dong, L. Zhang, Y. Han, G. Yan, Xiaowei Li, “Performance-asymmetry-aware scheduling for Chip

Multiprocessors with static core coupling”, Journal of Systems Architecture, 56 (2010), pp.534-542

29. J. Liu, Y. Han, Xiaowei Li, “Extended Selective Encoding of Scan Slices for Reducing Test Data and

Test Power”, IEICE Transactions on Information and Systems, Vol.E93-D, No.8, August 2010,

pp.2223-2232

30. J. Gao; Y. Han; Xiaowei Li, “A Novel PostSilicon Debug Mechanism Based on Suspect Window”,

IEICE Transactions on Information and Systems, Vol.E93-D, No.5, 2010, pp.1175-1185

31. J. Li, Q. Xu, Y. Hu, Xiaowei Li, “X-Filling for Simultaneous Shift- and Capture- Power Reduction in

At-Speed Scan-Based Testing”, IEEE Transactions on VLSI Systems, Vol.18, No.7, July. 2010,

pp.1081-1092

32. X. Fu, H. Li, Xiaowei Li, “Testable Critical Path Selection Considering Process Variation”, IEICE

Transactions on Information and Systems, Vol.E93-D, No.1, Jan. 2010, pp.59-67

33. Y. Zhang, H. Li, Xiaowei Li, “Selected Crosstalk Avoidance Code for Reliable Network-on-Chip”,

Journal of Computer Science and Technology, Vol.24, No.6, Nov. 2009, pp.1074-1085

34. L. Zhang, Y. Han, Q. Xu, Xiaowei Li, H. Li, “On Topology Reconfiguration for Defect-Tolerant

NoC-Based Homogeneous Manycore Systems”, IEEE Transactions on VLSI Systems, Vol.17, No.9,

Sept. 2009, pp.1173-1186

35. W. Wang, Y. Han, Xiaowei Li, F. Fang, “Co-optimization of Dynamic/Static Test Power in Scan Test”,

Chinese Journal of Electronics, Vol.18, No.1, 2009, pp.54-58

36. G. Yan, Y. Han, Xiaowei Li, H. Liu, “BAT: Performance-Driven Crosstalk Mitigation Based on

Bus-grouping Asynchronous Transmission”, IEICE Transactions on Electronics, Vol. E91-C, No.10,

2008, pp. 1690-1697

37. D. Wang, Y. Hu, H. Li, Xiaowei Li, “Design-for-Testability Features and Test Implementation of a Giga

Hertz General Purpose Microprocessor”, Journal of Computer Science and Technology, 23(6):

1037-1046 Nov. 2008

38. L. Sun, H. Zhu, B. Duan, Xiaowei Li, Y. Sun, “Analysis of Forwarding Mechanisms on Fine-Grain

Gradient Sinking Model in WSN”, The Journal of VLSI Signal Processing, 51, 2008, pp.145–159

39. W. Wang, Y. Hu, Y. Han, Xiaowei Li, Y. Zhang, “Leakage Current Optimization Techniques during

Test based on Don’t Care Bits Assignment”, Journal of Computer Science and Technology, Vol.22,

No.5, 2007, pp.673-680

40. Yi. Han, Y. Hu, Xiaowei Li, A. Chandra, Huawei Li, “Embedded Test Decompressor to Reduce the

Required Channels and Vector Memory of Tester for System-on-a-Chip”, IEEE Transactions on VLSI

Systems, Vol.15, No.5, May 2007, pp.531-540

41. G. Huang, Xiaowei Li, J. He, X. Li, “Data Mining via Minimal Spanning Tree Clustering for Prolonging

Lifetime of Wireless Sensor Networks”, International Journal of Information Technology and Decision

Making, Vol.6, Issue 2, June 2007, pp. 235-251

42. L. Zhao, W. Zhang, C. Xu, Y. Xu, Xiaowei Li, “Energy-Aware System Design for Wireless Sensor

Network”, ACTA Automatica Sinica, 2006, Vol.32, Issue 6, pp.892-899

4

43. C. Xu, L. Zhao, Y. Xu, Xiaowei Li, “Simsync: A Time Synchronization Simulator for Sensor

Networks”, ACTA Automatica Sinica, 2006, Vol.32, Issue 6, pp.1008-1014

44. T. Lv, J. Fan, Xiaowei Li, L. Liu, “An Observability Evaluation Technique Based on Dynamic Factored

Use-Def Chains”, Journal of Electronic Testing: Theory and Application, Vol.22, No.3, 2006,

pp.273-285

45. Y. Hu, Y. Han, Xiaowei Li, H. Li, X. Wen, “Compression/Scan Co-Design for Reducing Test Data

Volume, Scan-in Power Dissipation, and Test Application Time”, IEICE Transactions on Information

and Systems, Vol.E89-D, No.10, 2006, pp.2616-2625

46. Y. Han, Xiaowei Li, H. Li, A. Chandra, “Embedded Test Resource for SoC to Reduce Required Tester

Channels Based on Advanced Convolutional Codes”, IEEE Transactions on Instrumentation and

Measurement, Vol.55, No.2, April, 2006, pp.389-399

47. Y. Han, H. Li, Xiaowei Li, A. Chandra, “Response compaction for system-on-a-chip based on advanced

convolutional codes”, Science In China, Serial F, Vol. 49, No.2, April, 2006, pp. 262-272

48. S. Gong, H. Li, Xiaowei Li, “An Innovative Free Memory Design for Network Processors in Home

Network Gateway”, IEEE Transactions on Consumer Electronics, Vol.51, No.4, Nov. 2005,

pp.1182-1187

49. W. Lu, X. Yang, T. Lv, Xiaowei Li, “An Efficient Evaluation and Vector Generation Method for

Observability-Enhanced Statement Coverage”, Journal of Computer Science and Technology, Vol.20,

No.6, Nov., 2005, pp.875-884

50. Y. Han, Y. Hu, Xiaowei Li, H. Li, A. Chandra, X. Wen, “Wrapper Scan Chains Design for Rapid and

Low Power Testing of Embedded cores”, IEICE Transactions on Information and Systems, Vol.E88-D,

No.9, 2005, pp.2126-2134

51. Y. Han, Xiaowei Li, H. Li, A. Chandra, “Test Resource Partitioning Based on Efficient Response

Compaction for Test Time and Tester Channels Reduction”, Journal of Computer Science and

Technology, Vol.20, No.2, 2005, pp.201-209

52. H. Li, Xiaowei Li, “Selection of Crosstalk-induced Faults in Enhanced Delay Test”, Journal of

Electronic Testing: Theory and Application, Vol.21, No.2, 2005, pp.181-195

53. Xiaowei Li, M. Shao, G. Li, “Formal Verification Techniques Based on Boolean Satisfiability Problem”,

Journal of Computer Science and Technology,Vol.20, No.1, 2005, pp. 38-47

54. Y. Xu, Z. Luo, Xiaowei Li, L. Li, X. Hong, “Leakage Current Estimation of CMOS Circuit with Stack

Effect Considered”, Journal of Computer Science and Technology, Vol.19, No.5, 2004, pp.708-717

55. Z. Yin, Y. Min, Xiaowei Li, H. Li, “A Novel RT-Level Behavioral Description Based ATPG Method”,

Journal of Computer Science and Technology, Vol.18, No.3, 2003, pp.308-317

56. Z. Luo, Y. Min, S. Yang, Xiaowei Li, “The Monotonic Increasing Relationship between Average Powers

of CMOS VLSI Circuits With and Without Delay and Its Application”, Sciences in China, Series F,

Vol.45, No.6, 2002, pp.401-415

57. Xiaowei Li, P,Y.S.Cheung, “A Loop-Based Apparatus for At-Speed Self-Testing”, Journal of Computer

Science and Technology, Vol.16, No.3, 2001, pp.278-285

58. Xiaowei Li, P.Y.S.Cheung, H. Fujiwara, “LFSR-Based Deterministic TPG for Two-Pattern Testing”,

Journal of Electronic Testing: Theory and Application, Vol.16, No.5, 2000, pp.419-426

 

Conference Publications 

1. J. Ma, G. Yan, Y. Han, Xiaowei Li, “Amphisbaena: Modeling Two Orthogonal Ways to Hunt on

Heterogeneous Many-Cores”, Proc. of 19th IEEE Asia-Pacific Design Automation Conference

(ASP-DAC), Jan. 20- 23, 2014, Singapore

5

2. Y. Zhou, T. Wang, T. Lv, H. Li, Xiaowei Li, “Path Constraint Solving based Test Generation for

Hard-to-reach States”, Proc. of IEEE Asian Test Symposium (ATS), Taiwan, November 19-22, 2013

3. Y. Han, Y. Wang, H. Li, Xiaowei Li, “Enabling Near-Threshold Voltage(NTV) operation in Multi-VDD

cache for power reduction”, Proc. of IEEE International Symposium on Circuits and Systems (ISCAS),

Beijing, China, May 19-23, 2013, pp.337-340

4. B. Li, S. Shan, Y. Hu, X Xiaowei Li, “Tolerating Noise in MLC PCM with Multi-Bit Error Correction

Code”, IEEE 19th Pacific Rim International Symposium on Dependable Computing (PRDC 2013),

December 2-4, 2013, Vancouver, Canada

5. K. Huang, E. Yang, Y. Hu, Xiaowei Li, J. Gong, H. Liu, B. Liu, “HHC: Hierarchical Hardware

Checkpointing to Accelerate Fault Recovery for SRAM-based FPGAs”, 19th IEEE International On-Line

Testing Symposium (IOLTS), July 8-10, 2013, Chania, Greece

6. Xiaowei Li, “Chip Design & EDA in China”, ACM/IEEE Design Automation Conference (DAC), Global

Forum, June 2-6, 2013, Austin, USA

7. H. Lu, G. Yan, Y. Han, B. Fu, Xiaowei Li, “RISO: Relaxed Network-on-Chip Isolation for Cloud

Processors”, ACM/IEEE Design Automation Conference (DAC), June 2-5, 2013, Austin, USA

8. Y. Fang, H. Li, Xiaowei Li, “RSAK: Random Steam Attact for Phase Change Memory in Video

Applications”, IEEE VLSI Test Symposium (VTS), April 29-May 1, 2013, Berkeley, USA

9. Y. Han, S. Jin, Q. Xu, Xiaowei Li, “On predicting NBTI-induced Circuit Aging by Isolating Leakage

Change”, International Symposium on Quality Electronic Design (ISQED), March 4-6, 2013, Santa Clara,

pp.46-52

10. X. Zhang, J. Ye, Y. Hu, Xiaowei Li, “Capturing Post-Silicon Variation by Layout-Aware Path-Delay

Testing”, IEEE Design, Automation and Test in Europe (DATE), March 18-22, 2013, Grenoble, France,

pp.288-291

11. X. Hu, G. Yan, Y. Hu, Xiaowei Li, “Orchestrator: a Low-cost Solution to Reduce Voltage Emergencies

for Multi-threaded Applications”, IEEE Design, Automation and Test in Europe (DATE), March 18-22,

2013, Grenoble, France, pp.208-213

12. X. Li, G. Yan, Y. Han, Xiaowei Li, “SmartCap: User Experience-Oriented Power Adaptation for

Smartphone’s Application Processor”, IEEE Design, Automation and Test in Europe (DATE), March

18-22, 2013, Grenoble, France, pp.57-60

13. Y. Fang, H. Li, Xiaowei Li, “SoftPCM: Enhancing Energy Efficiency and Lifetime of Phase Change

Memory in Video Applications via Approximate Write”, Proc. of IEEE Asian Test Symposium,

Nov.19-22, 2012, Niigata, Japan, pp.131-136

14. Y. Hu, X. Gu, Xiaowei Li, “In-Field Testing of NAND Flash Storage: Why and How?”, Proc. of IEEE

Asian Test Symposium, Nov.19-22, 2012, Niigata, Japan, p.69

15. K. Huang, Y. Hu, Xiaowei Li, B. Liu, H. Liu, J. Gong, “Off-path Leakage Power Aware Routing for

SRAM-based FPGAs”, Proc. of IEEE Design, Automation and Test in Europe (DATE), March 12-16,

2012, Dresden, Germany, p.87

16. J. Gao, J. Wang, Y. Han, L. Zhang, Xiaowei Li, “A Clustering-Based Scheme for Concurrent Trace in

Debugging NoC-Based Multicore Systems”, Proc. of IEEE Design, Automation and Test in Europe

(DATE), March 12-16, 2012, Dresden, Germany, p.27

17. G. Yan, Y. Li, Y. Han, Xiaowei Li, X. Liang, “AgileRegulator: A Hybrid Voltage Regulator Scheme

Redeeming Dark Silicon for Power Efficiency in a Multicore Architecture”, Proc. of IEEE The

High-Performance Computer Architecture Symposium 2012 (HPCA-18), New Orleans, 25-29 February

2012

18. F. Lockom, Z. Li, K. Yue, S. Ghalim, S. Ren, L. Zhang, Xiaowei Li, “Hungarian Algorithm Based

Virtualization to Maintain Application Timing Similarity for Defect-Tolerant NoC”, Proc. of 17th IEEE

6

Asia-Pacific Design Automation Conference (ASP-DAC), Jan. 30- Feb. 2, 2012. Sydney, Australia, 2012,

pp.493-498

19. Y. Fang, H. Li, Xiaowei Li, “A Fault Criticality Evaluation Framework of Digital Systems for Error

Tolerant Video Applications”, Proc. of IEEE Asian Test Symposium, Nov.21-23, 2011, Delhi, India,

pp.329-334

20. K. Huang, Y. Hu, Xiaowei Li, “Exploiting Free LUT Entries to Mitigate Soft Errors in SRAM-based

FPGAs”, Proc. of IEEE Asian Test Symposium, Nov.21-23, 2011, Delhi, India, pp.438-443

21. Y. Cheng, L. Zhang, Y. Han, Xiaowei Li, “Wrapper Chain Design for Testing TSVs Minimization in

Circuit-Partitioned 3D SoC”, Proc. of IEEE Asian Test Symposium, Nov.21-23, 2011, Delhi, India,

pp.181-186

22. G. Yan, Xiaowei Li, “Online Timing Variation Tolerance for Digital Integrated Circuits”, Proc. of IEEE

International Test Conference (ITC), September 19-22, 2011, USA, paper 4.1

23. K. Yue, S. Ghalim, Z. Li, F. Lockom, S. Ren, L. Zhang, Xiaowei Li, “A Greedy Approach to Tolerate

Defect Cores for Multimedia Applications”, IEEE/ACM Symposium on Embedded Systems for Real-time

Multimedia (ESTIMedia 2011), Oct 13-14, 2011, Taipei, pp.112-119

24. S. Shan, Y. Hu, Xiaowei Li, “Transparent Dynamic Binding with Fault-Tolerant Cache Coherence

Protocol for Chip Multiprocessors”, Proc. of IEEE/IFIP 41th International Conference on Dependable

Systems and Networks (DSN), Hong Kong, June 27-30, 2011, pp.291-302

25. J. Dong, L. Zhang, Y. Han, Y. Wang, Xiaowei Li, “Wear Rate Leveling: Lifetime Enhancement of PRAM

with Endurance Variation”, Proc. of IEEE/ACM 48th Design Automation Conference (DAC), San Diego,

USA, June 5-10, 2011, pp.972-977

26. B. Fu, Y. Han, H. Li, Xiaowei Li, “An Abacus Turn Model for Time/Space-Efficient Reconfigurable

Routing”, Proc. of IEEE 38th International Symposium on Computer Architecture (ISCA), San Jose, USA,

June 4-8, 2011, pp.259-270

27. S. Pei, H. Li, Xiaowei Li, “A Unified Test Architecture for On-Line and Off-Line Delay Fault

Detections”, Proc. of 29th IEEE VLSI Test Symposium (VTS), May 2-4, 2011, Dana Point, California,

pp.272-277

28. Y. Wang, L. Zhang, Y. Han, H. Li, Xiaowei Li, “Flex Memory: Exploiting and Managing Abundant

Off-Chip Optical Bandwidth”, Proc. of IEEE Design, Automation and Test in Europe (DATE), March

14-18, 2011, Grenoble, France, pp.968-973

29. J. Gao, Y. Han, Xiaowei Li, “Eliminating Data Invalidation in Debugging Multiple-Clock Chips”, Proc. of

IEEE Design, Automation and Test in Europe (DATE), March 14-18, 2011, Grenoble, France, pp.691-696

30. J. Ye, Y. Hu, Xiaowei Li, “On Diagnosis of Multiple Faults Using Compacted Responses”, Proc. of IEEE

Design, Automation and Test in Europe (DATE), March 14-18, 2011, Grenoble, France, pp.679-684

31. S. Pan, Y. Hu, X. Hu, Xiaowei Li, “A Cost-effective Substantial-impact-filter Based Method to Tolerate

Voltage Emergencies”, Proc. of IEEE Design, Automation and Test in Europe (DATE), March 14-18,

2011, Grenoble, France, pp.311-316

32. K. Huang, Y. Hu, Xiaowei Li, “Cross-layer Optimized Placement and Routing for FPGA Soft Error

Mitigation”, Proc. of IEEE Design, Automation and Test in Europe (DATE), March 14-18, 2011,

Grenoble, France, pp.58-63

33. C. Liu, L. Zhang, Y. Han, Xiaowei Li, “A Resilient On-chip Router Design Through Data Path

Salvaging”, Proc. of 16th IEEE Asia-Pacific Design Automation Conference (ASP-DAC), Tokyo, Japan,

January 25-28, 2011, pp.437-442

34. C. Liu, L. Zhang, Y. Han, Xiaowei Li, “Vertical Interconnects Squeezing in Symmetric 3D Mesh

Network-on-Chip”, Proc. of 16th IEEE Asia-Pacific Design Automation Conference (ASP-DAC), Tokyo,

Japan, January 25-28, 2011, pp.357-362

7

35. L. Wang, Y. Leiferman, S. Ren, K. A. Kwiat, Xiaowei Li, “Improving complex distributed software

system availability through information hiding”, Proc. of the 2010 ACM Symposium on Applied

Computing (SAC), Sierre, Switzerland, March 22-26, 2010, pp.452-456

36. Y. Wang, L. Zhang, Y. Han, H. Li, Xiaowei Li, “Address Remapping for Static NUCA in NoC-based

Degradable Chip-Multiprocessors”, Proc. of 16th IEEE Pacific Rim International Symposium on

Dependable Computing (PRDC'10), December 13-15, 2010, Tokyo, Japan, pp.70-76

37. Y. Zhang, H. Li, Xiaowei Li, “Software-Based Self-Testing of Processors Using Expanded Instructions”,

Proc. of IEEE Asian Test Symposium (ATS), Shanghai, December 1-4, 2010, pp.415-420

38. Z. He, T. Lv, H. Li, Xiaowei Li, “An Efficient Algorithm for Finding a Universal Set of Testable Long

Paths”, Proc. of IEEE Asian Test Symposium (ATS), Shanghai, December 1-4, 2010, pp.319-324

39. J. Ye, X. Zhang, Y. Hu, Xiaowei Li, “Substantial Fault Pair at A Time (SFPAT): An Automatic

Diagnostic Pattern Generation Method”, Proc. of IEEE Asian Test Symposium (ATS), Shanghai, December

1-4, 2010, pp.192-197

40. S. Jin, Y. Han, H. Li, Xiaowei Li, “P²CLRAF: An Pre- and Post-silicon Cooperated Circuit Lifetime

Reliability Analysis Framework”, Proc. of IEEE Asian Test Symposium (ATS), Shanghai, December 1-4,

2010, pp.117-120

41. X. Fu, H. Li, Xiaowei Li, “On Selection of Testable Paths with Specified Lengths for

Faster-Than-At-Speed Testing”, Proc. of IEEE Asian Test Symposium (ATS), Shanghai, December 1-4,

2010, pp.45-48

42. Z. He, T. Lv, H. Li, Xiaowei Li, “On Generation of a Universal Path Candidate Set Containing Testable

Long Paths”, Proc. of IEEE International Test Conference (ITC), Austin, US, November 2-4, 2010, poster

16

43. H. Li, D. Xu, Y. Han, K-T. Cheng, Xiaowei Li, “nGFSIM: A GPU-Based 1-to-n-Detection Fault

Simulator and its Applications”, Proc. of IEEE International Test Conference (ITC), Austin, US,

November 2-4, 2010, paper 12.1

44. G. Yan, X. Liang, Y. Han, Xiaowei Li, “Leveraging the Core-Level Complementary Effects of PVT

Variations to Reduce Timing Emergencies in Multi-Core Processors”, Proc. of IEEE 37th International

Symposium on Computer Architecture (ISCA), Saint-Malo, France, June 19-23, 2010, pp.485-496

45. Z. He, T. Lv, H. Li, Xiaowei Li, “Fast path selection for testing of small delay defects considering path

correlations”, Proc. of IEEE VLSI Test Symposium (VTS), April 18-21, 2010, Santa Cruz, USA,

pp.203-208

46. S. Pei, H. Li, Xiaowei Li, “A Novel On-Chip Clock Generation Scheme for Faster-than-at-Speed Delay

Testing”, Proc. of IEEE Design, Automation and Test in Europe (DATE), March 8-12, 2010, Dresden,

Germany, pp. 1353-1356

47. B. Fu, Y. Han, H. Li, Xiaowei Li, “Binary-Tree Waveguide Connected Time/Power Efficient Optical

Network-on-Chip”, Proc. of IEEE Design, Automation and Test in Europe (DATE), March 8-12, 2010,

Dresden, Germany, pp.933-936

48. L. Zhang, Y. Yu, Y. Han, S. Ren, Xiaowei Li, “Performance-Asymmetry-Aware Topology Virtualization

for Defect-Tolerant NoC-Based Many-core Processors”, Proc. of IEEE Design, Automation and Test in

Europe (DATE), March 8-12, 2010, Dresden, Germany, pp.1566-1572

49. T. Zhang, T. Lv, Xiaowei Li, “An Abstraction-Guided Simulation Approach using Markov Models for

Microprocessor Verification”, Proc. of IEEE Design, Automation and Test in Europe (DATE), March

8-12, 2010, Dresden, Germany, pp.484-489

50. J. Ye, Y. Hu, Xiaowei Li, “Diagnosis of Multiple Arbitrary Faults with Mask and Reinforcement Effect”,

Proc. of IEEE Design, Automation and Test in Europe (DATE), March 8-12, 2010, Dresden, Germany,

pp.885-890

8

51. S. Pan, Y. Hu, Xiaowei Li, “IVF: Characterizing the Vulnerability of Microprocessor Structures to

Intermittent faults”, Proc. of IEEE Design, Automation and Test in Europe (DATE), March 8-12, 2010,

Dresden, Germany, pp.238-243

52. Z. He, T. Lv, H. Li, Xiaowei Li, “Graph partition based path selection for testing of small delay defects”,

Proc. of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC’10), Taipei, Taiwan, Jan.

18-21 2010, pp.499-504

53. S. Jin, Y. Han, L. Zhang, H. Li, Xiaowei Li, G. Yan, “M-IVC: Using Multiple Input Vectors to Minimize

Aging-induced Delay”, Proc. of IEEE Asian Test Symposium (ATS), November 23-26, 2009, Taichung,

pp.437-442

54. J. Liu, Y. Han, Xiaowei Li, “Extended Selective Encoding of Scan Slices for Reducing Test Data and Test

Power”, Proc. of IEEE Asian Test Symposium (ATS), November 23-26, 2009, Taichung, pp.319-324

55. S. Pei, H. Li, Xiaowei Li, “A Low Overhead On-chip Path Delay Measurement Circuit”, Proc. of IEEE

Asian Test Symposium (ATS), November 23-26, 2009, Taichung, pp.145-150

56. S. Pan, Y. Hu, Xiaowei Li, “Online Computing and Predicting Architectural Vulnerability Factor of

Microprocessor Structures”, Proc. of IEEE 15th Pacific Rim International Symposium on Dependable

Computing (PRDC’09), November 16-18, 2009, Shanghai, China, pp.345-350

57. B. Fu, Y. Han, H. Li, Xiaowei Li, “A New Multiple-Round DOR Routing for 2D NoC Meshes”, Proc. of

IEEE 15th Pacific Rim International Symposium on Dependable Computing (PRDC’09), November

16-18, 2009, Shanghai, China, pp.276-281

58. S. Pei, H. Li, Xiaowei Li, “Flip-flop Selection for Transition Test Pattern Reduction Using Partial

Enhanced Scan”, Proc. of IEEE 15th Pacific Rim International Symposium on Dependable Computing

(PRDC’09), November 16-18, 2009, Shanghai, China, pp.75-80

59. J. Wang, H. Li, Y. Min, Xiaowei Li, H. Liang, “Impact of Hazards on Pattern Selection for Small Delay

Defects”, Proc. of IEEE 15th Pacific Rim International Symposium on Dependable Computing

(PRDC’09), November 16-18, 2009, Shanghai, China, pp.49-54

60. J. Dong, L. Zhang, Y. Han, G. Yan, Xiaowei Li, “Variation-Aware Scheduling for Chip Multiprocessor

with Thread-Level Redundancy”, Proc. of IEEE 15th Pacific Rim International Symposium on

Dependable Computing (PRDC’09), November 16-18, 2009, Shanghai, China, pp.17-22

61. B. Fu, Y. Han, H. Li, Xiaowei Li, “T2-TAM: Reusing Infrastructure Resource to Provide Parallel Testing

for NoC based Chip”, Proc. of IEEE 8th International Conference on ASIC (ASICON), October 20-23,

2009, Changsha, China, pp.91-96 (Invited paper)

62. G. Yan, Y. Han, H. Liu, X. Liang, Xiaowei Li, “MicroFix: Exploiting Path-grained Timing Adaptability

for Improving Power-Performance Efficiency”, Proc. of IEEE/ACM International Symposium on Low

Power Electronics and Design (ISLPED), Aug 19-21, 2009, San Francisco, pp.395-400

63. G. Yan, Y. Han, Xiaowei Li, “A Unified Online Fault Detection Scheme via Checking of Stability

Violation”, Proc. of IEEE Design, Automation and Test in Europe (DATE), April 20-24, 2009, Nice,

France, pp.496-501

64. T. Lv, H. Li, Xiaowei Li, “Automatic Selection of Internal Observation Signals for Design Verification”,

Proc. of IEEE VLSI Test Symposium (VTS), May 3-7, 2009, Santa Cruz, USA, pp.203-208

65. J. Gao, Y. Han, Xiaowei Li, “A New Post-silicon Debug Approach with Suspect Window”, Proc. of IEEE

VLSI Test Symposium (VTS), May 3-7, 2009, Santa Cruz, USA, pp.85-90

66. Y. Yang, Y. Xu, Xiaowei Li, “A Sensor Network Performance Inference Algorithm Based on Passive

Measurement”, Proc. of IEEE Wireless Communication & Networking Conference (WCNC 2009), April

5-8 2009, Budapest, Hungary, page 1-6

67. Q. Zhou, Y. Xu, Xiaowei Li, “Mean Shift Based Collaborative Localization with Dynamically Clustering

for Wireless Sensor Networks”, Proc. of IEEE 2009 WRI International Conference on Communications

9

and Mobile Computing (CMC2009), January 6-8, 2009, Kunming, Yunnan, China, pp.66-70

68. Q. Zhou, Y. Xu, Xiaowei Li, “Smallest Enclosing Circle based Localization Approach for Wireless Sensor

Networks”, Proc. of IEEE 2009 WRI International Conference on Communications and Mobile

Computing (CMC2009), January 6-8, 2009, Kunming, Yunnan, China, pp.61-65

69. Y. Yang, Y. Xu, Xiaowei Li, “Topology Tomography in Wireless Sensor Networks Based on Data

Aggregation”, Proc. of IEEE 2009 WRI International Conference on Communications and Mobile

Computing (CMC2009), January 6-8, 2009, Kunming, Yunnan, China, pp.37-40

70. Y. Zhang, H. Li, Xiaowei Li, “Reliable Network-on-Chip Router for Crosstalk and Soft Error Tolerance”,

Proc. of IEEE Asian Test Symposium (ATS), November 24-27, 2008, Sapporo, Japan, pp.438-443

71. F. Wang, Y. Hu, Y. Huang, J. Ye, Xiaowei Li, “Observation Point Oriented Deterministic Diagnosis

Pattern Generation (DDPG) for Chain Diagnosis”, Proc. of IEEE Asian Test Symposium (ATS), November

24-27, 2008, Sapporo, Japan, pp.185-190

72. J. Li, X. Liu, Y. Zhang, Y. Hu, Xiaowei Li, Q. Xu, “On Capture Power-Aware Test Data Compression for

Scan-Based Testing”, Proc. of IEEE International Conference on Computer-Aided Design (ICCAD),

November 10-13, 2008, USA, pp.67-72

73. J. Ye, F. Wang, Y. Hu, Xiaowei Li, “Diagnosis of Mask-Effect Multiple Timing Faults in Scan Chains”,

IEEE International Test Conference (ITC’08), October 28-30, 2008, USA, poster 15

74. F. Wang, Y. Hu, H. Li, Xiaowei Li, Y. Huang, J. Ye, “Deterministic Diagnostic Pattern Generation

(DDPG) for Compound Defects”, Proc. of IEEE International Test Conference (ITC), October 28-30,

2008, USA, paper 14.1

75. M. Zhang, H. L, Xiaowei Li, “Multiple Coupling Effects Oriented Path Delay Test Generation”, Proc. of

IEEE VLSI Test Symposium (VTS), April 27-May 1, 2008, San Diego, USA, pp.383-388

76. Y. Zhang, H. Li, Xiaowei Li, Y. Hu, “Codeword Selection for Crosstalk Avoidance and Error Correction

on Interconnects”, Proc. of IEEE VLSI Test Symposium (VTS), April 27-May 1, 2008, San Diego, USA,

pp.377-382

77. J. Li, Q. Xu, Y. Hu, Xiaowei Li, “iFill: An Impact-Oriented X-Filling Method for Shift- and

Capture-Power Reduction in At-Speed Scan-Based Testing”, Proc. of IEEE Design, Automation and Test

in Europe (DATE), March 10-14, 2008, Munich, Germany, pp.1184-1189

78. L. Zhang, Y. Han Q. Xu, Xiaowei Li, “Defect Tolerance in Homogeneous Manycore Processors Using

Core-Level Redundancy with Unified Topology ”, Proc. of IEEE Design, Automation and Test in Europe

(DATE), March 10-14, 2008, Munich, Germany, pp.891-896

79. F. Wang, Y. Hu, H. Li, Xiaowei Li, “A Design-for-Diagnosis Technique for Diagnosing both Scan Chain

Faults and Combinational Circuit Faults”, Proc. of IEEE Asia and South Pacific Design Automation

Conference (ASP-DAC’08), Seoul, Korea, January 21-24, 2008, pp.571-576

80. J. Li, Q. Xu, Y. Hu, Xiaowei Li, “On Reducing Both Shift and Capture Power for Scan-Based Testing”,

Proc. of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC’08), Seoul, Korea,

January 21-24, 2008, pp.653-658

81. X. Fu, H. Li, Y. Hu, Xiaowei Li, “Robust Test Generation for Power Supply Noise induced Path Delay

Faults”, Proc. of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC’08), Seoul,

Korea, January 21-24, 2008, pp.659-662

82. J. Li, Q. Xu, Y. Hu, Xiaowei Li, “Channel Width Utilization Improvement in Testing NoC-Based Systems

for Test Time Reduction”, Proc. of 4th IEEE International Symposium on Electronic Design, Test &

Applications (DELTA2008), January 23-25, 2008, Hong Kong, pp.26-31

83. F. Wang, Y. Hu, Xiaowei Li, “Adaptive Diagnostic Pattern Generation for Scan Chains”, Proc. of 4th

IEEE International Symposium on Electronic Design, Test & Applications (DELTA2008), January 23-25,

2008, Hong Kong, pp.129-132

10

84. D. Wang, R. Li, Y. Hu, H. Li, Xiaowei Li, “A Case Study on At-Speed Testing for A Gigahertz

Microprocessor”, Proc. of 4th IEEE International Symposium on Electronic Design, Test & Applications

(DELTA2008), January 23-25, 2008, Hong Kong, pp.326-331

85. M. Zhang, H. Li, Xiaowei Li, “Static Crosstalk Noise Analysis with Transition Map”, Proc. of 4th IEEE

International Symposium on Electronic Design, Test & Applications (DELTA2008), January 23-25, 2008,

Hong Kong, pp.462-465

86. H. Liu, H. Li, Y. Hu, Xiaowei Li, “A scan-based delay test method for reduction of overtesting”, Proc. of

4th IEEE International Symposium on Electronic Design, Test & Applications (DELTA2008), January

23-25, 2008, Hong Kong, pp.521-526

87. J. Li, Y. Hu, Xiaowei Li, “Impact-Factor-Guided X-Filling for Peak Power Reduction during Test”, Proc.

of IEEE Region 10 Conference (TENCON’07), Oct. 30-Nov. 2, 2007, Taipei

88. J. Li, Y. Hu, Xiaowei Li, “Test Cost Efficiency Exploration for CMT Processors”, Proc. of IEEE Region

10 Conference (TENCON’07), Oct. 30-Nov. 2, 2007, Taipei

89. D. Wang, Y. Xie, Y. Hu, H. Li, Xiaowei Li, “Hierarchical Fault Tolerance Memory Architecture for

3-Dimension Interconnection”, Proc. of IEEE Region 10 Conference (TENCON’07), Oct. 30-Nov. 2,

2007, Taipei

90. S. Lei, Y. Han, Xiaowei Li, “A Frequency Analysis Model for Propagation of Transient Errors in

Combinational Logic”, Proc. of IEEE Asian Test Symposium (ATS), Oct. 2007, Beijing, pp.223-228

91. M. Zhang, H. Li, Xiaowei Li, “Test Generation for Crosstalk Glitches Considering Multiple Coupling

Effects”, Proc. of IEEE Asian Test Symposium (ATS), Oct. 2007, Beijing, pp.259-264

92. D. Wang, X. Fan, X. Fu, H. Liu, K. Wen, P. Li, H. Li, Y. Hu, Xiaowei Li, “The Design-For-Testability

Features of Godson-2 Microprocessor”, Proc. of IEEE International Test Conference (ITC), Oct. 2007,

USA, Paper 9.2

93. L. Zhang, H. Li, Xiaowei Li, “A Routing Algorithm for Random Error Tolerance in Network-on-chip”,

Proc. of 12th International Conference on Human-Computer Interaction (HCI’07), Beijing, July, 2007,

pp.1210-1219

94. J. Li, Q. Xu, Y. Hu Xiaowei Li, “On Improving Channel Utilization in Testing NoC-Based Systems”,

Digest of Papers, IEEE European Test Symposium, May 2007, Germany, pp.53-58

95. Y. Zhao, T. Lv, L. Liu, H. Li, Xiaowei Li, “A Novel Circuit-Oriented SAT Engine and Its Application to

Unbounded Model Checking”, Informal Digest of Papers, IEEE European Test Symposium, May 2007,

Germany, pp.41-46

96. L. Xie, Y. Xu, Xiaowei Li, Y. Zhu, "A Lightweight Scheme for Trust Relationship Establishment in

Ubiquitous Sensor Networks", Proc. of 6th IEEE International Conference on Computer and Information

Technology (CIT'06), Nov.2006, pp.229-234

97. T Liu, H Li, Xiaowei Li, Y Han, “Fast Packet Classification using Group Bit Vector”, Proc. of 49th

annual IEEE Global Telecommunications Conference (Globecom2006), Nov 27 – Dec 1, 2006, San

Francisco

98. Y. Hu, C. Li, J. Li, Y. Han, Xiaowei Li, W. Wang, H. Li, L.-T. Wang, X. Wen, “Test Data Compression

Based on Clustered Random Access Scan”, Proc. of IEEE Asian Test Symposium (ATS06), Nov.20-23,

2006, Fukuoka, Japan, pp.231-236

99. T. Lv, L. Liu, Y. Zhao, H. Li, Xiaowei Li, “An Observability Branch Coverage Metric Based on Dynamic

Factored Use-Define Chains”, Proc. of IEEE Asian Test Symposium (ATS06), Nov.20-23, 2006, Fukuoka,

Japan, pp.89-94

100. J. Li, Y. Hu, Xiaowei Li, “A Scan Chain Adjustment Technology for Test Power Reduction”, Proc. of

IEEE Asian Test Symposium (ATS06), Nov.20-23, 2006, Fukuoka, Japan, pp.11-16

101. L. Zhao, C. Xu, Y. Xu, Xiaowei Li, “Energy-Aware QoS Control for Wireless Sensor Network”, Proc. of

11

1st IEEE Conference on Industrial Electronics and Applications (ICIEA 2006), May 24-26, 2006,

Singapore, pp.1536-1541

102. G. Huang, Xiaowei Li, J. He, “Dynamic Minimal Spanning Tree Routing Protocol for Large Wireless

Sensor Networks”, Proc. of 1st IEEE Conference on Industrial Electronics and Applications (ICIEA

2006), May 24-26, 2006, Singapore, pp.1531-1535

103. Y. Yang, L. Huang, Q. Zhou, Y. Xu, Xiaowei Li, “SNAMP: A Multi-sniffer and Multi-view Visualization

Platform for Wireless Sensor Networks”, Proc. of 1st IEEE Conference on Industrial Electronics and

Applications (ICIEA 2006), May 24-26, 2006, Singapore, pp.1523-1526

104. C. Xu, L. Zhao, Y. Xu, Xiaowei Li, “Time Synchronization Simulator and its application”, Proc. of 1st

IEEE Conference on Industrial Electronics and Applications (ICIEA 2006), May 24-26, 2006, Singapore,

pp.1517-1522

105. L. Zhao, C. Xu, T. Zhang, Y. Xu, Xiaowei Li, “Cluster based Energy Efficient Scalable Resolution for

Wireless Sensor Network”, Proc. of International Conference on Sensing, Computing and Automation

(ICSCA’06), May 8-11, 2006, Chongqing, pp.2988-2993

106. C. Xu, L. Zhao, Y. Xu, Xiaowei Li, “Broadcast Time Synchronization Algorithm for Wireless Sensor

Networks”, Proc. of International Conference on Sensing, Computing and Automation (ICSCA’06), May

8-11, 2006, Chongqing, pp.2366-2371

107. G. Huang, Xiaowei Li, J. He, “Binary Tree Routing for Parallel Data Gathering in Sensor Networks of

Smart Home”, Proc. of International Conference on Sensing, Computing and Automation (ICSCA’06),

May 8-11, 2006, Chongqing, pp.792-797

108. G. Huang, Xiaowei Li, J. He, “Clustering Versus Evenly Distributing Energy Dissipation in Wireless

Sensor Routing for Prolong Network Lifetime”, Proc. of International Conference on Computational

Science 2006 (ICCS’06), Workshop on Wireless and Mobile Systems (WMS), UK, May 28-31, 2006,

Volume 3992 / 2006, pp.1069-1072

109. G. Huang, Xiaowei Li. “Energy-Efficiency Analysis of Cluster-Based Routing Protocols in Wireless

Sensor Network”, Proc. of IEEE Aerospace Conference, March 4-11, 2006, pp.1-7

110. J. Dong, Y. Hu, Y. Han, Xiaowei Li, “An On-chip Combinational Decompressor for Reducing Test Data

Volume”, Proc. of IEEE International Symposium on Circuits and Systems (ISCAS’06), May 21-24, 2006,

Greece, pp.1459-1462

111. H. Li, P. Shen, Xiaowei Li, “Robust Tests Generation for Precise Crosstalk-induced Path Delay Faults”,

Proc. of IEEE VLSI Test Symposium (VTS), April 30-May 4, Berkeley, USA, 2006, pp.300-305

112. H. Chen, P. Deng, Y. Xu, Xiaowei Li, “A Novel Localization Scheme Based on RSS Data for Wireless

Sensor Networks”, Proc. of International Workshop on Sensor Networks (IWSN), Jan.16-18, 2006,

pp.315-320

113. Y. Hu, Y. Han, Xiaowei Li, “Compression/Scan Co-Design to Reduce Test Data Volume, Scan-in Power

Dissipation and Test Application Time”, Proc. of IEEE Pacific-Rim Dependable Computing (PRDC),

Dec.12-14, 2005, Changsha, pp.175-182

114. Y. Han, S. Swaminathan, Y. Hu, A. Chandra, Xiaowei Li, “Scan Data Volume Reduction Using

Periodically Alterable MUXs Decompressor”, Proc. of IEEE Asian Test Symposium (ATS), Dec.17-21,

2005, Kolkata, India, pp.373-377

115. P. Shen, H. Li, Y. Xu, Xiaowei Li, “Non-robust Test Generation for Crosstalk-Induced Delay Faults”,

Proc. of IEEE Asian Test Symposium (ATS), Dec.17-21, 2005, Kolkata, India, pp.120-123

116. G. Huang, G. Zhang, Xiaowei Li and Yunzhan Gong, “A State Machine for Detecting C/C++ Memory

Faults”, Proc. of IEEE Asian Test Symposium (ATS), Dec.17-21, 2005, Kolkata, India, pp.82-87

117. G. Zhang, R. Chen, Xiaowei Li, C. Han, “The Automatic Generation of Basis Set of Path in Path Testing”,

Proc. of IEEE Asian Test Symposium (ATS), Dec.17-21, 2005, Kolkata, India, pp.46-49

12

118. Y. Xu, C. Xu, Xiaowei Li, “Power Property Analysis for CMOS Integrated Circuits”, Proc. of IEEE 6th

International Conference on ASIC (ASICON 2005), Shanghai, China, October 24-27, 2005, pp.960-961

119. Y Xu, L Liu, P Shen, T Lv, Xiaowei Li, “Processor Design Considerations for Wireless Sensor Network”,

Proc. of IEEE 6th International Conference on ASIC (ASICON 2005), Shanghai, China, October 24-27,

2005, pp.255-257

120. X Chang, D Fan, Y Han, Z Zhang, Xiaowei Li, “Fast algorithm for leakage power reduction by input

vector control”, Proc. of IEEE 6th International Conference on ASIC (ASICON 2005), Shanghai, China,

October 24-27, 2005, pp.98-103

121. G. Huang, Xiaowei Li, Y. Gong. “Upper Bound on the Number of Sensor Nodes in a Cluster Club of

Wireless Network”, Proc. of Future Telecommunications Conference, Beijing, Oct. 14, 2005, pp.217-221

122. L. Zhao, C. Xu, Y. Xu, Xiaowei Li, “Energy-Aware Design Considerations for Wireless Sensor

Networks”, Proc. of the First International Workshop on Sensor Networks and Applications (SNA’05),

October 21–22 2005, Beijing, China, pp.53-56

123. C. Xu, L. Zhao, Y. Xu, Xiaowei Li, “Simsync: An Effective Time Synchronization Simulator for Sensor

Networks”, Proc. of the first IEEE international Workshop on Sensor Network and Applications (SNA’05),

October 21–22 2005, Beijing, China, pp.2-5

124. Y. Xu, L. Liu, P. Shen, T. Lv, Xiaowei Li, “Low Power Processor Design for Wireless Sensor Network

Applications”, Proc. of IEEE International Conference on Wireless Communications, Networking and

Mobile Computing (WCNMC2005), Wuhan China, Sept.23-26, 2005, pp.921-924

125. H. Chen, P. Deng, Y. Xu, Xiaowei Li, “A Robust Location Algorithm with Biased Extended Kalman

Filtering of TDOA Data for Wireless Sensor Networks”, Proc. of IEEE International Conference on

Wireless Communications, Networking and Mobile Computing (WCNM C2005), Wuhan China, September

23-26, 2005, pp.883-886

126. Y. Han, Y. Hu, H. Li, Xiaowei Li, “Embedded Test Resource to Reduce the Required Memory and

Channels of Tester,” Proc. of IEEE Instrumentation and Measurement Technology Conference (IMTC),

May 2005, Ottawa, Canada, pp.190-195

127. J. Li, Y. Han, Xiaowei Li, “Deterministic and Low Power BIST Based on Scan Slice Overlapping”, Proc.

of IEEE International Symposium on Circuits and Systems (ISCAS), May 2005, Kobe, Japan,

pp.5670-5673

128. Y. Tan, Y. Han, Xiaowei Li, F. Luo, Y. Chen, “Validation Analysis and Test Flow Optimization of VLSI

Chip”, Proc. of IEEE International Symposium on Circuits and Systems (ISCAS), May 2005, Kobe, Japan,

pp.5666-5669

129. W. Lu, T. Lv, X. Yang, Xiaowei Li, “An Efficient RTL Observability Evaluation and Vector Generation

Method”, Digest of Papers, IEEE European Test Symposium (ETS), May 22-25, 2005, Tallinn, Estonia,

pp.97-102

130. Y. Han, Xiaowei Li, “Using MUXs Network to Hide Bunches of Scan Chains”, Proc. of IEEE

International Symposium on Quality Electronic Design (ISQED2005), San Jose, pp.238-243

131. S. Gong, H. Li, Y. Xu, T. Liu, Xiaowei Li, “Design of an Efficient Memory Controller for Network

Processor”, Proc. of IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 18-21,

2005, Shanghai, pp.897-900

132. Y. Xu, Z. Luo, J. Chen, Xiaowei Li, “Vector Extraction for Average Total Power Estimation”, Proc. of

IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Jan. 18-21, 2005, Shanghai,

pp.1086-1089

133. Y. Han, Y. Hu, H. Li, Xiaowei Li, “Theoretic Analysis and Enhanced X-Tolerance of Test Response

Compact based on Convolutional code”, Proc. of IEEE Asia and South Pacific Design Automation

Conference (ASP-DAC), Jan. 18-21, 2005, Shanghai, pp.53-58 (Best Paper Candidate)

13

134. Y. Han, Y. Hu, H. Li, Xiaowei Li, A. Chandra, “Response Compaction for Test Time and Test Pins

Reduction Based on Advanced Convolutional Codes”, Proc. of IEEE Int'l Symposium on Defect and Fault

Tolerance in VLSI Systems (DFT'04), October 11-13, 2004, France, pp.298-305

135. Y. Xu, J. Chen, Z. Luo, Xiaowei Li, “Compacted Simulation: A New Leakage Current Estimation

Method”, Proc. of IEEE 7th International Conference on Solid-State and Integrated-Circuit Technology

(ICSICT’04), October 18-21, 2004, Beijing, pp.1022-1025

136. G. Li, M. Shao, Xiaowei Li, “Circuit Width Based Heuristic Technique of Boolean Reasoning”, Proc. of

IEEE 13th Asian Test Symposium (ATS’04), Kenting, November 15-17, 2004, pp.336-341

137. Y. Hu, Y. Han, H., T. Lv, Xiaowei Li, “Pair Balance-Based Test Scheduling for SOCs”, Proc. of IEEE

13th Asian Test Symposium (ATS’04), Kenting, November 15-17, 2004, pp.236-241

138. Y. Han, Y. Hu, H. Li, Xiaowei Li, “Rapid and Energy-Efficient Testing for Embedded Cores”, Proc. of

IEEE 13th Asian Test Symposium (ATS’04), Kenting, November 15-17, 2004, pp.8-13

139. Y. Han, Xiaowei Li, “Simultaneous Reduction of Test Data Volume and Testing Power For Scan-based

Test”, Proc. of the 2004 International Multi-Conference in Computer Science and Engineering (VLSI),

June 21-24, 2004, Las Vegas, Nevada, USA, pp.374-379

140. Y. Xu, Z. Luo, Xiaowei Li, “A Maximum Total Leakage Current Estimation Method”, Proc. of IEEE

International Symposium on Circuits and Systems (ISCAS2004), Vancouver, May 23-26, 2004, Volume 2,

pp.757-760

141. M. Shao, G. Li, Xiaowei Li, “A SAT-based Algorithm of Verification for Port Order Fault”, Proc. of IEEE

12th Asian Test Symposium (ATS’03), November 16-19, 2003, Xi’an, pp.478-481

142. G. Li, M. Shao, Xiaowei Li, “Design Error Diagnosis Based on Verification Techniques”, Proc. of IEEE

12th Asian Test Symposium (ATS’03), November 16-19, 2003, Xi’an, pp.474-477

143. Y. Han, Y. Xu, H. Li, Xiaowei Li, A Chandra, “Test Resource Partitioning Based on Efficient Responses

Compaction for Test Time and Test Channels Reduction”, Proc. of IEEE 12th Asian Test Symposium

(ATS’03), November 16-19, 2003, Xi’an, pp.440-445 (Best Paper Award)

144. Y. Xu, Z. Luo, Z. Chen, Xiaowei Li, “Average Leakage Current Macromodeling for Dual-threshold

Voltage Circuits”, Proc. of IEEE 12th Asian Test Symposium (ATS’03), November 16-19, 2003, Xi’an,

pp.196-201

145. H. Li, Y. Zhang, Xiaowei Li, “Delay Test Pattern Generation considering Crosstalk-induced Effects”,

Proc. of IEEE 12th Asian Test Symposium (ATS’03), November 16-19, 2003, Xi’an, pp.178-183

146. T. Lv, J. Fan, Xiaowei Li, “An Efficient Observability Evaluation Algorithm Based on Factored Use-Def

Chains”, Proc. of IEEE 12th Asian Test Symposium (ATS’03), November 16-19, 2003, Xi’an, pp.161-166

147. Z. Luo, Y. Xu, Y. Han, Xiaowei Li, “Maximum Power-up Current Estimation of Power-Gated Circuits”,

Proc. of 5th International Conference on ASIC (ASICON’03), October 21-24, 2003, Beijing, pp.1243-1246

148. Y. Xu, Z. Luo, Z. Chen, Xiaowei Li, “Minimum Leakage Pattern Generation Using Stack Effect”, Proc. of

5th International Conference on ASIC (ASICON’03), October 21-24, 2003, Beijing, pp.1239-1242

149. Y. Xu, T. Lv, W. Lu, X. Yang, H. Li, Xiaowei Li, “Advanced Topics of DFT Technologies in a

General-Purposed CPU Chip”, Proc. of 5th International Conference on ASIC (ASICON’03), October

21-24, 2003, Beijing, pp.1179-1182

150. R. He, Xiaowei Li, Y. Gong, “A Scheme for Low Power BIST Test Pattern Generator”, Proc. of 5th

International Conference on ASIC (ASICON’03), October 21-24, 2003, Beijing, pp.1136-1139

151. G. Li, M. Shao, Xiaowei Li, “Using SAT for Verification in the Presence of Unknowns”, Proc. of 5th

International Conference on ASIC (ASICON’03), October 21-24, 2003, Beijing, pp.319-322

152. Y. Han, Y. Xu, Xiaowei Li, “Co-Optimization For Test Data Compression and Testing Power Based On

Variable-Tail Code”, Proc. of 5th International Conference on ASIC (ASICON’03), October 21-24, 2003,

Beijing, pp.105-108

14

153. Z. Luo, Xiaowei Li, H. Li, S. Yang, Y. Min, “Test Power Optimization Techniques for CMOS Circuits”,

Proc. of IEEE Asian Test Symposium (ATS2002), Nov. 18-20, 2002, Guam, pp.332-337

154. Z. Yin, Y. Min, Xiaowei Li, “An Approach to RTL Fault Extraction and Test Generation”, Proc. of IEEE

Asian Test Symposium (ATS2001), Nov.19-21, 2001, Kyoto, pp.219-224

155. Xiaowei Li, H. Li, Y. Min, “Reducing Power Dissipation during At-speed Test Application”, Proc. of

IEEE Int'l Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'01), October 24-26, 2001,

San Francisco, USA, pp.116-121

156. Xiaowei Li, T.Masuzawa, H.Fujiwara, “Strong Self-testability for Data Path High-Level Synthesis”, Proc.

of IEEE Asian Test Symposium (ATS2000), Dec. 4-6, 2000, Taipei, pp.229-234

157. Xiaowei Li, P.Y.S.Cheung, “An Approach to Behavioral Synthesis for Loop-Based BIST”, Proc. of IEEE

1999 International Symposium on Circuits and Systems (ISCAS'99), May 30-June 2, 1999, Florda, USA,

pp.374-377

158. Xiaowei Li, P.Y.S.Cheung, “An Effective BIST Scheme for Delay Testing”, Proc. of IEEE Int'l

Symposium on Circuit and System (ISCAS’98), June, 1998, Monterey, USA, pp.II-288-291

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