c01009+-+digital+system+-+chapter+5

Chng 5

Linh Kin Mch Tun T

CO1009 Digital Systems Chng 5: Linh Kin Mch Tun T

2

Ni dung

Mch tun t

Phn t nh Latch

Clock v Clocked-FlipFlop

ng b

Ng nhp bt ng b.

Vn Timing

ng dng FlipFlop


3

Gii thiu

Ma ch t hp khng c b nh

Hu ht cc h thng s c to thnh t mch t hp

v cc phn t nh mch tun t.


4

Gii thiu (tt)

Feedback


5

Gii thiu (tt)

FF c 2 trng thi

SET : Q=1, Q=0 - trng thi HIGH ho c 1.

CLEAR/RESET: Q=0, Q=1 - trng thi LOW ho c 0

FF cn c tn gi khc l Latch (ci)


6

NAND Gate Latch

FF c ba n nh t c th c xy dng t 2 c ng NAND ho c 2c ng NOR

FF to thnh t 2 cng NAND c gi l NAND gate latch haylatch

Ng ra cng NAND-1 ni vo ng nhp ca cng NAND-2 vngc li

Output c t tn la Q va Q (Q va Q lun ngc nhau trongi u ki n bi nh thng X/X, A/A...)

Co 2 input

SET input: set Q = 1 CLEAR input : set Q = 0


7

NAND Gate Latch

Recalling: Khi SET = 1 v CLEAR = 1 th ma ch NAND

latch c 2 trng hp c th xy ra

Ng xut ph thuc vo trng thi cc ng nhp trc


8

NAND Gate Latch

Setting - xy ra khi SET input c mt xung xung 0 trongkhi CLEAR input vn bng 1 Trng hp Q = 0


9

NAND Gate Latch

Setting - xy ra khi SET input c mt xung xu ng 0 trongkhi CLEAR input vn bng 1 Trng hp Q = 1


10

NAND Gate Latch

Clearing - xy ra khi CLEAR input c mt xung 0 trongkhi SET input vn bng 1 Trng thi Q = 0


11

NAND Gate Latch

Clearing - xy ra khi CLEAR input c mt xung 0 trongkhi SET input vn bng 1 Trng thi Q = 1


12

NAND Gate Latch

Khi SET = CLEAR = 0, gi tr nh ca Latch khng th

on trc c. Ty thuc vo tn hiu no ln 1

trc.

V vy, trong NAND latch iu kin SET = CLEAR = 0

khng c s dng


13

NAND Gate Latch


14

Biu din tng ng


15

NOR Gate Latch


16

Bi tp

V tn hiu Q.

x

y


17

Bi tp

V ng ra Q.


18

ng b v bt ng b

Mt h thng s c th hot ng trong 2 ch

Bt ng b (Asynchronous)

ng b (Synchronous)

H thng b t ng b: output c th thay i trng thi

b t k lc no khi input thay i

H thng ng b: output thay i trng thi ti mt

thi im xc nh bi tin hiu clock (Clock signal)


19

Xung s


20

Clock Signals

Tn hiuClock c phn b n t t c cc phn ca h

thng. Output c th thay i ch khi tn hiu clock

chuy n trng thi

Tn hiu clock chuyn trng thi

0 ln 1: cnh ln (Positive going transition PGT).

1 xu ng 0: cnh xu ng (Negative going transition NGT).


21

Clocked FFs

Hu ht cc h thng s u hot ng ch ng

b (synchronous)

D thit k

D sa cha

Cc h thng ny c xy dng t cc phn t c bn

Clocked FF.

Clocked FF c thi t k khi c s thay i tra ng

thi ca clock th trng thi ca output cng thay i

theo.


22

Clocked Flip-Flops

Clocked FFs c mt tn hiu clock c t tn l CLK,CP, hoc CK. Hu ht cc tn hiu CLK l tn hiu kchcnh (egde triggered).

Clocked FFs c 1 hoc nhiu tin hi u i u khi n Cc tn hiu iu khin khng nh hng n trng thi

ca output cho n khi c s thay i trng thi ca clockxy ra.

Tn hiu Clock: quyt nh thi im (WHEN)

Tn hiu iu khin: quyt nh trng thi (WHAT)


23

Clocked Flip-Flops


24

FF Vn thi gian

Setup and Hold time


25

Clocked SR Flip-Flops


26



27



28

Cu to mch - edge triggered SR FF


29

Cu to mch - edge triggered SR FF


30

JK Flip-Flops

mch ci SC / SR C 2 ng vo khng c ng thi mang gi tr 1

Tn ti trng thi bt nh.

Khng ph hp vi thc t thit k cn ci tin


31

JK Flip-Flops


32

JK Flip-Flops

0

10

1

1

1

1

01

0


33

JK Flip-Flops

1

01

0

1

1

0

10

1


34

Bi tp

Khi mt vi x l mun truy xut d liu b nh ngoi,

n tch cc tn hiu iu khin RD. Bit RD tch cc

mc thp v Datasheet cho bit xung iu khin tn

hiu ny c tw = 50ns, tr = 15ns, tf = 10ns. Hy v xung

ny theo trc thi gian.


35

Bi tp

V tn hiu ng ra Q ca JK Flipflop trong cc trng

hp.

J-K FF vi clock cnh ln.

J-K FF vi clock cnh xung.

Xem nh tH = 0.


36

Tng quan

Mch tun t

Phn t nh Latch

Clock v Clocked-FlipFlop

ng b

Ng nhp bt ng b.

Vn Timing

ng dng FlipFlop

36


37

D Flip-Flops

37


38

D Flip-Flops

Hi n thc D FF t JK FF

38


39

D Latch

39


40

Asynchronous Inputs (bt ng b)

Ng nhp ng b (synchronous): S, C, J, K, D

Tin hiu i u khi n (control inputs).

Nhng thay i ca chng ch nh hng n ng output khi

c tn hiu ng b ca CLK.

Ng nhp b t ng b (asynchronous inputs)

Hot ng c lp vi cc tn hiu input ng b v tn hiu

CLK (Bt k lc no v khng quan tm n nhng input

khc).

Set FF ln trng thi 1

Clear FF v trng thi 0

40


41



42



43

FF c tnh thi gian

Setup and Hold time

43


44

FF c tnh thi gian (tt)

Tr lan truyn (Propagation delay)

Gi tr ti a (Maximum): vi ns n 100ns

44


45


Maximum clock frequency.

Clock pulse high or low times.

Asynchronous active pulse width.

Clock transition times.

45


46


46


47

FF Vn thi gian


48

FF Vn thi gian (tt)

48


49

Bi tp

V tn hiu Q ca D latch

49


50

Bi tp

a) Q=0, tm thi gian Q=1 khi c CLK vi 7474?

b) Q=1, thi gian Q=0 khi khi c tn hiu CLR=0 vi 74HC112.

c) Thi gian ngn nht cn tch cc CLR Q=0 trn 74LS112.50


51

51


52

ng dng FF Lu tr d liu( register )

Chng rung

ng b d liu

Truyn d liu

Thanh ghi dch

Chia tn s

Biu din trng thi

Mod number52


53

Chng rung

53


54

ng b d liu

54


55

ng b d liu (tt)

55


56

Pht hin ng nhp tun t

Pht hin thay i ng thi.

Pht hin thay i tun t.


57

Data transfer

Synchonous transfer

Asynchronous transfer


58

Parallel transfer


59

Parallel transfer


60

Thanh ghi dch


61

Thanh ghi dch


62

Chia tn s


63

m v chuyn trng thi

63


64

m v chuyn trng thi (tt)

Mod number

MOD number: chi s trang thai trong chui m .

B m vi du trc co 23=8 trang thai khac nhau(000

ti 111). B m na y c goi la b m MOD-8.

Nu co 4 FF thi chui trang thai se m t 0000 n

1111(co 16 trang tha i). Va c goi la b m MOD-16.

B m MOD-2N co kha nng m ti 2N -1 sau o quay

v trang thai 0.


65

Bi tp

Da vo nguyn l hot ng ca mch trn, hy in y vo

bng s tht di y.

CLK

SET

CLEAR

QOUTPUT

ORNOT

NOT

NOT

OR

ORNAND

NAND

SET CLR CLK Q

0 0

0 1

1 0

1 1


66

Bi tp

Da vo nguyn l hot ng ca mch trn, hy in

y vo bng s tht di y

QSET

CLK

CLEAR

NOT

74LS04

NOT

74LS04

NOR

74LS02

NOR

74LS02

NOR

74LS02

NOR

74LS02OR

74LS32

SET CLR CLK Q

0 0

0 1

1 0

1 1


67

Bi tp

Cho s kt ni 2 J-K Flip-Flop nh hnh v. Xc nh tn s

ca ng xut A v ng xut B bit cc tn hiu J v K ca 2 Flip-

Flop u bng 1.

1

1 1

1

10 KHz

A BSJCPK

R

Q_Q

SJCPK

R

Q_Q


68

Bi tp

Hy v mch tun t tng ng vi bng s tht di

y

SET CLR CLK Q

0 0 NC

0 1 1

1 0 0

1 1 Invalid


69

Bi tp

Hy v biu din xung s tha mn yu cu sau.

a. Xung mc thp vi tr=20ns, tf=5ns, v tw=50ns.

b. Xung mc cao vi tr=5ns, tf=1ns, tw= 25ns.

c. Xung tw=1ms vi cnh ln xut hin mi 5ms. Hy xc

nh tn s ca tn hiu ny.


70

Bi tp

Hy thit k.

a. JK Flipflop t D Flipflop

b. T Fliplfop t D Flipflop

c. T Flipflop t JK Flipflop

T CLK Q

0 Q

1 Q

T Q

Q


71

Bi tp

a. Thi gian asynchronous clear ca 74LS112.

b. Thi gian asynchronous set ca 74HC112.

c. Thi gian ngn nht gia 2 ln tch cc clock ca 7474.

d. Thi gian cn thit 7474 synchronous chuyn t 0->1


72

Bi tp

Gi s ban u A,B,C bng 0. Bit rng ng xut Y s

bng 1 khi A,B,C bng 1 sau mt s ln thay i.

a. Hy xc nh cc bc thay i ca A,B,C Y=1.

b. Gii thch s cn thit xung LOW ca tn hiu Start.

c. Thay th JK FF bng D FF.


73

Bi tp

Tr li cc cu hi sau

a. Bao nhiu FF cn thit hin thc mt mch m

nh phn bt ng b t 0 1023.

b. Xc nh tn s g ra ca FF cui cng ca counter

ny nu tn s ng vo ca FF u tin l 2Mhz.

c. Mod number ca b m ny l g?

d. Nu ban u gi tr l 0, sau 2060 xung, gi tr ca

counter l bao nhiu.


74

Bi tp

Mt mch m nh phn vi xung clock iu khin 256

kHz. Bit rng xung clock ng xut ca FF cui cng c

tn s 2kHz.

a. Xc nh MOD number ca mch m ny.

b. Xc nh khong gi tr m.

c. V mch m s dng D FF


75

Bi tp

Mt siu th va lp t th nghim mt h thng m s

lng khch. H thng gm cc sensor t ti cng vo siu

th. Mi khi pht hin mt khch i vo. Senor s gi mt

xung n mt mch m nh phn 10 bit. n cui ngy,

nhn vin k thut kim tra gi tr ca b m v thy kt

qu 00000110012 = 2510. Nhn vin cho rng kt qu khng

chnh xc. V hm siu thi c s kin v thu ht rt ng

khch.

a. Gi s sensor v mch m khng c li, hy gii thch kt

qu ny.

b. Hy d on s lng khch thc s ca siu th ngy hm

.


76

Bi tp

Mt MCU s dng 16 pin nh a ch b nh ngoi.

Bit rng 8 pin tng ng vi 8 bit a ch thp cng

c dng nh ng nhp c kt qu t b nh

ngoi. Trong qu trnh truy xut b nh ngoi, 16 bit

a ch khng c php thay i. Do ngi ta dng

mt D-lach 8 bit cht 8 bit a ch thp. Hy v kt

ni pin ca MCU vi D-Latch sao cho mi khi tn hiu

ALE = 0, 8 bit thp ca a ch s khng i.


77

Bi tp

c01009+-+digital+system+-+chapter+5

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