cc2510-ln2-combinlogic

7/27/2019 CC2510-LN2-CombinLogic

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CC2510 Combinational Logic Page 1

1998-2007, C. J. Kikkert, James Cook University

CC2510 Digital Logic and Computing Methods

Combinational Logic and Boolean Algebra

Logic Functions(Wakerley Ch 4.1)

AND produces an output 1 if input A AND input B are both 1

A B X

0 0 0

0 1 0

1 0 0

1 1 1

In Boolean Algebra the AND symbol is denoted by a or a In ABEL the AND symbol is denoted by &

In VHDL the AND symbol is denoted by and

Boolean X= A BABEL X = A&B ;VHDL X := A and B ;

Schematic

Switch configuration

OR produces an output 1 if input either A OR input B (or both) are 1

A B X

0 0 0

0 1 1

1 0 1

1 1 1

In Boolean Algebra the OR symbol is denoted by a + or a In ABEL the OR symbol is denoted by #In VHDL the OR symbol is denoted by or

Boolean X= A + BABEL X = A#B ;VHDL X := A or B ;

A B


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Schematic

Switch configuration

NOT inverts the input

A X0 1

1 0

The NOT symbol is denoted by a , by a/, or by a !, depending on the application

Boolean X=A/ABEL X=!A ;VHDL X := not A ;

Schematic

Many logic circuits include inversions at the output of AND and OR functions,resulting in NAND and NOR functions. (Typically NAND gates are faster than ANDgates)

NAND (NOT AND) produces an output 0 if input A AND input B are both 1

A B X

0 0 1

0 1 1

1 0 11 1 0

Boolean X=(AB) /ABEL X = !(A&B) ;VHDL X := A nand B ; which can also be written as X := not ( A and B) ;

Schematic

A

B


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NOR (NOT OR) produces an output 0 if input either A OR input B (or both) are 1

A B X

0 0 1

0 1 0

1 0 01 1 0

Boolean X= (A+B)/

ABEL X = !( A#B ) ;VHDL X := A norB ; which can also be written as X := not ( A or B) ;

Schematic

Representing a Logic FunctionTruth table

The input and corresponding output values are presented in a table, as above for thebasic logic gates. It is very easy to indicate the requirements, but it is not so easy tothen realise the function in hardware. To cover all the possibilities, for a 3 inputCircuit, 8 rows are requires, for a 10 input circuit 1024 rows are required. The truthtable is only manageable for less than about 5 inputs.

The statement I can catch a fish if I have a fishing rod, worms and if the fish have

not yet eaten can be represented as follows:

Fishing Rod Worms Fish Full Catch

0 0 0 0

0 0 1 0

0 1 0 0

0 1 1 0

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 0

Truth table for catching fish

Boolean Algebra representation

The output is described by a Boolean algebra expression as indicated above. The onlyoperators normally used are AND, OR and NOT. This form of expression can beapplied to a logic circuit with many inputs.

Catch = Rod Worms Full/


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F = ((X+Y/)Z) /+(X/.Y.Z/)

Boolean algebra expressions are very useful in representing logic functions.

Boolean Algebra Theorems(Wakerley Ch4.1.3)

When we design a circuit we must take these specifications and turn them into somehardware with the least complexity and cost. We may have to manipulate theexpressions manually or we may use some tools to do the reductions for us. The waywe manipulate the expressions depends also on the hardware that is available. (NANDgates etc)

Theorems for Boolean Algebra

X + 0 = X X 1 = XX + 1 = 1 X 0 = 0X + X =X X X = X(X/)/ = XX + X/ = 1 X X/ = 0

Commutative Law

X + Y = Y + XX Y = Y X

Associative Law

X + (Y + Z) = (X + Y) + Z = X + Y + ZX (Y Z) = (X Y) Z = X Y Z

Distributive Law

X (Y + Z) = (X Y) + (X Z) = X Y + X ZX + (Y Z) = (X + Y) (X + Z)

Dual Networks

Replacing by + and vice versa and replacing 0 by 1 and vice versa, changes anequation into its dual. If the equation is true, so is its dual.

ExampleX 1 = X dual X+ 0 = X

Useful expressions

X + (X Y) = X X (X + Y) = XX + (X/ Y) = X + Y X (X/ + Y) = X YX/ + (X Y) = X/ + Y X/ (X + Y) = X/ Y(X + Y) (X/ + Z) = X X

/+ X Z + X

/ Y + Y Z = X Z + X

/ Y + Y Z

De Morgans Theorem

If Output = f(A, B, C, D .X, Y, Z, , +)


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then Output/ = f(A/, B/, C/, D/ .X/, Y/, Z/, + , )

Examples:(A B)/ = A/ + B/A B = (A

/+ B

/)

/we can thus make an AND gate using a NOR gate.

A B C D E F G H = ((A B C D)/

+ (E F G H)/

)/

8 input gates are not available in small-scale logic (7400 series) devices but 4 input

NAND gates are and two input NOR gates are. We must thus rearrange the BooleanAlgebra equations to put these into a form, which includes available devices.

Schematic for 8 input AND gate.

Standard forms(Wakerly 4.1.6)In many cases the specification of the logic function is obtained from a truth table.Example: 3 input adder

A B Cin S Cout

0 0 0 0 0 0

1 0 0 1 1 0

2 0 1 0 1 03 0 1 1 0 1

4 1 0 0 1 0

5 1 0 1 0 1

6 1 1 0 0 1

7 1 1 1 1 1

Truth table for Full Adder

S = (A/ B/ Cin) + (A/ B Cin

/ ) + (A B/ Cin/ ) + (A B Cin )

Cout = (A/ B Cin) + (A B

/ Cin ) + (A B Cin/ ) + (A B Cin )

An expression which is made up as an AND function, like the expression A/ B/ Cinis called a minterm.

These can be written in a simplified form as:

S = (1,2,4,7) sometimes the names of the variables are included, as

S = A,B,Cin (1,2,4,7). This is called a canonical sum. It is a sum of standard productterms. A canonical sum is thus the sum of minterms corresponding to each row in atruth table.


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Cout = A,B,Cin (3,5,6,7)

Similarly we can use DeMorgans Theorem to write our adder as:

S/ = (A + B + Cin/) (A + B/ + Cin

) (A/ + B + Cin) (A/ + B/ + Cin

/ )

Cout/ = (A + B/ + Cin/) (A/ + B + Cin/ ) (A/ + B/ + Cin ) (A/ + B/ + Cin/ )

An expression which is made up as an OR function, like the expression A + B + Cin/

is called a maxterm.

This can also be written in a simplified form as:

S/ = A,B,Cin (0,3,5,6)

Cout/= A,B,Cin (0,1,2,4)

This is a product of standard sum terms and is called a canonical product. Canonicalsums are used more often that canonical products. A canonical product is thus a

product of the maxterms corresponding to each row in a truth table.

Consider the 2 input AND gate:

A B X

0 0 0

0 1 0

1 0 0

1 1 1

We can write this as:

X= A B Minterm realisation of X

Applying DeMorgans Theorem to this gives:

X/= A/+ B/ Maxterm realisation of X/, ie X=0

Or we can write this as

X/= (A/ B/) + (A/ B) + (A B/) Minterm realisation of X/, ie X=0

Applying DeMorgans Theorem to this gives:


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X = (A + B) (A + B/) (A/+ B) Maxterm realisation of X, ie X=1

We can thus write any truth table in four standard forms.

Realisation of the X as a Canonical sum (using minterms)Realisation of the X/ as a Canonical sum (using minterms)

Realisation of the X as a Canonical product (using maxterms)Realisation of the X

/as a Canonical product (using maxterms)

Procedure for construction of Logic Circuits1 Using truth tables or otherwise, develop the logic functional requirements for

the circuit to be designed.2 Write down the Boolean Algebra expressions corresponding to the truth

table.

For Medium scale logic (TTL etc)

3 Simplify the Boolean Algebra expressions, using Karnaugh maps or othertechniques.

4 Manipulate the simplified expressions into a hardware-oriented form.5 Construct the hardware.

For Programmable Logic3 Incorporate the Boolean Algebra Expressions into an ABEL or VHDL

program.4 Compile the program to generate the JED file.5 Construct the required hardware.6 Program the device using the JED file.


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Minimisation Techniques

Boolean Algebra reductionUsing Boolean Algebra theorems, the expressions can be reduced.This is not straight-forward and one cannot guarantee that the optimum solution can

be obtained.

Example:T = A

/ B

/ C

/+ A

/ B C + A B

/ C + A

/ B C

/+ A

/ B

/ C + A B C

= A/ (B/ C/ + B C +B C/ + B/ C) + C (A/ B + A B/ + A/ B/ + A B)= A

/+ C

It is unlikely that one would be able to get that answer directly without knowing whatit was supposed to be.

Boolean Algebra reduction is thus not used to reduce complex circuitry

Karnaugh MapA Karnaugh map is a simple graphical representation of a Boolean algebra function.For a four variable function, all the possible input combinations can be mapped asfollows:

YZ00 01 11 10

00 W/X/Y/Z/ W/X/Y/Z W/X/YZ W/X/YZ/

01 W/XY

/Z

/W

/XY

/Z W

/XYZ W

/XYZ

/

11 WXY/Z/ WXY/Z WXYZ WXYZ/

WX

10 WX/Y/Z/ WX/Y/Z WX/YZ WX/YZ/

If instead of entering the variables, we put the numbers corresponding to the canonicalsum, we get:

YZ00 01 11 10

00 0 1 3 2

01 4 5 7 6

11 12 13 15 14

WX

10 8 9 11 10

T = A/ B

/ C

/+ A

/ B C + A B

/ C + A

/ B C

/+ A

/ B

/ C + A B C

Has the Karnaugh map as shown below:

BC00 01 11 10

0 1 1 1 1A

1 0 1 1 0

Reduction can take place ifadjacent ones can be grouped


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Grouping takes place in 2, 4, 8, 16 etc elements.

A two element grouping corresponds to the Boolean algebra reduction:A/ B/ + A/ B = A/ (B/ + B) = A/

A four element grouping corresponds to the Boolean algebra reduction:

A/

(B/

C/

+ B C +B C/

+ B/

C) = A/

The top row in this map corresponds to this expression and can thus be reduced.

The columns BC = 01 and BC = 11 correspond to the expression:C (A

/ B + A B

/+ A

/ B

/+ A B) = C

Examples of linkingT = (A/ B/ C/ D/ ) + (A/ B/ C/ D) + (A/ B/ C D/ ) + (A/ B C/ D/ )+ (A

/ B C

/ D) + (A

/ B C D

/) + (A B C D) + (A B

/ C D)

The Karnaugh Map reduction results in: T= A/ C/ + A/ D/ + A C D

T = C/ + A B

Dont CareSometimes a value will never occur. In that case we do not care what the output is. In

the Karnaugh map we label the appropriate square with a , a X or a d,depending on preferences. The dont care is included in the Karnaugh map loops onlyif convenient.

1 1

1 1

1

00

01

11

10

00 01 11 10

AB

CD

1

1

1

1 1

1 1

1

00

01

11

10

00 01 11 10

AB

CD

1 1

1 1

1


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Example1:

Consider a 7 segment display.

c

b

d

e

f

g

a

Seven Segment Display.

Number a b c d e f g Code

0 1 1 1 1 1 1 0 0

1 0 1 1 0 0 0 0 1

2 1 1 0 1 1 0 1 23 1 1 1 1 0 0 1 3

4 0 1 1 0 0 1 1 4

5 1 0 1 1 0 1 1 5

6 1 0 1 1 1 1 1 6

7 1 1 1 0 0 0 0 7

8 1 1 1 1 1 1 1 8

9 1 1 1 1 0 1 1 9

10 X X X X X X X X

11 X X X X X X X X

12 X X X X X X X X

13 X X X X X X X X14 X X X X X X X X

15 X X X X X X X X

Truth Table for Seven Segment Display with Numbers 0-9 only.

The truth table can be used to map element d onto a Karnaugh map as follows:

D1D0

D3D2

00 01 11 10

00

01

11

10

1 0 1 1

0 1 0 1

X XXX

1 1 X X

The resulting reduced Boolean expression is:


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d = D3 + D1D0/ + D2/D0/ + D2/D1 + D2D1/ D0

To realise this with NAND gates, NOR gates and inverters, De Morgans theorem isapplied to this expression and results in:

d = (D3/

(D1D0/

)/

(D2/

D0/

)/

(D2/

D1)/

(D2D1/

D0)/

)/

This requires 3 two input NAND gates, a three input NAND gate and a five inputNAND gate, thus requiring three 7400 series packages. (with one quarter of onepackage and tho thirds of another package not being used.)

Alternately the output d/ can be realised as:

D1D0

D3D2

00 01 11 10

00

01

11

10

1 0 1 1

0 1 0 1

X XXX

1 1 X X

d/= D2D1

/D0

/+ D2D1D0 + D3

/D2

/D1

/D0

To realise this with NAND gates, NOR gates and inverters, De Morgans theorem isapplied to this expression and results in:

d = ((D2D1/D0/ ) / (D2D1D0) / (D3/D2/D1/D0) /) / /

This requires 3 three input NAND gates, a four input NAND gate and an inverter. Byrealising the inverter as a 4 input NAND gate, the circuit can be realised using two7400 series packages.

With the use of dont cares the realisation of d is different from the inverse of the d/realisation. Both the d and d/ expressions are optimum. The use of dont caressignificantly reduces the circuit complexity.

To show the advantages of using a CPLD for this. Without the use of the dont cares,

so that the display can indicate the more usual A, b, C, d, E, F for 10 to 15, at least 3packages will be required per segment, ie 21 packages per display. For a 4hexadecimal digit display, 84 packages are required. Each device is about 50 cent inreasonable quantities, making a total of $42 in ICs, These devices fit on a large PCBand require 640 plated through holes. The same function fits inside half of one of the$6 iM4A5-64/32 CPLDs used in our labs, requiring a very small PCB area and no

plated through holes. It is however possible to use a 74LS47 MSI 7 segmentdecoder/driver IC for $1 per display.


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Example2: (Extra)

A BCD to decade multiplexer is a logic circuit that has 4 binary inputs (ABCD) andhas 10 binary outputs, (0 to 9), each corresponding to the value of the input as a

binary number. For such a BDC to decade multiplexer, the input values A, B, C, D, Eand F should never occur. We can thus use those locations as dont cares. This canmost easily be shown on the Karnaugh map by noting the location of the decimal

numbers, corresponding to each of the squares in the Karnaugh map as shown above.The numbers 10 to 15 correspond to dont cares for the decade multiplexer.

In canonical sums, dont cares are included as an extra term in brackets with a dprefix. For example the output 9 of a BCD to decade decoder as shown above iswritten as:

Output 9 = A,B,C,D

(9) + d(10,11,12,13,14,15)

And the corresponding reduced output is:

Output 9 = AD

If dont cares are not used, the output will be:

Output 9 = A B/ C

/ D .

Clearly using dont cares results in a saving in gate count.

Example 3: (Extra)

Sometimes a single optimum solution cannot be obtained, as shown in the followingexample:

F = (B/ C/ ) + (B D) + (C/ D) + (A C/ ) + (A B) + (B C) +(A/ C D/ ) + (A/ B/ D/ )

0 0

0 0

X

00 01 11 10

X X

0 1

X

00

01

11

10

CD

AB

X

0 0

0 0

X


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This can be realised in one of three different ways:

The first solution is:

F = (B/ C/ ) + (A/ C D/ ) + (B D) + (B C) + (A C / )

Which uses five minterms.

A better solution is:

F = (B/ C/ ) + (A/ C D/ ) + (B D) + (A B)

1 1

0

00 01 11 10

1

00

01

11

10

CD

AB

0 1

0

1 1 1

1 1 1 1

1 0

1 1

0

00 01 11 10

1

00

01

11

10

CD

AB

0 1

0

1 1 1

1 1 1 1

1 0

1 1

0

00 01 11 10

1

00

01

11

10

CD

AB

0 1

0

1 1 1

1 1 1 1

1 0


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Which uses only four minterms. By using De Morgans Theorem, this can be realisedusing three 2 input NAND gates, one 3 input NAND gate and one 4 input NAND

gate. F = ((B/ C/ ) / (A/ C D/ ) / (B D) / (A B) / ) /

For standard TTL there are two 4 input gates in one package, so that the minimum 2package realisation requires the 3 input NAND gate to be realised using a 4 input

NAND gate, with one input connected to logical 1.

A third solution is:

F = (C/ D ) + (A/ B

/ D

/) + (B C) + (A C

/)

The circuit diagram for this realisation is the same complexity as that for the secondsolution except that the input variables are different. There is thus no real differencein hardware costs between the last two realisations. These last two realisations are

both optimum.

5 and 6 Variable Karnaugh Maps (Extra)

A four variable Karnaugh map is a two-dimensional map as a single plane. For morethat 4 variables, either the Karnaugh maps have to be drawn as a three dimensionaldrawing, with several four variable Karnaugh maps as a series of stacked planes.

The linking is done not only in each plane, but also between adjacent planes. It can beseen that this is quite difficult to visualise. It is easier to place the individual maps

1 1

0

00 01 11 10

1

00

01

11

10

CD

AB

0 1

0

1 1 1

1 1 1 1

1 0

B'

C'

B

D

AB

A'CD'

1

F


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next to each other and do the linking between adjacent squares that way. It is probablythe most convenient to simply repeat the maps in a planar arrangement as shown forthe 5 variable Karnaugh map below:

Six variable Karnaugh map

Five variable Karnaugh map, planar arrangement.

One must remember that for instance 0, 2, 16 and 18 can form a group of fouradjacent locations. A 5 variable Karnaugh map is thus more difficult to use than a 4variable one. For a 6 variable Karnaugh map, we have four 4 variable maps in asimilar fashion to the maps for the 5 variable case. The linking for that is more

difficult still. For a 6 variable Boolean Algebra reduction, a 6 Karnaugh map will stillgive a quicker solution than other techniques, like the Quine McClusky reduction.

Computer Based Reduction Methods (Extra)It is extremely difficult to handle more than 6 variables in a Karnaugh map. If this isthe case then other techniques, like the Quine McClusky reduction must then be used.For this course the simplest technique would be to write the Boolean Algebraequations in ABEL and then let the Lattice ispExpert software solve those equations.

16 17 1819

20 21 2223

24 25 2627

28 29 3031

00 11 1001DE

ABC

110

111

101

1000 1 23

4 5 67

8 9 1011

12 13 1415

00 11 1001DE

ABC

010

011

001

000

AB

CD

EF


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The reduced equations are included as part of the reports produced by the software.These equations can then be used to either program the EPLDs or to realise thefunction using say TTL.

Quine-McClusky Reduction Method

(Chapter 4.4 of Wakerley)

The Quine McClusky method of reduction is an algorithm, which is very suitable forcomputer based implementation and can be applied to any number of variables. Themain aims of including this material is firstly to give a fuller understanding of theKarnaugh mapping technique and secondly to give an understanding how thecomputer programs which do the reduction for EPLDs work.

Part 1 Linking Canonical Sum terms.

Step 1 Group the binary numbers representing the required output, like canonicalsum, into groups with the same number of ones, ie according to index.

Step 2 Compare the numbers from adjacent groups, if they differ in one bit only,replace that bit with an X and enter the resulting word in the next column.This column is again grouped according to index. This grouping corresponds

to a linking of two adjacent squares in a Karnaugh map. Mark the numbersthat have been used with an 9.

Step 3 Repeat the process, assuming the x to be a new variable to be compared, untilno further reduction can take place. This amounts to making loops of 4, 8 16etc squares in the Karnaugh map.

Dont cares are included in these columns indication the linking of the canonical sumterms.

Example

T = 0,2,6,7,8,10,12,14,15,41 +d(25,27) i.e. 6 variables are required.

# Column 1 U # Column 2 U # Column 3 U

0 000000 9 0,2 0000X0 9 0,2,8,10 00X0X0

0,8 00X000 9

2 000010 9 2,6,10,14 00XX10

8 001000 9 2,6 000X10 9 8,10,12,14 001XX0

2,10 00X010 9

6 000110 9 8,10 0010X0 9 6,7,14,15 00X11X

10 001010 9 8,12 001X00 9

12 001100 9

6,7 00011X 9

7 000111 9 6,14 00X110 9 14 001110 9 10,14 001X10 9

25 011001 9 12,14 0011X0 9

41 101001

7,15 00X111 9

15 001111 9 14,15 00111X 9

27 011011 9 25,27 0110X1


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In this example no further merging can take place after the third column. The firstcolumn indicates single values. The second column contains loops with two canonicalsum terms, the third column contains loops with three canonical sum terms.

Part 2 Prime Implicant Table.

Step 4 Form the Prime Implicant table using the words, which could not be reducedfurther, i.e. those entries in the table without a 9.

Step 5 Select just sufficient Prime Implicants to cover all the variables and use thisto write the reduced equations.

# 0 2 6 7 8 10 12 14 15 41

41 X

25,27

0,2,8,10 X X X X

2,6,10,14 X X X X

8,10,12,14 X X X X

6,7,14,15 X X X X

Table 1 Prime Implicant TableIn this table we must have:41 as that is the only linking that covers 41.0,2,8,10 as that is the only linking that covers 0.8,10,12,14 as that is the only linking that covers 12.6,7,14,15 as that is the only linking that covers 7.

As each required row is selected, mark the columns that are covered by that row. Sofor 41, draw a vertical line through 41. For 0,2,8,10 draw vertical lines through 0,2,8

and 10. As each required row is used, place a9

.

The linked terms containing dont cares are included as rows of this table, but thedont cares are not included in the columns.

# 0 2 6 7 8 10 12 14 15 41

41 9 I I I I I I I I I X

25,27 I I I I I I I I I I

0,2,8,10 9 X X I I X X I I I I

2,6,10,14 I X X I I X I X I I

8,10,12,14 9 I I I I X X X X I I

6,7,14,15 9 I I X X I I I X X I

Table 2 Prime Implicant Table, after selecting the required linked terms.As a result 2,6,10,14 is not required, since 2, 6, 10, and 14 are already covered by theother terms in the table. As expected 25,27 is not required since that term onlyincluded dont cares.


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If the numbers are of the form # = FEDCBA, (i.e. A is the least significant bit and F isthe most significant bit) the reduced logic function is:

T = 41 + (0,2,8,10) + (8,10,12,14) + (6,7,14,15)

T = (FE/DC

/B

/A) + (F

/E

/C

/A

/) + (F

/E

/DA

/) + (F

/E

/CB)

Covering all the required canonical sum terms is simple in this example. Sometimes asingle optimum solution cannot be obtained. In those cases one has to make a choiceand select one of several optimum minimisations. On pages 10 - 12 of these Lecturenotes, an example is shown which gives two possible best realisations. The sametwo best realisations will result using a Quine-McClusky reduction.

Logic OptimisationThe compilers, which perform this type of logic reduction, perform well. Sometimesit is however necessary to obtain a particular reduction in order to ensure that a designstill fits inside a PAL, GAL or CPLD. In particular a combined minimisation, wherethe prime-implicant table covers more than one output variable, can yield a smallertotal gate count, at the expense of a more intensive reduction. With most of thecompilers, one can optimise the reduction for either high speed or a minimum amountof hardware used.

Sometimes a manually done reduction can be much more efficient than one achievedby the compiler. As a result one still needs to know how to do Karnaugh mapreductions.

Using Compilers for the ReductionConsider the BCD to Seven segment display on page 10.One can enter a truth table for all these outputs into the ispLever compiler. The truthtable does not include any entries for the dont cares and is as follows:

Truth_Table([BCD] -> [a, b, c, d, e, f, g, h])

[0 ] -> [1, 1, 1, 1, 1, 1, 0];[1 ] -> [0, 1, 1, 0, 0, 0, 0];[2 ] -> [1, 1, 0, 1, 1, 0, 1];[3 ] -> [1, 1, 1, 1, 0, 0, 1];[4 ] -> [0, 1, 1, 0, 0, 1, 1];[5 ] -> [1, 0, 1, 1, 0, 1, 1];[6 ] -> [1, 0, 1, 1, 1, 1, 1];[7 ] -> [1, 1, 1, 0, 0, 0, 0];[8 ] -> [1, 1, 1, 1, 1, 1, 1];

[9 ] -> [1, 1, 1, 1, 0, 1, 1];

where BCD is the BCD number and a to h are the corresponding outputs. The abovetruth table is written in a form suitable for use in an ABEL program. Using this truthtable as part of an ABEL program and then looking at the prefit equations in theispLever software, shows the reduced equations as shown below.


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It can be seen that the expression for !d is realised by the compiler. The realisationmatches the realisation for the zero values on the Karnaugh map shown on page 11and the reduced Boolean Algebra equation produced as part of the Fitter Report is

exactly the same as the equation for d/ shown on page 11.

For VHDL a case statement is used:process(Hexin)begin

LabSevSeg: case Hexin is-- need to have inverse of output coded here since the-- board displays include inverters.

when X"0" => SevSegOut SevSegOut SevSegOut SevSegOut SevSegOut SevSegOut SevSegOut SevSegOut SevSegOut SevSegOut


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It is thus much easier to use the ispLever (or equivalent) software to minimise theBoolean algebra equations, than drawing 7 Karnaugh maps and doing 7 reductions asrequired for conventional Karnaugh Map reduction techniques. There are howeversituations where Karnaugh map reduction must be used.

cc2510-ln2-combinlogic

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