ACCESS IC LAB

Graduate Institute of Electronics Engineering, NTU

CH18 Circuits for Arithmetic CH18 Circuits for Arithmetic OperationsOperations

Lecturer：吳安宇Date：2006/1/6

Graduate Institute of Electronics Engineering, NTU

台灣大學 吳安宇 教授

OutlineOutline18.1 Serial Adder with Accumulator18.2 Design of a Parallel Multiplier18.3 Design of a Binary Divider (Optional,

Skipped)

Final hour:Overview of Undergraduate Project

(by TA Chao)

Graduate Institute of Electronics Engineering, NTU

台灣大學 吳安宇 教授

Serial Addition ConceptSerial Addition Conceptv Similar to hand-operation by humanv focus on 1 digit ( bit ) at one time ti

v Use 1-bit full adderv Feed input bits { xi, yi, ci } from LSB to MSB sequentiallyv Output sum bits from LSB to MSB sequentiallyv D F/F should be cleared before the operations

c3 c2 c1 c0x3 x2 x1 x0

+ y3 y2 y1 y0s3 s2 s1 s0

c3 c2 c1Sum

Carry

t0t1t2t3

Graduate Institute of Electronics Engineering, NTU

台灣大學 吳安宇 教授

Timing of 4Timing of 4--bit Serial Adder with bit Serial Adder with Accumulator (X: ACC, Y: Addend)Accumulator (X: ACC, Y: Addend)

final sum

Graduate Institute of Electronics Engineering, NTU

台灣大學 吳安宇 教授

Serial Adder with AccumulatorSerial Adder with Accumulatorv Verify the numerical example yourself

Ci+Ci

SiX

Y

Graduate Institute of Electronics Engineering, NTU

台灣大學 吳安宇 教授

Serial Adder with AccumulatorSerial Adder with Accumulator

X = (x3x2x1x0)Y = (y3y2y1y0)

ØSI：Serial Input

ØSh: Enable Signal of

• Shift registers (X & Y)

• Carry D F/F

Graduate Institute of Electronics Engineering, NTU

台灣大學 吳安宇 教授

Controller of Serial Adder with Controller of Serial Adder with AccumulatorAccumulator

v Use Finite State Machine (FSM) for control unit of the serial adderv State graph and State table

Graduate Institute of Electronics Engineering, NTU

台灣大學 吳安宇 教授

Serial Adder with AccumulatorSerial Adder with Accumulatorv Control Unit Design of Serial Adderv Derivation of Control Circuit Equations

State Assignment

Graduate Institute of Electronics Engineering, NTU

台灣大學 吳安宇 教授

Serial Adder with AccumulatorSerial Adder with Accumulatorv Generalized Serial Arithmetic Circuit Design

Feedback signals

Graduate Institute of Electronics Engineering, NTU

台灣大學 吳安宇 教授

OutlineOutline18.1 Serial Adder with Accumulator18.2 Design of a Parallel Multiplier

Graduate Institute of Electronics Engineering, NTU

台灣大學 吳安宇 教授

Concept of ShiftConcept of Shift--andand--Add MultiplierAdd MultipliervSimilar to hand-operation by humanvMultiply 1 digit of multiplier to multiplicandvShift Multiplier (x2) and add it to (+) the partial

product

1101 x 1 (1011)1101 x 1 (1011)

1101 x 0 (1011)

1101 x 1 (1011)000

Graduate Institute of Electronics Engineering, NTU

台灣大學 吳安宇 教授

Share the Register of Share the Register of MultiplierMultiplier and and ProductProduct

{ product, multiplier }

(Add)(div by 2)

Graduate Institute of Electronics Engineering, NTU

台灣大學 吳安宇 教授

Structure of Serial MultiplierStructure of Serial Multiplierdirection of shift register

get 1 bit of multiplier

Load: Load multiplierSh: ShiftAd: Add

St: StartM: multiply (LSB of Multiplier)Done: finish multiplication

Graduate Institute of Electronics Engineering, NTU

台灣大學 吳安宇 教授

Implement FSM for Multiplier (1)Implement FSM for Multiplier (1)v Direct approachv Use states for each add/shift operation

Initial state

Load multiplicand and multiplier

S1→S2: M=1, do addition

S1→S3: M=0, do shift ( addition is skipped )

S2→S3: do shift to Right

1-bit multiplication

Overhead to increase 1-bit multiplication: 2 states

Graduate Institute of Electronics Engineering, NTU

台灣大學 吳安宇 教授

Implement FSM for Multiplier (2)Implement FSM for Multiplier (2)v Separate approachv use counter instead of state number for 1-bit multiplicationv complete signal K is generate from counter

1-bit multiplication loop

KM’ : MSB of multiplier is 0, shift and goto S3

K : reach MSB and add operation is finished, shift and goto S3

Graduate Institute of Electronics Engineering, NTU

台灣大學 吳安宇 教授

Timing Table of ExampleTiming Table of Examplev1101x1011

Graduate Institute of Electronics Engineering, NTU

台灣大學 吳安宇 教授

OutlineOutline18.1 Serial Adder with Accumulator18.2 Design of a Parallel Multiplier18.3 Design of a Binary Divider (Optional,

Skipped)