chapter 2 instructions: language of the machine

Chapter 2Instructions: language of the Machine

Chapter 2Instructions: language of the Machine

授課教師 : 張傳育博士 (Chuan-Yu Chang Ph.D.)E-mail: [email protected]: (05)5342601 ext. 4337

2

Instructions:

Language of the Machine

More primitive than higher level languagese.g., no complex control flow

Very restrictivee.g., MIPS Arithmetic Instructions

We’ll be working with the MIPS instruction set architecturesimilar to other architectures developed since the 1980's

Almost 100 million MIPS processors manufactured in 2002

used by NEC, Nintendo, Cisco, Silicon Graphics, Sony, …

Design goals: To find a language that makes it easy to build the hardware and compiler while maximizing performance and minimize cost, reduce design time

1400

1300

1200

1100

1000

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01998 2000 2001 20021999

Other

SPARC

Hitachi SH

PowerPC

Motorola 68K

MIPS

IA-32

ARM

3

MIPS arithmetic

All instructions have 3 operands

Operand order is fixed (destination first)

$s0, $s1,… for registers that correspond to variables in C programs

$t0, $t1,… for temporary registers needed to compile the program into MIPS instruction.

Example:C code: A = B + CMIPS code: add $s0, $s1, $s2

(associated with variables by compiler)

4

ExamplesExamples

Compiling Two C Assignment Statements into MIPSa = b + c;d = a – e;

Solutionadd a, b, csub d, a, e

Compiling a Complex C Assignment into MIPSf = (g + h) – (i + j);Solutionadd t0, g, hadd t1, i, j sub f, t0, t1

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MIPS arithmetic

Design Principle: simplicity favors regularity( 簡單明瞭有助於一致性 ).

Example:

C code: a = b + c + d;e = f - a;

MIPS code: add $t0, $s1, $s2add $s0, $t0, $s3sub $s4, $s5, $s0

Operands must be registers, only 32 registers provided

Design Principle: smaller is faster.

The size of a register in the MIPS architecture is 32 bits

The variables a, b, c, d, e and f are assigned to the registers $s0, $s1, $s2,

$s3, $s4, $s5.

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ExampleExample

Compiling a C assignment Using Registersf = (g + h) – (i + j);SolutionThe variables f, g, h, i, and j are assigned to the registers $s0, $s1, $s2, $s3, $s4. The compiled MIPS code :add t0, $s1, $s2add t1, $s3, $s4 sub $s0, $t0, $t1

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Registers vs. Memory

Processor I/O

Control

Datapath

Memory

Input

Output

Arithmetic instructions operands must be registers, — only 32 registers provided

Compiler associates variables with registers

What about programs with lots of variables?The CPU can keep only a small amount of data in registers.

Computer memory contains millions of data elements.

MIPS must include instructions (data transfer instruction) that transfer data between memory and registers..

8

Memory Organization

How can a computer represent and access large memory?

Viewed as a large, single-dimension array, with an address.

A memory address is an index into the array

"Byte addressing" means that the index points to a byte of memory.

0

1

2

3

4

5

6

...

8 bits of data

8 bits of data

8 bits of data

8 bits of data

8 bits of data

8 bits of data

8 bits of data

100

10

101

1

3

2

1

0

DataAddress

MemoryProcessor

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Memory Organization

Bytes are nice, but most data items use larger "words"

For MIPS, a word is 32 bits or 4 bytes.

232 bytes with byte addresses from 0 to 232-1

230 words with byte addresses 0, 4, 8, ... 232-4

Words are aligned

0

4

8

12

...

32 bits of data

32 bits of data

32 bits of data

32 bits of data

Registers hold 32 bits of data

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Instructions

Load instructionslw: (load word): moves data from memory to a register.

Store instructionssw: (store word): transfers data from a register to memoryStore word has destination last

Example:Let’s assume that A is an array of 100 words and that the compiler has associated the variables g and h with the registers $s1 and $s2 as before. The starting address of the array is in $s3. Translate this C assignment statement:

C code: g = h + A[8]MIPS code: lw $t0, 32($s3)

add $s1, $s2, $t0

C code: A[8] = h + A[8];MIPS code: lw $t0, 32($s3)

add $t0, $s2, $t0sw $t0, 32($s3)

Remember arithmetic operands are registers, not memory!

offset

Base register

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Compiling using a variable indexCompiling using a variable index

Example: g = h + A [i]Assume A is an array of 100 elements whose base is in register $s3 and that the compiler associates the variables g, h and i with the registers $s1, $s2, and $s4. What is the MIPS assembly code corresponding to this C segment?

Solution:add $t1, $s4, $s4 # Temp reg $t1 = 2 * iadd $t1, $t1, $t1 # Temp reg $t1 = 4 *iadd $t1, $t1, $s3 # $t1 = address of A[i] (4*i+$s3)lw $t0, 0($t1) # Temporary reg $t0 = A[i]add $s1, $s2, $t0 # g = h + A[i]

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Constant and Immediate OperandsConstant and Immediate Operands

The constants would have been placed in memory when the program was loaded.

lw $t0, AddrConstant4 ($s1) # $t0=constant 4add $s3, $s3, $t0 # $s3=$s3+$t0 ($t0==4)

Assuming that AddrConstant4 is the memory address of the constant 4.

Add immediate (addi)Addi $s3, $s3, 4 #$s3=$s3+4

To add 4 to register $s3

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So far we’ve learned:

MIPS— loading words but addressing bytes— arithmetic on registers only

Instruction Meaning

add $s1, $s2, $s3 $s1 = $s2 + $s3sub $s1, $s2, $s3 $s1 = $s2 – $s3lw $s1, 100($s2) $s1 = Memory[$s2+100] sw $s1, 100($s2) Memory[$s2+100] = $s1

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Instructions, like registers and words of data, are also 32 bits long

Example: add $t0, $s1, $s2

registers have numbers, $t0=8, $s1=17, $s2=18

$s0~$s7:16~23, $t0~$t7:8-15

Instruction Format:R-Type

0000001000110010 01000 00000 100000 op rs rt rd shamt funct

Machine Language

6 bits 5 bits 5 bits 5bits 5 bits 6 bits

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Machine LanguageMachine Language

MIPS Fieldsop: opcode, basic operation of the instructionrs: the first source operand registerrt: the second source operand registerrd: the destination operand registershamt: shift amountfunct: function, selects the specific variant of the op

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Consider the load-word and store-word instructions,What would the regularity principle have us do?

New principle: Good design demands a compromise

Introduce a new type of instruction formatI-type for data transfer instructions

other format was R-type for register

Example:lw $t0, 32($s3)#Temporary reg $t0 gets A[8] 35 19 8 32 op rs rt address

Where's the compromise?To keep all instructions the same length, thereby requiring different kinds of instruction formats for different kinds of instructions.

Machine Language

6 bits 5 bits 5 bits 16 bits

Specifies the destination register

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MIPS Instruction Encoding

Instruction Format op rs rt rd shamt funct address

add R 0 reg reg reg 0 32 n.a.

sub R 0 reg reg reg 0 34 n.a.

lw I 35 reg reg n.a.

n.a. n.a. address

sw I 43 reg reg n.a. n.a. n.a. address

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Translating MIPS Assembly Language into Machine LanguageTranslating MIPS Assembly Language into Machine Language

Example: Assuming that $t1 has the base of the array A and that $s2 corresponds to h, the C assignment statementA[300] = h + A[300]is compiled intolw $t0, 1200($t1)add $t0, $s2, $t0sw $t0, 1200($t1)What is the MIPS machine language code for these three instructions?

Solution: op rs rt rdAddress/

shamt funct

35 9 8

0 18 8 8 0 32

43 9 8

1200

1200

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Today’s computers are built on two key principles:Instructions are represented as numbers (bits)

Programs are stored in memory — to be read or written just like data

Fetch & Execute CycleInstructions are fetched and put into a special register

Bits in the register "control" the subsequent actions

Fetch the “next” instruction and continue

Processor Memory

memory for data, programs, compilers, editors, etc.

Stored Program Concept

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Decision making instructionsalter the control flow,i.e., change the "next" instruction to be executed

MIPS conditional branch instructions:Branch if equal: beq

beq register1, register2, L1if the value of register1 equals the value of register2 then go to the statement labeled L1.Branch if not equal: bne

bne register1, register2, L1if the value of register1 does not equals the value of register2 then go to the statement labeled L1.

Example: if (i==j) h = i + j; Assume that i, j and h mapping to $s0,$s1, and $s3

bne $s0, $s1, Labeladd $s3, $s0, $s1

Label: ....

Instructions for Making Decisions: Control

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Example: Compiling an If Statement into a Conditional Branch.Example: Compiling an If Statement into a Conditional Branch.

Example: C code segmentif (i == j) go to L1;f = g + h;

L1: f = f-i;Assuming that the five variables f through j correspond to the five registers $s0 through $s4, what is the compiled MIPS code?

Solution:beq $s3, $s4, L1add $s0, $s1, $s2

L1: sub $s0, $s0, $s3

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Control: if-then-else

MIPS unconditional branch instructions:j label

Example:if (i!=j) beq $s3, $s4, Lab1 h=i+j; add $s2, $s3, $s4else j Lab2 h=i-j; Lab1: sub $s2, $s3, $s4

Lab2: ...

Example:if ( i == j ) f = g + h; else f = g – h;

Solution:bne $s3, $s4, Elseadd $s0, $s1, $s2j Exit

Else: sub $s0, $s1, $s2Exit:

i == j?

f = g– hf = g + h

Else:

Exit:

i=j ij

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Control: LoopsControl: Loops

Example: Here is a loop in C:Loop: g = g + A[i];

i = i + j;if ( i != h ) goto Loop;

Assume that A is in $s5, g, h, i,j are in $s1 through $s4. What is the MIPS assembly code corresponding to this C loop?

Solution:Loop: add $t1, $s3, $s3 #Temp reg $t1 = 2 * i

add $t1, $t1, $t1 #Temp reg $t1 = 4 * i add $t1, $t1, $s5 #$t1 = address of A[i]

lw $t0, 0($t1)add $s1, $s1, $t0 # g = g + A[i]

add $s3, $s3, $s4 # i = i + j bne $s3, $s2, Loop # if ( i != h ) goto Loop

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Control: While LoopsControl: While Loops

Example: Here is a traditional loop in Cwhile ( save [ i ] == k)

i = i + j;

Assume that i, j, and k correspond to registers $s3, $s4, and $s5, and the base of the array save is in $s6. What is the MIPS assembly code corresponding to this C segment?

Solution:Loop: add $t1, $s3, $s3

add $t1, $t1, $t1add $t1, $t1, $s6lw $t0, 0($t1)bne $t0, $s5, Exit # go to Exit if save[i]

!= k add $s3, $s3, $s4 # i = i +j

j Loop # go to LoopExit:

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So far:

Instruction Meaningadd $s1,$s2,$s3 $s1 = $s2 + $s3sub $s1,$s2,$s3 $s1 = $s2 – $s3lw $s1,100($s2) $s1 = Memory[$s2+100] sw $s1,100($s2) Memory[$s2+100] = $s1bne $s4,$s5,L Next instr. is at Label if $s4 != $s5beq $s4,$s5,L Next instr. is at Label if $s4 = $s5j Label Next instr. is at Label

Formats:

op rs rt rd shamt funct

op rs rt 16 bit address

op 26 bit address

R

I

J

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We have: beq, bne, what about Branch-if-less-than?

New instruction:if $s1 < $s2 then

$t0 = 1 slt $t0, $s1, $s2 else

$t0 = 0

slt (set on less than)

Note that the assembler needs a register to do this,— there are policy of use conventions for regist

ers

Control Flow

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Control: Branch on Less ThanControl: Branch on Less Than

Example: What is the code to test if register $s0 is less than register $s1 and than branch to label Less if the condition holds?

Solution:slt $t0, $s0, $s1bne $t0, $zero, Less

Register $zero always contains 0.

The pair of instructions, slt and bne, implements branch on less than.

Jump register (jr)

An unconditional jump to the address specified in a register.

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Control: Case/Switch StatementControl: Case/Switch Statement

The simplest way to implement switch is via a sequence of conditional tests, turning the switch statement into a chain of if-then-else statements.

Encoded as a table of addresses of alternative instruction sequences, called jump address table.

The program needs only to index into the table and then jump to the appropriate sequence.

The jump table is an array of words containing addresses that correspond to labels in the code.

MIPS includes a jump register (jr) instruction, meaning an unconditional jump to the address specified in a register.

The program loads the appropriate entry from the jump table into a register, and then it jumps to the proper address using a jump register.

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Example:switch (k) {

case 0: f = i + j; break; case 1: f = g + h; break; case 2: f = g - h; break; case 3: f = i - j; break;

}Assume that variables f through k correspond to six registers $s0 through $s5 and the register $t2 contains 4. What’s the MIPS code?

Solution:slt $t3, $s5, $zerobne $t3, $zero, Exitslt $t3, $s5, $t2beq $t3, $zero, Exitadd $t1, $s5, $s5add $t1, $t1, $t1add $t1, $t1, $t4lw $t0, 0($t1)jr $t0

L0: add $s0, $s3, $s4j Exit

L1: add $s0, $s1, $s2j Exit

L2: sub $s0, $s1, $s2j Exit

L3: sub $s0, $s3, $s4Exit:

假設 JumpTable 的起始位址為 $t4

檢查 k 是否小於 0檢查 k 是否小於 4

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Jump address table

Jump Address Table

L0L1L2L3

Jump address table 的起始位址為 $t4 ，每個 location 為 4 bytes。

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Policy of Use Conventions

Name Register number Usage$zero 0 the constant value 0$v0-$v1 2-3 values for results and expression evaluation$a0-$a3 4-7 arguments$t0-$t7 8-15 temporaries$s0-$s7 16-23 saved$t8-$t9 24-25 more temporaries$gp 28 global pointer$sp 29 stack pointer$fp 30 frame pointer$ra 31 return address

Register 1 ($at) reserved for assembler, 26-27 for operating system

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Supporting Procedures in Computer HardwareSupporting Procedures in Computer Hardware

Execution a procedure, the program must follow these six steps:Place parameters in a place where the procedure can access them

Transfer control to the procedure

Acquire the storage resources need for the procedure.

Perform the desired task.

Place the result value in a place

Return control to the point of origin

MIPS allocates 7 registers for procedure call$a0-$a3: to pass parameters

$v0-$v1: to return values

$ra: to return the point of origin.

Jump-and-link instruction (jal)jal Procedure Address

The jal instruction saves PC+4 in register $ra

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What happens when a procedure is calledWhat happens when a procedure is called

Before calling a procedure, the caller must:1. Pass the arguments to the callee procedure;

The 4 arguments are passed in registers $a0-$a3 ($4 -$7). The remaining arguments are placed on the stack.

2. Save any caller-saved registers that the caller expects to use after the call. This includes the argument registers and the temporary registers $t0-$t9. (The callee may use these registers, altering the contents.)3. Execute a jal to the called procedure (callee). This saves the return address in $ra.

At this point, the callee must set up its stack frame:1. Allocate memory on the stack by subtracting the frame size from the $sp.2. Save any registers the caller expects to have left unchanged.

These include $ra, $fp, and the registers $s0 - $s7.

3. Set the value of the frame pointer by adding the stack frame size to $fp and subtracting 4.

The procedure can then execute its function.Note that the argument list on the stack belongs to the stack frame of the caller.

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Returning from a procedureReturning from a procedure

When the callee returns to the caller, the following steps are required:

1. If the procedure is a function returning a value, the value is placed in register $v0 and, if two words are required, $v1 (registers $2 and $3).2. All callee-saved registers are restored by popping the values from the stack, in the reverse order from which they were pushed.3. The stack frame is popped by adding the frame size to $sp.4. The callee returns control to the caller by executing jr $ra

Note that some of the operations may not be required for every procedure call, and modern compilers would only generate the steps required for each particular procedure.

For example, the lowest level subprograms to be called (\leaf nodes") would not have to save $ra.

If a programming language does not allow a subprogram to call itself (recursion) then implementing a stack frame may not be required, but a stack is still required for nested procedure calls.

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Supporting Procedures in Computer Hardware (cont.)Supporting Procedures in Computer Hardware (cont.)

Return jumpjr $ra

Stack (last in first out)Push: placing data onto the stack

Pop: removing data from the stack

Stack grow from higher address to lower address.

Stack pointer$sp : used to save the registers needed by the callee

($a0~$a3)jal X

($v0~$v1)jr $ra

caller callee X

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Example: Compiling a procedure that does not call another procedureExample: Compiling a procedure that does not call another procedure

What is the compiled MIPS assembly code?int leaf_example(int g, int h, int i, int j){

int f;f = ( g + h ) – ( i + j );return f;

}SolutionThe parameter variables g, h, i, and j correspond to the argument registers $a0, $a1, $a2, and $a3, and f corresponds to $s0.

sub $sp, $sp, 12sw $t1, 8($sp)sw $t0, 4($sp)sw $s0, 0($sp)add $t0, $a0, $a1add $t1, $a2, $a3sub $s0, $t0, $t1 add $v0, $s0, $zerolw $s0, 0($sp)lw $t0, 4($sp)lw $t1, 8($sp)add $sp, $sp, 12jr $ra

Contents of register $s0

Contents of register $t0

Contents of register $t1

$sp

$sp

$sp

High address

Low address a. b. c.

在 leaf_example 的 procedure中，會使用到 3 個暫時性的暫存器，因此需預留 3*4=12byte

將暫存器 $t1, $t2, $s0 的值，儲存在堆疊中。

將堆疊中的值，回存暫存器 $t1, $t2, $s0 。

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Nest ProceduresNest Procedures

Push all the other registers that must be preserved onto the stack.

The stack pointer $sp is adjusted to account for the number of registers placed on the stack.

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Example: Compiling a recursive procedure, showing nested procedure linking

Example: Compiling a recursive procedure, showing nested procedure linking

int fact (int n){

if ( n <1 ) return (1);else return (n * fact (n-1) );

}Solution

fact:sub $sp, $sp, 8sw $ra, 4($sp)sw $a0, 0($sp)slt $t0, $a0, 1 #test for n<1beq $t0, $zero, L1 #if n>=1, goto L1add $v0, $zero, 1 #return 1add $sp, $sp, 8 #pop 2 items off stackjr $ra

L1: sub $a0, $a0, 1 #n>=1: argument gets (n-1)jal fact #call fact with (n-1)lw $a0, 0($sp) #return from jal: restore argument

nlw $ra, 4 ($sp) #restore the return address addi $sp, $sp, 8mul $v0, $a0, $v0jr $ra

因為會用到 $a0和返回位址 $ra，所以需要 2個位址，並且先將 $a0和 $ra儲存在堆疊中。

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The MIPS memory allocation for program and dataThe MIPS memory allocation for program and data

The data segment is divided into 2 parts, the lower part for static data (with size known at compile time) and the upper part, which can grow, upward, for dynamic data structures.

The stack segment varies in size during the execution of a program, as functions are called and returned from.

It starts at the top of memory and grows down.

$sp

$gp

0040 0000 hex

0

1000 0000 hex

Text

Static data

Dynamic data

Stack7fff ffff hex

1000 8000hex

pc

Reserved

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What is preserved across a procedure callWhat is preserved across a procedure call

Preserved Not Preserved

Saved registers: $s0~$s7 temporary registers: $t0~$t9

Stack pointer register : $sp Argument register : $a0~$a3

Return address register: $ra Return value register: $v0~$v1

Stack above the stack pointer Stack below the stack pointer

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Beyond NumbersBeyond Numbers

Load byte (lb)Loads a byte from memory, placing it in the rightmost 8 bits of a register.

Store byte (sb)Takes a byte from the rightmost 8 bits of a register and writes it to memory.

lb $t0, 0($sp) # read byte from sourcesb $t0, 0($sp) # write byte to destination

There are three choices for representing a string:The first position of the string is reserved to give the length of a string.

An accompanying variable has the length of the string

The last position of a string is indicated by a character used to mark the end of a string.

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Example: Compiling a string copy procedure, showing how to use C stringsExample: Compiling a string copy procedure, showing how to use C strings

void strcpy (char x[], char y[]){

int i;i = 0;while ( ( x[i] = y[i] ) != 0)

i = i + 1 ;}Solutionstrcpy:

sub $sp, $sp, 4 #adjust stack for 1 more itemsw $s0, 0($sp) # save $s0add $s0, $zero, $zero # i = 0

L1: add $t1, $a1, $s0 #address of y[i] in $t1lb $t2, 0($t1) $t2 = y[i]add $t3, $a0, $s0 #address of x[i] in $t3sb $t2, 0($t3) #x[i] = y[i]beq $t2, $zero, L2 # if y[i]==0, go to L2add $s0, $s0, 1 #i = i+1j L1 # go to L1

L2: lw $s0, 0($sp) # y[i] ==0; end of stringadd $sp, $s0, 4 #restore old $s0, pop 1 word off stac

kjr $ra #return

array x and y are in $a0 and $a1 i is in $s0

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Small constants are used quite frequently (50% of operands) e.g., A = A + 5;

B = B + 1;C = C - 18;

Solutions? Why not?put 'typical constants' in memory and load them.

Ex: to add the constant 4 to register $spLw $t0, AddrConstant4add $sp, $sp, $t0

create hard-wired registers (like $zero) for constants like one.

Example: Translating Assembly Constants into Machine Language

Solution: addi $sp, $sp, 4

Constants

op (6 bit) rs (5 bit) rt (5 bit) Immediate(16 bit)

8 29 29 4

001000 11101 11101 0000 0000 0000 0100

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Immediate OperandsImmediate Operands

Immediate version of the set on less than instruction:slti $t0, $s2, 10 #$t0 = 1 if $s2 <10

Load upper immediate instruction:To set the upper 16 bits of a constant in a register.

lui $t0, 255 # $t0 is register 8

001111 00000 01000 0000 0000 1111 1111

0000 0000 0000 00000000 0000 1111 1111

Content of register $t0 after executing lui $t0, 255

The machine language version of lui $t0, 255op rs rt immediate

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We'd like to be able to load a 32 bit constant into a register

Must use two instructions, new "load upper immediate" instruction

lui $t0, 1010101010101010

Then must get the lower order bits right, i.e.,

ori $t0, $t0, 10101010101010101010101010101010 0000000000000000

0000000000000000 1010101010101010

1010101010101010 1010101010101010

ori

1010101010101010 0000000000000000

filled with zeros

How about larger constants?

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Example: Loading a 32-bit constantExample: Loading a 32-bit constant

What is the MIPS assembly code to load this 32-bit constant into register $s0?

0000 0000 0011 1101 0000 1001 0000 0000

Solution (1):lui $s0, 61

addi $s0, $s0, 2304

Solution (2): (discuss in chapter 4)lui $s0, 61ori $s0, $s0, 2304

0000 0000 0000 00000000 0000 0011 1101

0000 1001 0000 00000000 0000 0011 1101

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Instructions:

bne $t4,$t5,Label Next instruction is at Label if $t4 <> $t5

beq $t4,$t5,Label Next instruction is at Label if $t4 = $t5

j Label Next instruction is at Label

Formats:

Addresses are not 32 bits

How do we handle this with load and store instructions?Program counter = register + branch address

PC-relative addressing

Addresses in Branches and Jumps

op rs rt 16 bit address

op(6bit) 26 bit address

I

J

Conditional branch

unconditional branch

48

Showing Branch Offset in Machine LanguageShowing Branch Offset in Machine Language

If we assume that the loop is placed starting at location 80000.Loop: add $t1, $s3, $s3

add $t1, $t1, $t1add $t1, $t1, $s6lw $t0, 0($t1)bne $t0, $s5, Exitadd $s3, $s3, $s4j Loop

Exit:

Solution:

0 19 19 9 0 320 9 9 9 0 320 9 22 9 0 32

35 9 8 05 8 21 8 (2)0 19 20 19 0 322 80000 (20000)

8000080004800088001280016800208002480028

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Showing Branch Offset in Machine Language (cont.)Showing Branch Offset in Machine Language (cont.)

The while loop on page 74 was compiled into this MIPS assembler code:Loop: sll $t1, $s3, 2

add $t1, $t1, $s6lw $t0, 0($t1)bne $t0, $s5, Exitaddi $s3, $s3, 1j Loop

Exit:If we assume we place the loop starting at location 80000 in memory, what is the MIPS machine code for this loop?

0 0 19 9 2 0

0 9 22 9 0 32

35 9 8 0

5 8 21 2

8 19 19 1

2 20000

80000

80004

80008

80012

8001680020

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Branching Far AwayBranching Far Away

How about the conditional branch instruction to jump far away?Insert an unconditional jump to the branch target

Inverts the condition so that the branch decides whether to skip the jump.

Example:Given a branch on register $s0 being equal to register $s1

beq $s0, $s1, L1replace it by a pair of instructions that offers a much greater branching distance.

Solutionbne $s0, $s1, L2j L1

L2;

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MIPS Addressing Mode SummaryMIPS Addressing Mode Summary

Addressing modes:Register addressing

The operand is a register

Base addressingThe operand is at the memory location whose address is the sum of a register and a constant in the instruction.

Immediate addressingThe operand is a constant within the instruction itself.

PC-relative addressingThe address is the sum of the PC and a constant in the instruction.

Pseudo-direct addressingThe jump address is the 26 bits of the instruction concatenated with the upper bits of the PC.

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MIPS addressing modesMIPS addressing modes

Byte Halfword Word

Registers

Memory

Memory

Word

Memory

Word

Register

Register

1. Immediate addressing

2. Register addressing

3. Base addressing

4. PC-relative addressing

5. Pseudodirect addressing

op rs rt

op rs rt

op rs rt

op

op

rs rt

Address

Address

Address

rd . . . funct

Immediate

PC

PC

+

+

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Example: Decoding machine codeExample: Decoding machine code

What is the assembly language corresponding to this machine instruction? 0000 0000 1010 1111 1000 0000 0010 0000

Solution:

查表 (Fig. 2.25)可得

add $s0, $a1, $t7

000000 00101 01111 10000 0000 100000

op rs rt rd shamt funct

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To summarize:MIPS operands

Name Example Comments$s0-$s7, $t0-$t9, $zero, Fast locations for data. In MIPS, data must be in registers to perform

32 registers $a0-$a3, $v0-$v1, $gp, arithmetic. MIPS register $zero always equals 0. Register $at is $fp, $sp, $ra, $at reserved for the assembler to handle large constants.

Memory[0], Accessed only by data transfer instructions. MIPS uses byte addresses, so

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memory Memory[4], ..., sequential words differ by 4. Memory holds data structures, such as arrays,

words Memory[4294967292] and spilled registers, such as those saved on procedure calls.

MIPS assembly language

Category Instruction Example Meaning Commentsadd add $s1, $s2, $s3 $s1 = $s2 + $s3 Three operands; data in registers

Arithmetic subtract sub $s1, $s2, $s3 $s1 = $s2 - $s3 Three operands; data in registers

add immediate addi $s1, $s2, 100 $s1 = $s2 + 100 Used to add constants

load word lw $s1, 100($s2) $s1 = Memory[$s2 + 100] Word from memory to register

store word sw $s1, 100($s2) Memory[$s2 + 100] = $s1 Word from register to memory

Data transfer load byte lb $s1, 100($s2) $s1 = Memory[$s2 + 100] Byte from memory to register

store byte sb $s1, 100($s2) Memory[$s2 + 100] = $s1 Byte from register to memory

load upper immediate lui $s1, 100 $s1 = 100 * 216 Loads constant in upper 16 bits

branch on equal beq $s1, $s2, 25 if ($s1 == $s2) go to PC + 4 + 100

Equal test; PC-relative branch

Conditional

branch on not equal bne $s1, $s2, 25 if ($s1 != $s2) go to PC + 4 + 100

Not equal test; PC-relative

branch set on less than slt $s1, $s2, $s3 if ($s2 < $s3) $s1 = 1; else $s1 = 0

Compare less than; for beq, bne

set less than immediate

slti $s1, $s2, 100 if ($s2 < 100) $s1 = 1; else $s1 = 0

Compare less than constant

jump j 2500 go to 10000 Jump to target address

Uncondi- jump register jr $ra go to $ra For switch, procedure return

tional jump jump and link jal 2500 $ra = PC + 4; go to 10000 For procedure call

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MIPS instruction encodingMIPS instruction encoding

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Translating and Staring a ProgramTranslating and Staring a Program

A translation hierarchy

Assembler

Assembly language program

Compiler

C program

Linker

Executable: Machine language program

Loader

Memory

Object: Machine language module Object: Library routine (machine language)

為了加速編譯的過程，有些步驟會被合併或省略，例如：

1. 有些 compiler 直接產生 object code2. 採用 linking loader 整合 linker 和 load

er

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CompilerThe compiler transforms the C program into an assembly language program.

A symbolic form of what the machine understands

AssemblerThe assembler convert the assembly language instruction into the machine language.

Pseudoinstruction

Sometimes, an assembler will accept a statement that does not correspond exactly to a machine instruction. For example, it may correspond to a small set of machine instructions. These are called pseudoinstructions.

Assemblers keep track of labels used in branches and data transfer instructions in symbol table.

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The object file for UNIX systems typically contains Object file header

Describes the size and position of the other pieces of the object file.Text segment

Contains the machine code.Static data segment

Contains data allocated for the life of the program.Relocation information

Identifies instructions and data words that depend on absolute address when the program is loaded into memory.

Symbol tableContains the remaining labels that are not defined, such as external reference.

Debugging informationContains a concise description of how the modules were compiled .

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Linker (link editor)

Place code and data modules symbolically in memory

Determine the addresses of data and instruction labels.

Patch both the internal and external references.

The linker uses the relocation information and symbol table in each object module to resolve all undefined labels.

The linker produces an executable file that can be run on a computer

Loader

Reads the executable file header to determine size of the text and data segment.

Creates an address space large enough for the text and data

Copies the instructions and data from the executable file into memory.

Initializes the machine registers and sets the stack pointer to the first free location.

Jumps to a start-up routine that copies the parameters into the argument registers and calls the main routine of the program.

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Dynamic Linked LibrariesDynamic Linked Libraries

Although the traditional static linking libraries is the fastest way to call library routines, it has a few disadvantages:

The library routines become part of the executable code.

It loads the whole library even if all of the library is not used when the program is run.

Dynamic Linked LibrariesThe library routines are not linked and loaded until the program is run.

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Starting a Java ProgramStarting a Java ProgramJava is compiled first to instructions that are easy to interpret: the Java bytecode instruction set.Java programs are distributed in the binary version of these bytecodes.Java Virtual Machine (JVM) is an interpreter which can execute Java bytecodes.

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Array Version of ClearArray Version of Clear

clear1 (int array[ ], int size){

int i;for ( i =0, i <size, i = i +1)

array[i ] = 0;}

Solution:move $t0, $zero # i=0

loop1: add $t1, $t0, $t0 # $t1=i*4add $t1, $t1, $t1add $t2, $a0, $t1 # $t2=address of array[i]sw $zero, 0($t2) # array[i]=0addi $t0, $t0, 1 # i=i+1slt $t3, $t0, $a # $t3= (i<size)bne $t3, $zero, loop1 # if (i<size) goto loop1

array: $a0size: $a1i: $t0

sll $t1, $t0, 2

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Pointer Version of ClearPointer Version of Clear

clear2 (int *array, int size){

int *p;for ( p =&array[0], p < &array[size], p = p +1)

*p = 0;}

Solution:move $t0, $a0 # p=address of array[0]

loop2: sw $zero, 0($t0) # Memory[p]=0addi $t0, $t0, 4 # p=p+4 add $t1, $a1, $a1 # $t1=i*4add $t1, $t1, $t1 #(sll $t1, $a1, 2)add $t2, $a0, $t1 # $t2=address of array[size]slt $t3, $t0, $t2 # $t3=(p<&array[size])bne $t3, $zero, loop2 # if (p<&array[size]) goto loop2

array: $a0size: $a1p: $t0

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Design alternative:

provide more powerful operations

goal is to reduce number of instructions executed

danger is a slower cycle time and/or a higher CPI

Sometimes referred to as “RISC vs. CISC”

virtually all new instruction sets since 1982 have been RISC

VAX: minimize code size, make assembly language easy

instructions from 1 to 54 bytes long!

We’ll look at PowerPC and 80x86

Alternative Architectures

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PowerPC

Indexed addressingexample: lw $t1,$a0+$s3 #$t1=Memory[$a0+$s3]

What do we have to do in MIPS?

Update addressingupdate a register as part of load (for marching through arrays)

example: lwu $t0,4($s3) #$t0=Memory[$s3+4];$s3=$s3+4

What do we have to do in MIPS?

Others:load multiple/store multiple

a special counter register “bc Loop” decrement counter, if not 0 goto loop

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80x86

1978: The Intel 8086 is announced (16 bit architecture)

1980: The 8087 floating point coprocessor is added

1982: The 80286 increases address space to 24 bits, +instructions

1985: The 80386 extends to 32 bits, new addressing modes

1989-1995: The 80486, Pentium, Pentium Pro add a few instructions

(mostly designed for higher performance)

1997: MMX is added

“This history illustrates the impact of the “golden handcuffs” of compatibility“adding new features as someone might add clothing to a packed bag”“an architecture that is difficult to explain and impossible to love”

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A dominant architecture: 80x86

See your textbook for a more detailed description

Complexity:Instructions from 1 to 17 bytes long

one operand must act as both a source and destination

one operand can come from memory

complex addressing modes

e.g., “base or scaled index with 8 or 32 bit displacement”

Saving grace:the most frequently used instructions are not too difficult to build

compilers avoid the portions of the architecture that are slow

“what the 80x86 lacks in style is made up in quantity, making it beautiful from the right perspective”

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Some typical 80x86 Instruction & their functionsSome typical 80x86 Instruction & their functions

JE name

JMP name

CALL name

MOVW EBX,[EDI + 45]

PUSH ESI

POP EDI

ADD EAX,#6765

TEST EDX,#42

MOVSL

If equal (CC) EIP = name};EIP– 128 name < EIP + 128

{EIP = NAME};

SP = SP – 4; M[SP] = EIP + 5; EIP = name;

EBX = M [EDI + 45]

SP = SP – 4; M[SP] = ESI

EDI = M[SP]; SP = SP + 4

EAX = EAX + 6765

Set condition codea (flags) with EDX & 42

M[EDI] = M[ESI];EDI = EDI + 4; ESI = ESI + 4

FunctionInstruction

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Typical 80x86 instruction formatsTypical 80x86 instruction formats

JE

JE EIP + displacement

Offset

CALL

MOV EBX, [EDI + 45]

PUSH

PUSH ESI

ADD w

ADD EAX, #6765

Reg

4 4 8

6

8 32

5 3

4 13 32

Immediate

Condition

MOV

1

w

1

d

8 8

TEST EDX, #42

7 1 8 32

TEST Postbyte Immediatew

Reg

f.

e.

d.

c.

b.

a.

CALL

Displacementr-m

postbyte

Displacement

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Instruction complexity is only one variablelower instruction count vs. higher CPI / lower clock rate

Design Principles:simplicity favors regularity

smaller is faster

good design demands compromise

make the common case fast

Instruction set architecturea very important abstraction indeed!

Summary

chapter 2 instructions: language of the machine

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