chip design < work on palpidefs >
DESCRIPTION
Chip design < Work on pALPIDEfs >. KIM,D.H. , KWON,Y. ,SONG,M.K. Department of Semiconductor Science, Dongguk Univ. for the ALICE collaboration. Department of Physics, Yonsei Univ. for the ALICE collaboration. < CONTENTS >. pALPIDEfs – work on DACs - PowerPoint PPT PresentationTRANSCRIPT
System IC Design Lab.
Dongguk University1
Chip design< Work on pALPIDEfs >
KIM,D.H. , KWON,Y. ,SONG,M.K.
Department of Semiconductor Science,Dongguk Univ. for the ALICE collaboration.
Department of Physics, Yonsei Univ. for the ALICE collaboration.
System IC Design Lab.
Dongguk University2
< CONTENTS >
I. pALPIDEfs – work on DACs
II. pALPIDEfs version 2 – work on I/O PAD
III. Next plan
System IC Design Lab.
Dongguk University3
I. pALPIDEfs – work on DAC - Layout of pALPIDEfs
Pixel Matrix: sensitive area
Periphery circuit ( DACs, PADs, periphery readout logic, etc)
Matrix
DACs
Periphery Logic
I/O pads
System IC Design Lab.
Dongguk University4
I. pALPIDEfs – work on DAC DAC - List of Voltage and Current DACs
Voltage DAC Current DAC
Resolution • 8bit • 8bit
Type • Resistor • pMOS
Output/unitcol-umn
• 6EA 1) VCASP 2) VCASN 3) VRESET 4) VPULSE_LOW 5) VPULSE_HIGH 6) VAUX
• 5EA 1) IBIAS 2) ITHR 3) IDB 4) IAUX1 5) IAUX2
System IC Design Lab.
Dongguk University5
I. pALPIDEfs – work on DAC DAC – Voltage DAC
Bottom
Top
Resistor (256)
Unit cell (256)
Control Block(256)
VCASP
VCASN
VRESET
DACMONV
VPLSE_HIGH
VAUX
SET
_VC
ASP
<255
:0>
SET
_VC
ASN
<255
:0>
SET
_VR
ESE
T<2
55:0
>
SET
_VPL
SE_L
OW
<255
:0>
SET
_VPL
SE_H
IGH
<255
:0>
SET
_VA
UX
<255
:0>
VPLSE_LOW
VC
ASP
VC
ASN
VR
ESE
T
VPL
SE_L
OW
VPL
SE_H
IGH
VA
UX
SWC
NT
L_V
CA
SP
SWC
NT
L_V
CA
SN
SWC
NT
L_V
RE
SET
SWC
NT
L_V
PLSE
_LO
W
SWC
NT
L_V
PLSE
_HIG
H
SWC
NT
L_V
AU
X
SWC
NT
L_D
AC
MO
NV
VR
ESE
T_I
NT
VPL
SE_L
OW
_IN
T
VPL
SE_H
IGH
_IN
T
VA
UX
_IN
T
VRESET_INT
VPLSE_LOW_INT
VPLSE_HIGH_INT
VAUX_INT
SET_VCASP
SET_VCASN
SET_VRESET
SET_VPLSE_LOW
SET_VPLSE_HIGH
SET_VAUX
SWCNTL_VCASPB
SWCNTL_VCASNB
SWCNTL_VRESETB
SWCNTL_VPLSE_LOWB
SWCNTL_VPLSE_HIGHB
SWCNTL_VAUXB
SWCNTL_DACMONVB
SWCNTL_VCASP
SWCNTL_VCASN
SWCNTL_VRESET
SWCNTL_VPLSE_LOW
SWCNTL_VPLSE_HIGH
SWCNTL_VAUX
SWCNTL_DACMONVB
SWCNTL_DACMONVB
SWCNTL_DACMONVB
SWCNTL_DACMONVB
SWCNTL_DACMONVB
VR
EF
AV
SS
DA
CR
EF
VCASP VCASN VRESET VPLSE_LOW
VPLSE_HIGH VRESET
0 0 0 368mV 368mV 368mV 368mV255 1.8V 1.8V 1.8V 1.8V 1.8V 1.8V
<Voltage DACS output range at nominal corner simulation>
VREF AVSS
<Voltage DAC resistor divider> <Voltage DAC unit block >
• Block diagram & Simulation result
System IC Design Lab.
Dongguk University6
I. pALPIDEfs – work on DAC DAC – Current DAC
• Block diagram & Simulation result
Current DAC Current reduc-tion
SLOW@ 1.62V , 60°C
NOM@ 1.8V , 27°C
FAST@ 1.98V , 0°C
0 255 0 255 0 255
IBIAS 1 : 128 90pA 15nA 300pA 80.4nA 2nA 500nA
ITHR 1 : 4096 10pA 0.65nA 12pA 2.56nA 60pA 15.5nA
IDB 1 : 256 46pA 10.6nA 162pA 41.7nA 1nA 259nA
IRESET 1 : 256000 0.8pA 2.56pA 0.7pA 26.2pA 0.9pA 192pA
IAUX2 1:1 Not used
Unit cell (256)
AVSS
AVSS
AVSS
VDD
ITHR_MTX_INT
AVSS
AVSS
AVSS
AVDD IBIAS_MTX_INT
SET_IAUX
SET_IBIAS
SWCNTL_IBIASb SWCNTL_IBIAS
SWCNTL_IBIAS
SWCNTL_DACMONb
SWCNTL_IAUXb SWCNTL_IAUX
SWCNTL_IAUX
SWCNTL_DACMONb
C u r r e n t m i r r o r
C u r r e n t m i r r o r
C u r r e n t m i r r o r
C u r r e n t m i r r o r
IAUX_INT
IBIAS_INT IBIAS_MTX_INT
IDB_MTX_INT
IRESET_MTX_INT
IAUX
IAUX
ITHR
IBIAS
IDB
IRESET
SET
_IB
IAS<
255:
0>
SET
_IT
HR
<255
:0>
SET
_ID
B<2
55:0
>
SET
_IR
ESE
T<2
55:0
>
SET
_IA
UX
<255
:0>
SWC
NT
L_I
BIA
S
SWC
NT
L_I
TH
R
SWC
NT
L_I
DB
SWC
NT
L_I
RE
SET
SWC
NT
L_I
AU
X
SWC
NT
L_D
AC
MO
NI
Control Block(256)
IBIAS_INT
ITHR_INT
IDB_INT
IRESET_INT
IAUX_INT
DA
CR
EF
<Current DACs scheme><Current DACs, corner simulations results>
System IC Design Lab.
Dongguk University7
II. pALPIDEfs Version 2 – work on PAD - Specification of I/O PAD
PAD
Output driver
InputBuffer
R1 R2
R3
Chip<0>
PAD
Output driver
InputBuffer
R1 R2
R3
CPAD
CCABLE
RCABLE
Chip<6>
CPAD
CABLE
Property of Cable• R=170mΩ/cm @ W= 100um• C=1pF/cm @ W= 100um
100um
21cm
• RCABLE = 3.57 Ω• CCABLE = 21pF
3.57 Ω 21pF
6pF 6pF
10 Ω 10 Ω 50 Ω 50 Ω
Pull down or Pull up
Total Load at the output driver• RLOAD = 3.57Ω + 10 Ω ≈ 14Ω • CLOAD = 6pF x 7 + 21pF ≈ 65pF
40 kΩ
DVDD or DVSS
40 kΩ
DVDD or DVSS Pull down or Pull up
System IC Design Lab.
Dongguk University8
II. pALPIDEfs Version 2 – work on PAD - design of I/O PAD
92um
90um
CIN
OEN
D_O
UT
PAD
DVSS
DVDD
AVSS
AVDD
SUB
ESD diode
Buffer & Resistor
PAD
Output driver
InputBuffer
10Ω
CPAD
50Ω
40kΩ
DVSS
CIN
OEN
D_O
UT
PAD
< Layout of I/O PAD>
< Block diagram of I/O PAD>
CINDOUT
System IC Design Lab.
Dongguk University9
II. pALPIDEfs Version 2 – work on PAD - Simulation result of I/O PAD
CIN
OEN
D_O
UT
PAD
TypeStructure
Type Result
Standard Core Input Transition = 0.5 ns Pad Load = 4Ω ,65pFSlow (80°C) Normal (25°C) Fast (0°C)
Rising Falling Rising Falling Rising Falling
R1 = 10Ω for protect buffer, 1x buf -fer
Out-put Driver(CorePAD)
Transi(ns) 4.96 5.43 4.11 4.11 3.29 3.61
tCMOS(ns) 323 3.76 2.50 2.80 1.96 232
tOE(ns) 6.30 6.20 4.60 4.66 3.81 4.06
Input Buf -fer(PADCore)
Transi(ns) 0.58 0.26 0.44 0.18 0.34 0.15
tCD(ns) 0.56 0.44 0.41 0.34 0.31 0.28
Power DVDD(pJ)
Tot. Int. Load. Tot. Int. Load. Tot. Int. Load.
174.6 4 170.6 215.9 5.3 210.6 261.
9 7.1 254.8
DOUT
PAD
50%
35% 65%
50%
tCMOS(falling) tCMOS(rising)
10%90%
Transition(falling)T1 T2 T3 T4
Transition(rising)
90%10%
Dout
90%50%
10%
50%90%10%
50%65%35%
Post simulation result of PAD_I/O (with parasitic parameter) Output driver : Delay < 5ns @ Load : 4Ω, 65pF Input buffer : Load : 0.5Ω, 160fF
System IC Design Lab.
Dongguk University10
III. Next plan - Study of discriminator
CIN
OEN
D_O
UT
PAD
VRESET
PWELL
IBIAS_PIX
source
curfeed
VCASP
VDDA
GNDA
HITB
VCASN
ITHR_PIX
IDB
D0
D1
M0
M1
M2
M3
Cs
Cf
M4
M5M6
M7
<pALPIDEfs Front-End principle>
• Analysis of front-end and design new structure
System IC Design Lab.
Dongguk University11
Thank you