chp 4- asics
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ASIC and FPGA
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What is an ASIC? ASIC -- Application-specific integrated circuit.
An ASIC is an
Integrated Circuit for a Specific Application.
A kind of integrated circuit, often referred to as
"gate-array" or "standard-cell" products.
It is developed and designed to satisfy a specific application
requirement as opposed to a general purpose circuit, such as a
microprocessor.
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Examples of ASICs
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ROMs,
DRAM and SRAM
Microprocessors
TTL equivalent ICs at SSI, MSI, and LSI levels. Etc
Example of ICs that are not ASICs:
Example of ICs that are ASICs:
A Chip for a toy that talks
A chip for satellite
A chip designed to Handle the interface between memory
and microprocessor for work station CPU. Etc.
Note : If the IC has data sheet, then it is probably not an ASIC
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ASIC-Benefits
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Origin of ASICs The standard parts
Initially used to design Microelectronic Systems
Gradually replaced with a combination of
Glue Logic
Custom ICs
Dynamic Random Access Memory (DRAM)
Static Random Access Memory (SRAM)
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ASIC-Drawbacks
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ASICs Manufacturing Process ICs made on a wafer
Circuits are made up of a successive mask
layers The number ofMasks used to define the
interconnect
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Types of ASICs
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Full custom ASICs Semi custom ASICsProgrammable ASICs
ASICs
Standard-CellBased Gate-ArrayBased
Channeled Gate Array Channel less Gate Array Structured Gate Array
PLDs FPGA
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FULL CUSTOM ASICs
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Why full Custom ASICs?
Constraints and Optimizations
Speed
Power Consumption
Chip Size
New Technology
If there are no libraries available
Engineer design some or all logic cells/circuits/layout specially
for one ASIC
This approach used only if there are no suitable existing cell librariesnot available.
Full custom is mainly used for high-volume high-end circuits.
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Designing Full custom ASICs
Designing the desired technology node library
components using the
Layout editors Check for DR
Simulate the circuit using the layout level
simulators
Magic - IRSIM
Mentor IC Station - LVS
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Full Custom ASICs Fabrication
All mask layers are customized in a full-
custom ASIC.
Full custom design consists of a complete setof masks
One for each step in fabrication process
Data files required to specify mask sets createdusing a layout editor within a CAD tool
Eg: Magic, Mentor IC Station
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Examples Full custom ASICs
High-voltage (automobile) Electronics,
analog/digital Circuits (communications),
Sensors
Actuators (transform an electrical signal
into motion) MEMS (Micro Electro Mechanical Systems)
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Examples Full custom ASICs
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Mixed signal Full custom ASIC
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Full custom ASICs
Advantages
Highest performances
Lowest part cost (Smallest Die size) Disadvantages
Increased design time,
Complexity, Design expense, and
Highest risk (Design risk, Pentium 2).
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Semi-Custom ASICs Standard Cell Based ASICs
Gate Array Based ASICs
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Standard Cell Based ASICs
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VDD
VSS
feed througharea
transistors
externalconnection
poin ts
Standard cell:
A cell that performs a dedicated function. For instance 2 input NAND,
XOR, D flip-flop etc. Designer works with cells and is not bothered about
transistor level details.
A cell library holds relevant information about
cells. For instance, name, functionality, delays,
resistance, capacitance, layout, area, pin
topology etc. All cells in a library have samestandardized layouts, i.e., all cells have the
same height.
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Standard Cell Based ASICs A cell-based ASIC (CBICsea-bick)
CBIC are built of rows of standard cells- like a wall built of bricks
Standard Cells Types:
Megacells,
Megafunctions,
Full custom blocks,
System Level Macros,
Fixed blocks,
Cores or Functional Standard Blocks19
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Standard Cell Based ASICs
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Standard Cell Layout
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cells
routing arearouting
area
feedthroughcell
wastedspace
Metal2 Metal 1
Metal 1
Metal2
No contact
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Standard Cell Based ASICs (Contd..)
The ASIC designer defines only the
placement of standard cells and interconnect
in CBIC All mask layers are customizedtransistors
and interconnect
Custom blocks can be embedded Manufacturing lead time is about eight weeks.
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Standard Cell Based ASICs
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CBIC design style offerssame performance andflexibility advantages ofFull
custom ASIC but reducestime and risk
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Advantages & Disadvantages
Advantages:
CBIC designer will save time, money, and reduce
risk by using a predesigned , Protested, andprecharactarised Standard- cell Library.
Disadvantage:
Each standard cell in library is constructed usingfullcustom design methodology.
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Gate Array Based ASICs
A gate array, masked gate array (MGA), or pre-diffusedarray uses macros.
A gate arraybased ASIC consists of regular arrays of
unconnected transistorson the Si Wafer. The predefined pattern of transistors on a gate array is
know as base array.
The smallest element that is replicated to make the base
array is the base cell. It comprises a base array made from a base cell or
primitive cell.
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Gate Array Based ASICs
The logic cells in a gatearray library are oftencalled as Macros.
The designer has only todesign the final interconnectpattern using
logic cells in a cell library
powerful CAD tools.
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ASIC for Brushless DC drive controller
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Year: 1993
Technology: CMOS Gate array
No. of gates : 20,000
Feature size: 1um
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Gate Array Based ASICs - Types
Gate Arrays are three types:
Channeled Gate Arrays
Channel-less Gate Arrays Structured Gate Arrays
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Channeled Gate Array
Only the interconnect is customized
The interconnect uses predefined spaces
between rows of base cells known as channel. Manufacturing lead time is between two days
and two weeks
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Channeled Gate Array
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Channel-less Gate Array
A channel-free gate array,
sea-of-gates array (SOG array).
No Channel or spaces between rows of base cells. Only some (the top few) mask layers are customized
- the interconnect
Manufacturing lead time is between two days and
two weeks.
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Channel-less Gate Array
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Structured Gate Array
An embedded gate array or structured gate array (master-slice
or master-image)
Only the interconnect is customized
Custom blocks (the same for each design) can be embedded
Manufacturing lead time is between two days and two weeks.
Structured ASICs are used mainly for mid-volume level
designs
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Structured Gate Array
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Structured ASIC Advantages
Largely Prefabricated
Components are almost
connected in a variety ofpredefined configurations
Only a few metal layers are
needed for fabrication Drastically reduces
turnaround time
Pre-Routed Layer
Pre-Routed Layer
Pre-Routed Layer
Routing Layer
Routing Layer
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Structured ASIC Advantages
Capacity, performance, and power
consumption closer to that of a standard cell
ASIC. Faster design time, reduced NRE costs, and
quicker turnaround.
Therefore, the per-unit cost is reasonable forseveral hundreds to 100k unit production runs.
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Structured ASIC Disadvantages
Lack of adequate design tools
Expensive
Altered from traditional ASIC tools
These new architectures have not yet been
subject to formal evaluation and comparative
analysis Tradeoffs between 3-, 4-, and 5-input LUTs
Tradeoffs between sizes of distributed RAM
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Programmable Logic Devices(PLDs)
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What is PLD?
A Programmable Logic Device is an integrated circuitwith internal logic gates and interconnects. These gatescan be connected to obtain the required logic
configuration through a program (HDL).. The term programmable means changing either
hardware or software configuration of an internal logicand interconnects.
The configuration of the internal logic is done by theuser.
PROM, EPROM, PAL, GAL etc. are examples ofProgrammable Logic devices
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Why Programmable Logic?
Facts:
It is most economical to produce an IC in largevolumes
Many designs require only small volumes of ICs
Need an IC that can be:
Produced in large volumes
Handle many designs required in small volumes
A programmable logic part can be:
Made in large volumes
Programmed to implement large numbers of
different low-volume designs
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Programmable Logic Devices
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Programmable Logic Devices
No customized mask layers or logic cells
Fast design turnaround
A single large block of programmableinterconnect
A matrix of logic macro cells that usually
consist of programmable array logic followedby a flip-flop or latch
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Mask programming:
Programming of device is done in the mask level.
Advantages:
Good timing performance due to internal connections hardwiredduring manufacture
Cheap at high volume production
Disadvantages: Programmed by manufacturer
Development Cycle Time may be Weeks or Months Not Re-programmable
Field programming:
Programming of device is done by the user.
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PLD Programming Types
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Technology Characteristics
Permanent - Cannot be erased and reprogrammed Mask programming
Fuse
Antifuse
Reprogrammable
Volatile - Programming lost if chip power lost
Single-bit storage element
Non-Volatile
Erasable
Electrically erasable
Flash (as in Flash Memory)
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Programmable Logic - Advantages
Many programmable logic devices are field- programmable, i.e., can be programmed outside of the manufacturingenvironment.
Most programmable logic devices are erasable andreprogrammable.
Allows updating a device or correction of errors
Allows reuse the device for a different design - the ultimate inre-usability!
Ideal for course laboratories
Programmable logic devices can be used to prototype designthat will be implemented for sale in regular ICs.
Complete Intel Pentium designs were actually prototype withspecialized systems based on large numbers of VLSIprogrammable devices!
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Programmable Configurations
Read Only Memory (ROM) - a fixed array of AND gates and
a programmable array of OR gates
Programmable Array Logic (PAL) - a programmable array
of AND gates feeding a fixed array of OR gates.
Programmable Logic Array (PLA) - a programmable array
of AND gates feeding a programmable array of OR gates.
Complex Programmable Logic Device (CPLD) /Field-
Programmable Gate Array (FPGA) - complex enough to be
called architectures -
PAL is a registered trademark of Lattice Semiconductor Corp.
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ROM, PAL and PLA Configurations
(a) Programmable read-only memory (PROM)
InputsFixed
AND array(decoder)
ProgrammableOR array
OutputsProgrammable
Connections
(c) Programmable logic array (PLA) device
Inputs ProgrammableOR array
OutputsProgrammable
Connections
Programmable
ConnectionsProgrammable
AND array
(b) Programmable array logic (PAL) device
Inputs ProgrammableAND array
FixedOR array
OutputsProgrammable
Connections
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Programmable Array Logic (PAL)
The PAL is the opposite of the ROM, having a programmable
set of ANDs combined with fixed ORs.
Disadvantage
ROM guaranteed to implement any M functions of N
inputs. PAL may have too few inputs to the OR gates.
Advantages
For given internal complexity, a PAL can have larger N and M
Some PALs have outputs that can be complemented, adding POS functions
No multilevel circuit implementations in ROM (without external connectio
from output to input). PAL has
outputs from OR terms as internal inputs to all AND
terms, making implementation of multi-level circuits easier.
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PAL
Structure
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AND gates inputs
0 91 2 3 4 5 6 7 8
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0 91 2 3 4 5 6 7 8
Productterm
1
2
3
4
5
6
7
8
9
10
11
12
F 1
F 2
F 3
F 4
I3 C
I2 B
I 1 A
I4
X X
X X
X X X
X X
X
X
X
XX
X
X X
X
X X
PAL Example
AND gates inputs
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PAL Example
4-input, 3-output PAL
with fixed, 3-input OR
terms What are the equations
for F1 through F4?
F1 = AB + C
F2 = ABC + AC + AB
F3 = ?
F4 = ?
0 91 2 3 4 5 6 7 8
AND gates inputs
0 9
Productterm
1
2
3
4
5
6
7
8
9
10
11
12
F1
F2
F3
F4
I3 C
I2 B
I1 A
1 2 3 4 5 6 7 8
I4
X X
X X
XX X
X X
X
X
X
XX
X
X X
X
X X
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Programmable Logic Array (PLA)
Compared to a ROM and a PAL, a PLA is the most flexible having a
programmable set of ANDs combined with a programmable set of
ORs.
Advantages
A PLA can have large N and M permitting implementation of equations
that are impractical for a ROM (because of the number of inputs, N,
required
A PLA has all of its product terms connectable to all outputs,
overcoming the problem of the limited inputs to the PAL Ors
Some PLAs have outputs that can be complemented, adding POS
functions
Disadvantage
Often, the product term count limits the application of a PLA. Two-
level multiple-output optimization reduces the number of product terms
in an implementation, helping to fit it into a PLA.
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PLA
Structure
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Example: PLA
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PLA Example
3-input, 3-output PLAwith 4 product terms
What are the equations for F1 and F2?
Could the PLA implement the
functions without the XOR gates?
Fuse intact
Fuse blown
1
F1
F2
X
A
B
C
C C B B A A 0
1
2
3
4X
XX
X X
X
X
X
X
X
X
X
X
X
A B
A C
B C
A B
X
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PLAs Vs PALs
PLAs are more flexible than PALs
PALs operate faster, because hard-wired
connections take less time to switch than theirprogrammable equivalents.
PALs are Cheap to manufacture.
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Why CPLDs ?
Atmel 16V8 PLD (20 Pins)
can have 16 inputs (max) and/or 8 outputs (macrocells)
has 32 inputs to each of the AND gates (product terms)
Lattice 22V10 PLD (24 pins)
can have 22 inputs and/or 10 outputs (max)
has 44 inputs to each of the AND gates
How about a 128V64 for larger applications?
It will be slower and will more wasted silicon space
Solution? Use CPLDs
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CPLDComplex PLD
A collection of PLDs on a
single chip with
Programmable interconnectsis known as Complex PLD.
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CPLD Architecture
CPLD Architecture
consists of
Function blocks
I/O blocks Interconnect Matrix.
The devices are
programmed using the
technology of EPROM or
EEPROM cells.
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PLDBlock
PLDBlock
Interconnection Matrix
I/O
Block
I/O
Block
PLDBlock
PLDBlock
I/O
Block
I/O
Block
Interconnection Matrix
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Example CPLD Families
Altera MAX 5000 and MAX 7000 families
AMD MACH family
Atmel ATV family Lattice ispLSI and pLSI families
Xilinx XC9500 family
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CPLD and FPGA
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Field Programmable Gate Arrays
The name Field Programmable Gate Arrays (FPGA) is due to
similar structure like gate array ASIC.
This makes FPGAs very nice for use in prototyping ASICs,
or in places where and ASIC will eventually be used. FPGA has narrower logic choices and more memory
elements. LUT (Lookup Table) may replace actual logic
gates.
Design turnaround time is only a few hours
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Lookup Table
A LUT (Lookup table) is a one bit wide memory array
A 4-input AND gate is replaced by a LUT that has four
address inputs and one single bit output with 16 one bit
locations Location 15 would have a logic value 1 stored, all others
would be zero
LUTs can be programmed and reprogrammed to change the
logical function implemented
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Field Programmable Gate Arrays
An FPGA is usually just larger and more complex
than a PLD
None of the mask layers are customized A method for programming the basic logic cells and
the interconnect
Array of programmable basic logic cells that can
implement
Combinational and
Sequential logic65
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FPGA - Generic Structure
FPGA building blocks:
Programmable logic blocks
Implement combinatorial andsequential logic
Programmable interconnect
Wires to connect inputs and outputs to
logic blocks Programmable I/O blocks
Special logic blocks at the periphery
of device for external connections
I/O
I/O
Logicblock
Interconnection switches
I/O
I/O
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FPGA Architecture
The architecture consists of
Configurable Logic blocks
Configurable I/O blocks
Programmable interconnect.
Clock circuitry for driving the clock signals to each logic block,
Additional logic resources such as ALUs, memory, and decoders may
be available.
The two basic types of programmable elements for an FPGA
are Static RAM and anti-fuses.
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Programming types in FPGA
SRAM Programming
It involves small Static RAM bits for each programming element.
Writing the bit with a zero turns off a switch, while writing with a one
turns on a switch.
Anti-fuse Programming
It consist of microscopic fuses which, unlike a regular fuse, normally
makes no connection.
A certain amount of current during programming of the device causes
the two sides of the fuse to connect.
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Basic FPGA Operation
Write Configuration Memory
Defines system function
Input/Output Cells
Logic in Cells Connections between Logic cells & I/O cells
Changing configuration
memory data => changes system function
Configuration can change at anytime Even while system function is in operation
Run-time reconfiguration (RTR)
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Advantages of FPGA
Faster time-to-market - no layout, masks or other
manufacturing steps are needed
No upfront NRE (non recurring expenses) - costs typically
associated with an ASIC design
Simpler design cycle - due to software that handles much of
the routing, placement, and timing
More predictable project cycle - due to elimination of
potential re-spins, wafer capacities, etc.
Field reprogramability - a new bit stream can be uploaded
remotely
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Example FPGA Families
SRAM based FPGA families
Altera FLEX family
Atmel CLi family
Lucent Technologies ORCA family
Xilinx XC2000, XC3000, XC4000 families
Anti-fuse based FPGA families
Actel ACT1, ACT2, ACT3 families Quicklogic pASIC family
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Difference in CPLDs & FPGAs
As they grow larger, there is less difference
Primary difference is in combinational logic
CPLDs use programmable logic arrays (PLAs) with 8 to
16 product terms of many inputs
Programmable logic blocks tend to be large
8 to 16 macrocells
FPGAs used small RAMs as look-up tables (LUTs) to
hold the truth table for small Boolean functions of 4 to 5
inputs
Programmable logic blocks tend to be small
2 to 4 flip-flops (macrocells)
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Easy to Design
Short Development Time
Low NRE Costs
Design Size Limited
Design Complexity
Limited
Performance Limited
High Power Consumption
High Per-Unit Cost
Difficult to Design
Long Development Time
High NRE Costs
Support Large Designs
Support Complex Designs
High Performance
Low Power ConsumptionLow Per-Unit Cost (at high
volume)
FPGA Standard Cell ASIC
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VLSI DESIGN FLOW
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Major EDA Vendors:
Cadence
Synopsys
Magma Mentor Graphics
Atrenta
Xlinx
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Traditional VLSI Design Flow
Concept + Market research
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Architectural Specs &
RTL coding
RTL Simulation
Logic Synthesis,
Optimization &
Scan Insertion
Formal Verification(RTL Vs Gates)
Pre-layout STA
Floor planning,
Placement,
CT insertion &
Global Routing
Timing
OK?
Transfer Clock
Tree to DC
Formal Verification
(Scan inserted netlist
Vs
CT inserted Netlist)
Post Global route STA
Timing
OK?
Detailed Routing
Post-layout STA
Timing
OK?
Tape out
Concept + Market research
Yes
NoYes
No
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VLSI Design Cycle Steps
New trends alter this flow. e.g. Physical Synthesis
System specification
Architectural Level Synthesis
-- Architectural Design (VHDL Code)
-- Behavioral/Functional Design (Simulation)
Logic-level Synthesis
-- Logic Design (gate representation)
-- Circuit Design (CMOS representation)79
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VLSI Design Cycle Steps (contd.)
Geometrical Level Synthesis (Physical Design)
-- Partitioning
-- Floorplanning
-- Placement
-- Routing: Global and Detailed
-- Compaction
-- Extraction and Verification
Fabrication
Packaging, Testing and Debugging
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System Specification
High level representation of the system
Performance, functionality, physical dimensions
Economic viability
Fabrication technology
Design techniques
Speed, Power
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Architectural Design
Basic architecture designed in this step
Instruction set
Number of ALUs, floating point units
Enables check on early estimates of power,
performance, size, to see if they meet specs
Estimates based on existing designs
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Functional Design
Main functional units are identified
Set of operations and dependencies.
Identify hardware resources to implement theoperations, scheduling the execution time ofoperations, binding them to resources
Interconnect requirement between units are identified
Area, power other parameters estimated
Behaviour in terms of input, output, timing of each unit, without specifying internal structure
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Logic Design
Control flow, word widths, register allocation,
arithmetic operations, logic operations are derived
Description can be used in simulation and
verification
Boolean expressions minimized
Sequential logic optimization
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Circuit Design
Convert Boolean expressions to circuitrepresentation
Logic networks replaced by interconnection of gates,
cells etc. Technology Mapping: mapping design to cells from
a standard library
Interconnection represented by a netlist
In traditional design flow, netlist passed on toPhysical Design tools
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Physical Design
Netlist converted to a geometric representation (layout)
Specify geometric patterns defining the physical layout, aswell as their position
Each logic component (gates, transistors etc.) is convertedinto geometric representation in several layers
Broken up into substeps:
Circuit partitioning, floorplanning and placement, routing,compaction, extraction and verification
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Circuit partitioning
Millions of transistors on a single chip
Not feasible to layout the entire chip in a single step
Design partitioned into subcircuits (blocks)
Output is a set of blocks and interconnections between them Partitioning may be hierarchical (blocks subdivided into sub-
blocks)
System may be partitioned into functional blocks and eachblock implemented as a separate chip
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Floorplanning and Placement
Floorplanningrelative positions of the blocks aredecided
Actual shape of the block may be varied Certain components have to located at specific
positions
During placement blocks are exactly positioned
Goal: To find a minimum area arrangement of blocksthat allows interconnections between blocks and meetsall performance requirements
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Routing
Complete interconnection between blocks according tospecified netlist
Empty space not occupied by blocks divided into
channels and switchboxes Global routing: Specify list of channels and switchboxes
through which each wire needs to be routed
Detailed Routing: Exact geometric information like
location and spacing of wires and layer assignmentsspecified. Done for each channel and switchbox
Routing completion important: rip out and re-routeused.
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Compaction
Reducing area by compressing layout
Compact layout requires smaller wires and reduces
delays.
Need to ensure that design rules are not violated
Extensive compaction used only for large applications
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Extraction and Verification
DRC: design rule checking to verify if all geometricpatters meet the design rules of the fabrication process.
Functionality verified by Circuit Extraction Extracted description is compared with circuit
description (Layout versus schematic or LVS).
RC extraction: Geometric information extracted tocompute resistances and capacitances
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ASIC Design FLOW
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1.Enter the design into an ASIC design system, eitherusing a hardware description language ( HDL ) or
schematic entry
g
ASIC Design FLOW
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2.Use an HDL (VHDL or Verilog) and a logic synthesis toolto produce a netlist a description of the logic cells andtheir connections
ASIC Design FLOW
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3. System partitioning. Divide a large system into ASIC-sized pieces
ASIC Design FLOW
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4.Prelayout simulation. Check to see if the designfunctions correctly
ASIC Design FLOW
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6. Placement. Decide the locations of cells in a block
ASIC Design FLOW
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7.Routing. Make the connections between cells and blocks
ASIC Design FLOW
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8. Extraction. Determine the resistance and capacitance of theinterconnect
ASIC Design FLOW
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9.Postlayout simulation. Check to see the design still works withthe added loads of the interconnect.
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ASIC Design FLOW1. Design entry. Enter the design into an ASIC design system, either using a
hardware description language ( HDL ) or schematic entry .
2. Logic synthesis. Use an HDL (VHDL or Verilog) and a logic synthesis
tool to produce a netlista description of the logic cells and their
connections.
3. System partitioning. Divide a large system into ASIC-sized pieces.4. Prelayout simulation. Check to see if the design functions correctly.
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ASIC Design Flow (Contd..)
Floorplanning. Arrange the blocks of the
netlist on the chip.
Placement. Decide the locations of cells in ablock.
Postlayout simulation. Check to see the
design still works with the added loads of the
interconnect.
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FPGA Design Flow
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FPGA Design Flow
Functional Specs
HDL
Synthesis
Place & Route
Download and
Verify in Circuit
Behavioral
Simulation
Static TimingAnalysis
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Xilinx Spartan FPGA Kit