chuong04 datapath và pipeline

8/10/2019 Chuong04 Datapath V Pipeline

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CE

CHNG 4

B X L (THE PROCESSOR)

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KIN TRC MY TNH


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CE

CHNG 4


Phn 1. Xy dngngtruyndliu(Datapath)

Phn 2. Kthutngdn(Pipeline)

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KIN TRC MY TNH


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CEB X L

Nidung phn11. Giithiu

2. Nhclicc quy cthitklogic

3. Xy dngngtruyndliu(datapath) ngin

4. Hin thcdatapath nchu k

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CEB X L

Nidung1. Giithiu




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CEGiithiu

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Hiusutcamtmy tnh cxc nhbiba yut:

Tngscu lnh cxc nhbitrnh bin dchv kintrc tplnh

Chu kxung clock

Schu kxung clock trn mtlnh

(Clock cycles per instruction CPI)

Mcchchnh cachngny:- Giithch quy tchotngv hngdnxy dngdatapath cho mtbxl

chamtslnh ngin(gingkintrc tplnh dngMIPS), gmhai

chnh: Thitkdatapath

Hin thcdatapath thitk

MIPS (btnguntchvitttcaMicroprocessor without Interlocked Pipeline Stages) l mtkintrc tptplnh dngRISC, cpht trinbiMIPS Technologies (trcyl MIPSComputer Systems, Inc.)

cxc nhbiqutrnh hinthcbxl


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CEGiithiu

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Chngny chxem xt 8 lnh trong 3 nhm chnh catplnhMIPS:

Nhm lnh tham khobnh(lw v sw)

Nhm lnh lin quan nlogic v shc(add, sub, AND, OR, v slt)

Nhm lnh nhy(Lnh nhyviiukinbngbeq)


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CEGiithiu

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Tngquan cc lnh cnxem xt:

Nhm lnh tham khobnh:

Nplnhcmt/hai thanh ghiSdngALUTruy xutbnhc/ghi d

liu

Nhm lnh logic v shc:

Nplnhcmt/hai thanh ghiSdngALUGhi dliuvo thanh ghi

Nhm lnh nhy:

Nplnhcmt/hai thanh ghiSdngALUChuynnachlnh tip

theo datrn ktquso snh


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CEGiithiu

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Hnh nhdatapath camtbxl vi8 lnh MIPS: add, sub, AND, OR, slt,lw, sw v beq

Nplnh

cmt/hai thanh ghi

SdngALUGhi dliuvo thanh ghi


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CEB X L

Nidung1. Giithiu




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CEQuy cthitk

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Phn ny nhclicc khi nim:

Mch thp(Combinational): ALU

Mch tunt(Sequential): instruction/data memories v thanh ghi

Tn hiuiukhin(Control signal)

Tn hiudliu(Data signal)

Asserted (assert): Khi tn hiu mccao hoctrue

Deasserted (deassert):Khi tn hiu mcthphocfalse

Bus


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CEB X L

Nidung1. Giithiu




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CEXy dngDatapath

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Cc thnh phntrong mtdatapath bao gm: bnhlnh v dliu

(instruction and data memories), tpcc thanh ghi (register file/registers), ALUv bcng(Adders).

Program Counter (PC): l thanh ghi chaachcalnh angcthcthitrong chngtrnh

Tpcc thanh ghi: L mtmchtuntchatphpcc thanh ghi. Victruyxutc/ghi ln mithanh ghi cthchinbngcch cung cpchsthanhghi (mithanh ghi c mtchsring, cngcxem l achthanh ghi)


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CEXy dngDatapath

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1. Nplnh

Mtphnhnh nhcadatapath, csdngcho qu trnh nplnh v sau tngcon ln 4cacon trPC


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CEXy dngDatapath

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2. Nhm lnh logic v shc(add, sub, AND, OR and slt)

V d: add$t1, $t2, $t3

Hai thnhphncnhinthccc lnh thucnhm logic vshcl tpthanh ghi v ALU


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CEXy dngDatapath

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2. Nhm lnh logic v shc(add, sub, AND, OR and slt)

Mtphnhnh nhcadatapath, baogmqu trnh nplnhv cc lnh trong nhm logic vshc

Nplnhcmt/hai thanh ghi SdngALUGhi dliuvo thanh ghi

Nplnh

cmt/hai thanh ghi

SdngALU


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CEXy dngDatapath

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3. Nhm lnh tham khobnh(lw v sw)

V d: lw$s1, offset_value($t2)

sw$s1, offset_value($t2)

Ngoi register file v ALU, hai thnhphncnthm vo trong datapath khi c nhm lnh tham

khobnhl bnhdliuv khimrngdu(Sign-extend)


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CEXy dngDatapath

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4. Nhm lnh nhy(beq)

Example: beq$t1, $t2, offset

Mtphnhnh nhcadatapath cho lnh beq. Trong , ALU csdngtnh ton iukinnhyv bcng dng tnh achcalnh snhyn.

Nplnhcmt/hai thanh ghi SdngALUChuynnachlnhtiptheo datrn ktquso snh


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CEXy dngDatapath

20Datapath hon chnhcho nhm 8 lnh: add, sub, and, or,slt, lw, sw v beq


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CE Bi tp

Different execution units and blocks of digital logic have

different latencies (time needed to do their work). In Figure4.2 there are seven kinds of major blocks. Latencies of blocks

along the critical (longest-latency) path for an instruction

determine the minimum latency of that instruction. For the

remaining three problems in this exercise, assume thefollowing resource latencies:

What is the critical path for an MIPS AND instruction?

What is the critical path for an MIPS load (LW) instruction?

What is the critical path for an MIPS BEQ instruction?

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CEB X L

Nidung1. Giithiu




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CEHin thcdatapath

24Datapath viydliuinput cho tngkhi

????

1. Inputs cakhiRegisters, Control v Sign-extend


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CEHin thcdatapath

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Trngop (hay opcode) lun chabits t31:26.

Hai thanh ghi dng ctrong ttccc lnh lun lun l rs v rt, tivtr bits t25:21v 20:26.

Thanh ghi nncho lnh load v store lun l rsv tivtr bits 25:21.

16 bits offset cho beq, lwvswth lun tivtr 15:0.

Cc thanh ghi chdng ghi ktquvo hai vtr: Vilw, thanh ghi chtivtrbits t20:16 (r t), trong khi vinhm lnh logic v shc, thanh ghi ch vtr 15:11(rd). V vy, mtmultiplexor cnsdng ylachnthanh ghi no scghi.


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CEHin thcdatapath

26Datapath viydliuinput cho tngkhi


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CEHin thcdatapath

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2. KhiALU Control

????


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CEHin thcdatapath

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BALU caMIPS gm6 chcnngtnh ton datrn 4 bits iukhinuvo:

Ty thucvo tngnhm lnh m ALU sthchin1 trong 5 chcnngu(NOR scdng cho ccphnkhc)

Vicc lnh load wordv store word, ALU sdngchcnngaddtnh ton achcabnh

Vicc lnh thucnhm logic v shc, ALU thchin1 trong 5 chcnng(AND, OR, subtract, add,v set on less than), ty thucvo gi trcatrngfunct (6 bits) trong m my lnh.

Vilnh nhynubng, ALU thchinchcnngsubtractxem iu

khinbngc ngkhng.


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CEHin thcdatapath

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Nhvy, sinh ra 4 bits iukhinALU, mttrong scc cch hinthcc thl s

dngthm mtkhiiukhinALU ControlALU Control nhninput l 6 bits ttrngfunctcam my, ngthidavo 2 bitsALUOp csinh ra tkhiControl sinh ra output l 4 bits iukhinALU, theoquy tcnhbngsau:

Mtgi sinh ra 4 bits iukhinALU davo trngopcode v trngfunct cam my.


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CEHin thcdatapath

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3. Khi iukhinchnh Control

???


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CEHin thcdatapath

32Tc ngcacc tn hiuiukhin

Tn tn hiuiukhin

Tc ngkhi mcthp Tc ngkhi mccao

RegDst Thanh ghi chcho thao tc ghi stthanh ghi rt(bits t20:16)

Thanh ghi chcho thao tc ghi stthanh ghi rd (bits t15:11)

RegWrite KhiRegisters chthchinmichcnngcthanh ghi

Ngoi chcnngc, khiRegister sthchinthm chcnngghi. Thanh ghi cghi l thanh ghi c chscavo tngWrite register v dliudng ghi vo thanh ghi ny clytng Write data

ALUSrc Input thhai cho ALU ntRead

data 2 cakhiRegisters

Input thhai cho ALU ntoutput cakhiSign-extend

Branch Chobitlnhnpvo khngphibeq.Thanh ghi PC nhngi trl PC + 4

Lnhnpvo l lnh beq, kthpviiukinbngthng quacngAND nhmxc nhxem lnh tiptheo c nhynachmihay khng.Nuiukinbngng, PC nhngi trmitktqucabcngAdd

MemRead (Khng) KhiData register thchinchcnngcdliu. achdliucnccavo tng Address v nidung cc

xutra ng Read data

MemWrite (Khng) KhiData register thchinchcnngghi dliu. achdliucnghi cavo tng Address v nidung ghi vo lytng Write data

MemtoReg Gi travo ng Write data ntALU

Gi travo ng Write data ntkhiData memory


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CEHin thcdatapath

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Gi trcc tn hiuiukhintngngvimilnh nhsau:

KhiControl trong datapath nhninput l 6 bits ttrngopcode cam my, davo cc tn hiuiukhincsinh ra tngngnhbng.


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CEHin thcdatapath

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BngsthtkhiControl:

BngsthtkhiControl


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CEHin thcdatapath

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Hin thc b x l n chu k (Single-cycle implementation hay singleclock cycle implementation): l cch hinthcsao chobxl pngthcthi micu lnhchtrong 1 chu kxung clock ihichu kxung clockphibngthigian calnhdi nht.

Cch hinthcbxl nhtrnh by trn l cch hinthcnchu k:

Lnh di nht l lw, gm truy xut vo Instruction memory, Registers, ALU,Datamemoryv quay trliRegisters,trong khi cc lnhkhc khng ihittccc cng ontrn chu kxung clock thitkphibngthigian thcthi lnhlw.

Mcd hinthcbxl nchu kc CPI = 1 nhnghiusutrtkm, v

mtchu kxung clock qu di, cc lnhngnuphithcthi cng thigianvilnhdi nht.V vy, Hinthcnchu khintikhng cn csdng(hocchc thchpnhncho cc tplnhnh)


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CE

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Xem liDatapath vitngnhm lnh

Cc ngmnt l cc nghotngkhi lnh thucnhm logic vshcthcthi

Nplnh

cmt/hai thanh ghi SdngALU

Truy xutbnhc/ghi

dliu


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Nplnh


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CE

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Xem liDatapath vitngnhm lnh

Cc ngmnt l cc nghotngkhi lnh beqthcthi

p

cmt/hai thanh ghi

SdngALU

Chuynnachlnh

tiptheo datrn ktqu

so snh

E i


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CE Exercise

Different instructions require different control signals to be

asserted in the datapath. The remaining problems in thisexercise refer to the following two control signals:

What is the value of these two signals for this instruction?

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CE Exercise

In this exercise we examine how the clock cycle time of the

processor affects the design of the control unit, and vice versa.

Problems in this exercise assume that the logic blocks used toimplement the datapath have the following latencies:

To avoid lengthening the critical path of the datapath shown in

Figure 4.24, how much time can the control unit take to generate

the MemWrite signal?

Which control signal in Figure 4.24 has the most slack and how

much time does the control unit have to generate it if it wants toavoid being on the critical path?

Which control signal in Figure 4.24 is the most critical to

generate quickly and how much time does the control unit have

to generate it if it wants to avoid being on the critical path? 40

E i


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CE Exercise

The remaining problems in this exercise assume that the time

needed by the control unit to generate individual controlsignals is as follows

What is the clock cycle time of the processor?

If you can speed up the generation of control signals, but the

cost of the entire processor increases by $1 for each 5ps

improvement of a single control signal, which control signals

would you speed up and by how much to maximize

performance? What is the cost (per processor) of this

performance improvement?

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CE Exercise

The remaining problems in this exercise assume that the time

needed by the control unit to generate individual controlsignals is as follows

If the processor is already too expensive, instead of paying to

speed it up as we did in 4.10.5, we want to minimize its cost

without further slowing it down. If you can use slower logic to

implement control signals, saving $1 of the processor cost foreach 5ps you add to the latency of a single control signal,

which control signals would you slow down and by how much

to reduce the processors cost without slowing it down?

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E i


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CE Exercise

In this exercise we examine in detail how an instruction is

executed in a single-cycle datapath. Problems in this exerciserefer to a clock cycle in which the processor fetches the

following instruction word:

What are the outputs of the sign-extend and the jump Shiftleft 2 unit (near the top of Figure 4.24) for this instructionword?

What are the values of the ALU control units inputs for thisinstruction?

What is the new PC address after this instruction is executed?

Highlight the path through which this value is determined. 43

KIN TRC MY TNH


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CE

CHNG 4


Phn 1. Xy dngngtruyndliu(Datapath)

Phn 2. Kthutngdn(Pipeline)

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KIN TRC MY TNH

K thut ng dn (pipeline)


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CEKthutngdn(pipeline)

Pipeline l mtkthutm trong cc lnhcthcthi theo kiuchnglplnnhau.

V d minh hahotngnhthno l khng pipelinehay pipeline:

Gi smtphng c nhiungi, mingiucngit qunobncamnh.Qu trnh git quno bao gm4 cng on:

1. t qunobnvo my git git

2. Khi my git hon thnh, aquno tvo my sy3. Khi my syhon thnh, tquno kh ln bn v i4. Khi ihon tt, xpquno vo t

Numtngihon ttttccc cng ongitquno (xong cng oni, xpquno vo t)th ngikhc mibtu(btutquno bnvo my git),

qu trnh thchinny gil khng pipeline. Tuy nhin, r rng rngkhi ngitrchon thnh cng on1, sang cng on2th my gittrng, lc ny ngitiptheo c thaquno bnvo git.Nhvy, ngitiptheo khng cnphichngitrcxong cng onth4 micthbtu, m ngay khi ngitrcncng onth2 th ngitiptheo cthbtucng onthnhtv ctiptcnhvy. Qu trnh thchinchnglp

ny gil pipeline. 45



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Hnh nh4 ngiA, B, C, D git quno theo kiutipcnkhng pipeline (hnh trn) vpipeline (hnh di)



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- Cch tipcndng k thutpipeline tiu tn t thigian hn cho ttccc cng vichon ttbi v cc cng vic c thc hin song song, v vy s cng vichon thnhtrong mtgisnhiuhnso vikhng pipeline.

- Ch , pipeline khng lm gimthigian hon thnh mtcng vicm lm gimthigian hon thnh tngscng vic(nhtrong v dtrn, thigian cho ngiA hon thnhvic git khi p dngpipeline hay khng pipeline u l 2 gi, nhng tng s gi cho 4ngiA, B, C v D hon thnh dng pipeline gimrtnhiuso vikhng pipeline)



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Tng t vic git qun o, thay v mt lnhphi ch lnh trc hon

thnh micthc thi th cc lnhtrong mtchngtrnh cabx l cththcthi theo kiupipeline.

Khi thcthi, cc lnhMIPS cchia lm 5 cng on:

1. Np lnhtbnh

2. Giim lnhv ccc thanh ghi cnthit(MIPS cho php cv giimngthi)

3. Thcthi cc php tnh hoctnh ton ach

4. Truy xutcc ton hngtrongbnh5. Ghi ktqucuivo thanh ghi

V vy, MIPS pipeline trong chngny xem nhc 5 cng on(cn gilpipeline 5 tng)

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An Overview of Pipelining


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CEAn Overview of Pipelining

1.Np lnhtbnh IF2.Giim lnhv ccc thanh ghi ID3.Thcthi EX4. Truy xutbnh MEM5. Ghi ktquvo thanh ghi WB

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- Xt mtbxl vi8 lnhcbn: load word (lw), store word (sw), add (add),

subtract (sub), AND (and), OR (or), set less than (slt), v nhy vi iu kinbng(beq).

- Gisthigian hotngcc cng onnhsau: 200 ps cho truy xutbnh,200 ps cho tnh ton caALU, 100 ps cho thao tc c/ghi thanh ghi

- So snh thigian trung bnh giacc lnhcahinthcnchu kv pipeline.

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V d hnh nh3 lnhlw thchintheo kiukhng pipeline, nchu k(hnh trn) v cpipeline (hnh di)

Thigian gialnhthnhtv thttrong khng pipeline l 3 x 800 = 2400 ps, nhng

trong pipeline l 3 x 200 = 600 ps



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Stngtccapipeline

Trong trnghpl tng: khi m cc cng on pipeline hon tonbngnhau th

thigian giahai lnhlin tipcthcthi trong pipelinebng:

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Nhvy, trong v d trn, thigiangiahai lnhlin tipc pipeline bng160 ps (800:5 = 160)

Trong trnghpl tng, pipeline stngtcso vikhng pipeline vislnngbngstngcapipeline.

Trong thct:Cc cng on thctkhngbngnhau, vicp dngpipelinephichncng on di nhtlm mtchu kpipeline.

V vy, trong v d trn, thigian lin tipgiahai lnhpipeline l 200 ps. V p dngpipeline tngtcgp4 lnso vikhng pipeline.

Speed-up Thigiangiahai lnhlin tipkhng pipeline : Thigiangiahai lnhlin tippipeline800 :200 = 4< 5(number pipeline stages)

Trong thct, pipeline stngtcso vikhng pipeline vislnnhhnstng

capipeline.


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Quy ctrnh by 5 cng on thcthi mtlnhcapipeline:

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Lu cch vhnh cc cng onpipeline nhsau:

Khi t enhon ton hoc trnghon ton: Trong mi cng on pipeline, nulnhthcthi khng lm g trong cng onny sct trng,ngcliscten.

V d lnhadd c EX en v MEM trng tc lnhny c tnh ton trong cngonEX v khng truyxutbnhdliutrong cng onMEM.

Cc cng onlin qua nbnhv thanh ghi c tht natri hocnaphien:Nunaphit en,tccng onangthchinthao tc c; ngclinuna

tri t en,cng onangthchinthao tc ghi.



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Hnh nhdatapath c htrpipeline

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Cc xung tc thxyra khi p dngkthutpipeline (Pipeline Hazards):

Xung tl trngthi m lnhtiptheo khng ththcthi trong chu kpipelinengay sau (hocthcthi nhngscho ra ktqusai), thngdo mttrong banguyn nhn sau:

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Xung tcu trc (Structural hazard): lkhi mt lnhdkinkhng ththcthi trong ngchu kpipeline can dophncngcnkhng thhtr.

Ni cch khc, xung tcutrc xyra khi c hai lnhcng truy xutvo mtti nguynphncngno cng mtlc.

Xung tdliu(Data hazard): l khi mtlnhdkinkhng ththc thitrong ng chu kpipeline can do d lium lnhny cnvnchasn

sng.

Xung t iu khin (Control/Branch hazard): l khi mt lnh d kinkhng th thcthi trong ngchu kpipeline can do lnhnpvo khngphi l lnhccn. Xung tny xy ra trong trnghp lung thc thi

chacc lnhnhy.


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Xung tdliu

V d cho on lnhsau: add $s0, $t0, $t1

sub $t2, $s0, $t3

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Trong v dtrn, nup dngpipeline bnh thngth cng onID calnhsubsthc

hincng lc vicngonEX calnhadd. Trong cng onID, lnhsubscnc

gi trcathanh ghi $s0, trong khi gi trmicathanh ghi $s0phiticng onWB

calnhaddmisnsng. V vy, nuthchinpipeline thng thng, trnghpnysxyra xung tdliu

Mtcch giiquytc thtrong trnghpny l chthm hai chu kxung xung clock

th lnhadd micnpvo

CEK thut ng dn (pipeline)


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Xung tdliu

Thay v chmt schu knkhi d liucnsn sng, mtk thut c thc p

dngrt ngnschu kri, gil kthutnhn trc(forwarding haybypassing).

Nhtrong v dtrc, thay v chsau hai chu kriminplnhadd vo, ngay khiALU hon thnh tnh ton tngcho lnhaddth tngny cngccung cpngay chocng onEX ca lnhsub(thng qua mtbm d liugn thm bn trong) ALU tnh ton ktquchosub nhanh.

Kthutnhn trc: mtphngphp giiquytxung tdliubngathm vo ccbmphbn trong, cc dliucnc thctruy xuttbmny hnl chinkhi n snsng trongbnhhay trong thanh ghi.

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Xung tdliu

Lu, vilnhlwv cc lnhc chcnngtngt, thng thngktqucan khng

phi khi hon ttcng onEX m l khi hon ttcng onMEM.Xt v dsau: lw $s0, 20($t1)

sub $t2, $s0, $t3

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Vilnhlw, dliumong munschsnsng sau 4 chu kpipeline (tcsau khi cng onMEM hon tt). V vy, gisdliuura cacng onMEM calnhlw ctruyntiuvo cng onEX calnhsub theo sau, th lnhsubvnphichsau mtchu krimicnpvo.

Kthutforwarding c thhtrgiiquytxung tdliuhiuqu, tuy nhin n khngthngnchnttccc trnghpchu kri



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Xung tdliu

Tm li, vikthutforwarding c:

ALU-ALU forwarding hayEX-EX forwarding (hnh 1)

MEM-ALU forwarding hayMEM-EX forwarding (hnh 2)

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Hnh 1.

Hnh 2.



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Xung tiukhin

Mtslnhnhyc iukinv khng iukintrong MIPS (branches, jump) tora xung tiukinny

V dxt onchngtrnh sau: add $4, $5, $6

beq $1, $2, label

lw $3, 300($s0)Nup dngpipeline thng thng, tichu kthba capipeline, khi beqangthcthi cng onID th lnhlwscnpvo.Nhngnuiukinbngcalnhbeqxyra th lnhthchiptipsau khngphil lwm l lnhcgnnhn label,lc ny xyra xung tiukhin.

Cc giiphp giiquytxung tiukhin(tham khothm mc4.8, sch thamkhochnh)

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Example


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Example

Hazards?

SW R16,100(R6)

LW R4,8(R16)

ADD R5,R4,R4

SUB R1, R3, R2

Hazards?

OR R1,R2,R3

OR R2,R1,R4

OR R1,R1,R2

chuong04 datapath và pipeline

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