12th MOS-AK ESSDERC/ESSCIRC Workshop

Compact Model of Tunneling Field Effect Transistor for Ultra-low Voltage

Circuit Analysis

Chika Tanaka, Kanna Adachi, Motohiko Fujimatsu, Akira Hokazono, Yoshiyuki Kondo, Daisuke Matsushita,

and Shigeru Kawanaka Advanced LSI Technology Laboratory,

Corporate Research and Development Center, Toshiba Corporation

2/16

Outline

1.  Introduction 2.  TFET model concept 3.  Model evaluation and Circuit simulation results 5.  Summary

Introduction: TFET – device feature and circuit application

3/16

TFET

S-factor [mV/dec] 50 60 80 100

I off [

A/u

m]

1012

1011

1010

109

108

107 Vdd

1V 0.3V

MOSFET

Vgs

Ids

MOSFET

TFET

Fast switching and low power!

Steep S-Slope

Ion/Ioff=106

Ion=10uA/um

Tunneling FET (TFET)

1st issue: performance optimization for various device structure of TFET

4/16

So high tunneling probability and high electron density are needed,

conventional g-FET (Berkeley) SJL-TFET (Toshiba)

Btm.S-TEFT(Toshiba) Simple process Low Ion

The critical device parameters for each TFET are different! High Ion

Low variability

Simple process Low Ion

SSDM2014

SSDM2014

5/16

2nd Issue: For the circuit simulation, Ids under the various Vgs and Vds conditions are needed!

Switching operation for n-type TFET

Vgs=>0  Vs=0  

Gate  Source   Drain  p-­‐type  

i  

Vds>0  

n-­‐type  

Source Channel Drain

Vgs=0  (off)  

Vds=1  Vgs=1(on)  

Reverse bias condition for p-n junction

TFET operation under the various bias conditions

6/16

(a) Vgs>0: BTB tunneling current is dominant.

(1) S-D reverse bias conditions (Vds>=0) (b) Vgs=<0: TFET is in the off state. Ig and Ij should be considered.

(2) S-D forward bias conditions (Vds<0) (c) Vgs>0: p-n diode current is dominant.

(d) Vgs=<0: p-n diode current and Ig should be considered.

Our challenge: Proposal of TFET compact model with simple device parameter which operates every bias conditions

Switching operation

Our concept: “TFET” model is combined with “MOSFET” (BSIM) model

7/16

To simulate the circuit operation of TFET,

S D

G

B

TFET  model

MOSFET  Model  (BSIM4)

TFET(G,  D,  S,  B) Ids: tunneling current p-n diode current

Ig: gate leakage current, Ij: junction leakage current

ü CV characteristic: Calibrated BSIM4 model parameters

8/16

Outline

1.  Introduction 2.  TFET model concept 3.  Model evaluation and Circuit simulation results 5.  Summary

9/16

Tunneling current model

(2) based on a drift-diffusion model under the gradual-channel approximation

𝐽↓BTB = √2𝑚↑∗     𝑞↑3 /4𝜋↑3 ℏ↑2 √𝐸↓𝑔   ∙exp(− 4√2𝑚↑∗     𝐸↓𝑔 ↑3/2   /3𝑞ℏ 𝐸↓𝑡  )∙ 𝐸↓𝑡 ∙ 𝑉↓𝑎𝑝𝑝     ,

𝐸↓𝑡 =  √2𝑞𝑁↓𝑎 (𝑉↓𝑔 + 𝜓↓𝑏𝑖 )/𝜀↓𝑠𝑖   

(1) If Rt is efficiently large, Qchannel ~ Qtunnel.

BTB tunneling current

𝐼↓𝐵𝑇𝐵 /𝑊 =   𝐽↓𝐵𝑇𝐵 ∙ 𝑥↓𝑗 =   𝑄↓𝑡𝑢𝑛 ∙ 𝑣↓𝐵𝑇𝐵 

Qth: the oxide charge for gate-to-source overlap region f1: smoothing function (e.g. 1/(1 + e-x), where x represents the ratio Lg: Lov)

Total charge for the drain current (Q0)

10/16

𝑸↓𝟎 =   𝑸↓𝒕𝒖𝒏 𝒇↓𝟏 +   𝑸↓𝒕𝒉 (𝟏−𝒇↓𝟏 )

𝑄↓𝑡ℎ =     𝜀↓𝑜𝑥 /𝑇↓𝑜𝑥  𝑉↓𝑔 (𝑒↑− (𝑉↓𝑏𝑖 + 𝑉↓𝑔𝑠 + 𝑉↓𝑑𝑠 )∕𝜙↓𝑡   −1)

𝑰↓𝑫 /𝑾 =   𝑸↓𝟎 ∙ 𝒗↓𝒊𝒏𝒋 ∙ 𝑭↓𝒔  The total drain current (ID) is represented using Q0,

“TFET model”: parameter list

11/16

Symbol Unit φbi Built-in potential V Eg Band gap eV T Temperature K L Channel length m W Channel width m Xj Junction depth m

Tox Oxide thickness m Ddibl Drain induced barrier lowering coefficient V/V vinj Injection verocity m/s

Rs/Rd Source/drain resistance W Ntun Substrate concentration of the tunnel junction cm-3

Vth0 Threshold voltage V dtran Transition length of p-n junction m

The advantage of our TFET model: •  simple device parameter ->add various devise structure •  Representation of steep-S slope •  It will be available for every bias conditions.

Our proposed model was implemented in SmartSpice using Verilog-A description.

12/16

Outline

1.  Introduction 2.  TFET model concept 3.  Model evaluation and Circuit simulation results 5.  Summary

Simulation results: IdVg

13/16

GateSource Drain

BoronAs

GateSource Drain

BoronAs

TCAD simulation (in-house) •  The device structure was formed to

demonstrate the steep S.S. of 50mV/decade.

•  The ideal Ion required for the low-power operation.

•  Lg=120nm, Tox=2nm, Ns=1e16 cm-3

SPICE  model  TCAD(Vd=1V)  

0.2 0.4 0.6 0.8 1.0 10-17

Dra

in c

urre

nt (I

d) [A

]

0

10-15

10-13

10-11

10-09

10-07

10-05

SPICE  model  TCAD(Vd=0.2V)  

0.2 0.4 0.6 0.8 1.0 0 10-17

Dra

in c

urre

nt (I

d) [A

]

10-15

10-13

10-11

10-09

10-07

10-05

2D dopant profile for TCAD simulation

Gate voltage (Vg) [V] Gate voltage (Vg) [V]

Simulation results: IdVd

14/16

Drain voltage (Vd) [V]

0.2 0.4 0.6 0.8 1.0

Dra

in c

urre

nt (I

d) [1

0-8 A

]

0

SPICE  model  TCAD  

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

Our model shows a good agreement with TCAD in the targeted operating voltage range.

Circuit simulation results

15/16

Vd=50mV

Vd=1V

IdVg(nTFET) IdVd(nTFET)

diode characteristics

81-stage ring oscillator V(n0) V(n80)

V(n0) V(n80)

Vdd=1.2V

Vdd=0.5V

16/16

Summary Ø Compact model of tunneling field effect

transistor was proposed. – Our ”TFET model” combined with

”MOSFET BIMS4 model” by parallel connection.

– It was available for every bias conditions. – implemented in circuit simulator using Verilog-A description.

Acknowledgement This research was partly supported by JST, CREST in Japan.

our proposed model is useful tool for the circuit-level analysis.