CONG NGHE FPGAI. Gii thieu linh kien logic kha trnh II. Cong nghe lap trnh III. Cau truc FPGA tong quat IV. Cau truc FPGA hang Xilinx V. Cau truc FPGA hang Altera VI. Cau truc FPGA ho Stratix (Altera) VII. Ngon ng mo ta phan cng Verilog va VHDL VIII. Gii thieu mot so kit FPGA IX. Mot so ho FPGA cua cac hang X. Kt lun1

I. LINH KIEN LOGIC KHA TRNHTrc ay phan ln cac loai linh kien ien t la co nh, khong lap trnh c. - Cac loai linh kien logic kha trnh n gian: EPROM, EEPROM, Flash ROM, PLD - e thuan tien cho viec th nghiem, tao mau, phat trien ng ng dung, san xuat quy mo nho, ngi ta a che tao ra cac linh ng kien (thiet b) logic kha trnh (Programmable Logic Devices), tc la cac linh kien so co the c cau hnh lai nhieu lan cho cac ng dung logic khac nhau ng ng - Gom 2 loai chnh: CPLD (Complex Programmable Logic Devices) va FPGA (Field Programmable Gate Array) - Cac hang san xuat FPGA/CPLD: ALTERA, XILINX, ATMEL, QUICKLOGIC, ACTEL,2

FPGA l g?FPGA l mt vi mch cha cc logic cells. Cc logic cells thc hin cc mch logic v c kt ni vi nhau bi ma trn kt ni v chuyn mch lp trnh c. FPGA l tp hp cc phn t ri rc c kt ni theo mt cch chung.

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II. CONG NGHE LAP TRNH A. NGUYEN LY ANTIFUSE:1. Cau truc Antifuse:Antifuse: cau ch nghch Difussion: khuyech tan Lap trnh bang dong ien

Hnh 1: Cau truc Antifuse (hang Actel) (a) Phan giao nhau (b) Hnh ve n gian (c) Antifuse hoat ong nh 1 cong tac 2. u khuyet iem: Kch thc nho

Quy trnh che tao khac vi cong nghe CMOS4

B. NGUYEN LY TE BAO SRAM:1. Cau truc te bao SRAM

Hnh 2: Cau truc te bao SRAM (hang Xilinx) 2. u khuyet iem he thong bang tai cau hnh phan cng trc tiep. Cong nghe CMOS Tai s dung va nang cap thiet ke de dang. Cap nhat va thay oi

D lieu b mat khi nguon cung cap b ngat. Kch thc ln hn antifuse

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C. NGUYEN LY UVEPROM VA EEPROM1. Nguyen ly hoat ong Transistor EPROM

Hnh 3: Cau truc transistor EPROM (hang Xilinx)

2. u khuyet iem Tai lap trnh khong can bo nh ngoai. Dien tch nho Khong tai cau hnh trc tiep tren mach6

III. CAU TRUC FPGA TONG QUAT NG

Cau truc FPGA gom 3 phan: Logic Blocks (LBs), I/O Blocks (IOB), Interconnection

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IV. CAU TRUC FPGA HANG XILINX

Cau truc FPGA hang Xilinx

Cau truc FPGA Spartan II hang Xilinx8

Spartan IIE L mt h linh kin FPGA ca hng Xilinx

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Gm cc khi: CLB: Mt CLB gm 4logic-cell, Logic cell gm 2 LUT ging nhau, mi LUT gm 4-ng-vo, tn hiu iu khin v FF-D. Mi CLB gm hai b iu khin ng ra 3 trng thi (BUFT). Mi BUFT c chn iu khin v ng vo c lp.

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i dy: Cng ngh SRAM, General Routing Matrix (GRM) Local routing: I/O Routing: General Purpose Routing: Dedicated Routing: Global Routing: IOB: tn hiu vo qua 1 b m, tn hiu ra qua b m 3 trng thi, theo cc chun, b nh/giao tip Bus. Mi IOB gm 3 Flip-Flop chia chung 1 tn hiu Clock v cc tn hiu CE (Clock Enable), iu khin c lp cho tng Flip-Flop.

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Khi chc nng RAM Block: gm nhiu khi RAM, t chc thnh hai ct, hai cnh ng ca linh kin.

DLL (Delay Lock Loops): iu khin xung clock, nhm loi tr lch hoc tr hon mt khong thi gian gia tn hiu Clock ng vo v cc xung Clock ng vo bn trong, gim ti a s tr hon, to s ng b v tit kim nng lng. Mi DLL ni hai mng Clock ton cc.12

V. CAU TRUC FPGA HANG ALTERACu trc CPLD MAX7000Cau truc FPGA hang Altera gom: Logic Element / Look up Tables Programmable Interconnect Array I/O Block

Cu trc MAX7000 gm: Logic Array Block Macrocells Programmable Interconnect Array I/O control blocks13

MAX 7000 (t.t)Cu trc Logic Array Block

Mt LAB bao gm 16 Macrocells. Cc LAB c ni vi nhau qua ng kt ni chung lp trnh c Programmable Interconnect Array (PIA), cc ng ny s ni cc macrocells v chn I/O. 36 tn hiu ng vo Macrocells

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MAX 7000 (t.t)Cu trc Macrocells Cu trc I/O

1 Macrocell bao gm 3 khi chc nng: Mng logic, ma trn chn thnh phn tch (Product Term Select Matrix) v thanh ghi lp trnh c (Programmable Register) Thc hin chc nng mch t hp hoc mch tun t Parallel Logic Expanders cho php ni cc macrocell li vi nhau to thnh chc nng logic ln hn v Sharable Logic Expanders m rng thnh phn tch

Khi I/O: Cc chn I/O c th cu hnh l ng vo, ng ra, 2 chiu 15 Cc chn I/O m 3 trng thi

Cu trc Flex10K FLEX10K bao gm cc EAB (Embedded Array Block). Mi EAB gm c 2048 bit, c th to RAM, FOM, FIFO hoc cc chc nng logic tng qut. Mi EAB gm 100-600 cng, c th dng c lp hoc kt hp li vi nhau. Cc EAB khi l RAM c th l 256x8, 512x4, 1024x2, 2048x1. Cc mng Logic bao gm cc LAB, mi LAB gm 8 LE v mt ng kt ni cc b. Mi LE gm 1 LUT (Look-up Table) 4 ng vo, 1 FlipFlop lp trnh c v cc ng dnh ghp ni. Cc Interconnection theo hng v ct, ni cc LAB vi nhau Cc IOE (I/O Element) cha cc I/O pin. Mi IOE gm 1 b m 2 chiu v 1 FlipFlop c th l ng vo/ra/2 chiu, hoc thanh ghi vo/ra. ng dng ca cc EAB l to b nh, cc b vi x l, vi iu khin, lc s,

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Cau truc CPLD ho Flex10K

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Cau truc CPLD ho Flex10K (tt)Cu trc Logic array block Cu trc LE

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V. CAU TRUC FPGA HANG ALTERACau truc FPGA hang Altera gom: Logic Element / Look up Tables Programmable Interconnect Array I/O Block

Cau truc CPLD ho Flex10K

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VI. CAU TRUC FPGA HO STRATIX 1. CAU TRUC HO STRATIX:- Gom cac LAB, Interconnection, cac khoi bo nh va cac khoi DSP - Cau truc 2 chieu : hang va cot, dung cong nghe ket noi MultiTrack - Cac chuoi ket noi hang va cot ket noi cac LABs, khoi bo nh, IOE va DSP - Mang logic bao gom cac LAB, moi LAB gom 10 LEs (LE la 1 n v logic nho nham thc hien hieu qua nhng ham logic). Cac LAB c nhom trong cac hang va cot xuyen suot trong linh kien. - Cac khoi bo nh gom M512 RAM, M4K RAM, M-RAM thc hien RAM, ROM, FIFO, - Cac chan I/O ( IOE) at cuoi hang va cot cua LAB. Moi IOE gom 1 bo em 2 chieu, 6 thanh ghi cho cac ngo vao/ra thanh ghi va ieu khien - Cac khoi DSP - Khoi PLLs.20

Cau truc FPGA ho Stratix (hang Altera)

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Cau truc LAB ho Stratix (hang Altera)

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Cau truc LUT ho Stratix (hang Altera)

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2. TAI NGUYEN KET NOI HO STRATIX:- Ket noi gia cac LE, bo nh, DSP va chan I/O - Ket noi hang gom: + Ket noi trc tiep gia cac LAB va cac khoi ke can + Ket noi R4, Ket noi R8, Ket noi hang R24 xuyen suot chieu dai linh kien - Ket noi cot gom: + Ket noi chuoi LUT va chuoi thanh ghi trong LAB + Ket noi C4, Ket noi C8, Ket noi cot C16 xuyen suot chieu doc linh kien - Ket noi hang ket noi vi ket noi cot.

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Cau truc IOE ho Stratix (hang Altera)25

3. CAC KHOI CHC NANG HO STRATIX:1. Khoi bo nh: + RAM 2-port n gian, RAM 1 port, FIFO, ROM, thanh ghi dch. Khoi bo nh gom 3 khoi RAM: M512, M4K, M-RAM 2. Khoi PLLs: (Phase Lock Loop) + Cau truc phan cap xung Clock + Ket hp cac nguon tai nguyen xung Clock vi tong hp tan so chnh xac c cung cap bi cac PLL nhanh va tien tien tao thanh giai phap quan ly xung Clock hoan chnh 3. Khoi DSP: (Digital Signal Processing) + Dung trong loc FIR, loc FIR phc tap, loc IIR, FFT, bien oi Cosin ri rac, tng quan + Khoi DSP gom cac thanh phan sau: o Khoi nhan o Khoi cong/ngo ra

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Cau truc khoi bo nh ho Stratix (hang Altera)

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Cau truc MAC - DSP ho Stratix (hang Altera)

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Cau truc PLLs ho Stratix (hang Altera)

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VII. NGON NG MO TA PHAN CNG VERILOG HDL VA VHDL+ Co rat nhieu ngon ng mo ta phan cng c phat trien nham muc ch mo phong, tao mau, thiet ke, kiem tra va lam tai lieu cho cac he thong so. + Tuy nhien ngay nay co hai ngon ng c s dung rat pho bien, o la : Verilog HDL va VHDL. + VHDL (Very High Speed Integrated Circuits Hardware Description Language) la ngon ng mo ta phan cng c cong nhan tieu chuan IEEE t nam 1987. No la ngon ng co ay u sc manh cho viec thiet ke va mo ta cac he thong so ngay nay. Tuy nhien VHDL rat giong vi ngon ng Ada, mot ngon ng khong pho bien. ac iem nay lam cho VHDL kho hoc hn. + Verilog HDL c chuan hoa t nam 1995 va rat giong ngon ng C. Chnh ac iem nay ma no c s dung kha rong rai ngay nay. Tai Viet Nam, cong ty Renesas cung s dung ngon ng nay trong viec thiet ke.30

VIII. GII THIEU MOT SO KIT FPGAKit Stratix EP1S25 (Altera) cua hang Parallax + 144 chan I/O + Bo dao ong xung clock 50MHz + Nguon 3.3V cho I/O va 1.5V cho loi FPGA + Cong noi tiep chuan 9 chan + Cac chan noi JTAG

www.parallax.com31

Kit UP2 cua Altera + Chip EPM7128S ho Max7000 + Chip EPF10K70 ho FLEX10K + Ho tr 2 led 7 oan + 16 led + JTAG chain, cap tai ByteBlaster II + Cong giao tiep P/S2, VGA + Bo tao dao ong 25.17 MHzNgoai ra con co Kit UP3 (Altera)

www.altera.com

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Kit Digilab 2E cua Digilent + Spartan 2E XC2S200E cua Xilinx + 143 chan I/O ngi dung + Nguon ieu chnh 1,5A (2,5 va 3,3V) + Bo dao ong 50MHz + Cong JTAG + Cong RS-232 + Mot led va mot nut bam www.digilentinc.com

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Virtex-4 ML401 Development Board

Linh kien: XC4VLX25-FF668-10C Tan so: 100 MHz Oscillator Bo nh: 64 MB DDR SDRAM, 8Mb ZBT SRAM, 64 Mb Flash, 4 kb I2C EEPROM Hien th: 16x2 Character LCD Cac giao tiep: 4 SMA (Differential Clocks), 2 PS/2 (Keyboard/Mouse), 4 Audio Jacks (Line In/Out, Microphone, Head Phone), RS-232 Serial Port, 3 USB Ports, JTAG, VGA

www.nuhorizons.com

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PHAN MEM S DUNG TRONG THIET KE FPGAXilinx: Xilinx ISE Foundation 7.1 http://www.xilinx.com Altera: Maxplus II, Quartus II (Tai lieu s dung ng Maxplus II a c ang trong phan tin CMS Dien an ien t), www.altera.com ), Cac phan mem ho tr FPGA khong phu thuoc hang san xuat nh FPGA Advantage (Mentor Graphics): Leonardo Spectrum, ModelSim, Matlab, Labview, www.mentor.com

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Chng trnh Quartus II

Chc nang:Soan thao thiet ke: Verilog HDL, VHDL, AHDL; Graphic Mode Bien dch Tong hp Toi u hoa Phan tch nh thi Mo phong dang song Nap chng trnh

Giao dien cua chng trnh Quartus II

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XI. MOT SO HO FPGA CUA CAC HANG+ Altera : gom cac ho Max3000, Max7000, MAXII, Flex10K, Cyclone, APEX, ACEX, Mercury, Stratix, Stratix GX, Stratix II (co the tham khao tai www.altera.com). + Xilinx : XC3000, XC4000, XC9500, Spartan, Spartan2, Spartan3, Qpro Virtex, Virtex, VirtexII (co the tham khao tai www.xilinx.com). + QuickLogic : Eclipse, EclipsePlus, QuickRam, pASIC1, pASIC2, pASIC3 (co the tham khao tai www.quicklogic.com). + Atmel : AT6000, AT40K (co the tham khao tai www.atmel.com).

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X. KT LUN1. NG DNG+ Thiet ke mach logic so hien ai theo nhu cau cua ngi thiet ke + Tao mau trc khi che tao vi mach + Thiet ke cac bo vi x ly, vi ieu khien + X ly tn hieu so + X ly anh so, Video + X ly am thanh + Trong truyen thong: cac chuan Ethernet, ma Turbo, ma Viterbi, Reed Solomon, + Cac giao tiep PCI, USB + ieu khien t ong + Va cac ng dung khac 38

2. QUY TRNH THIET KE FPGANgo vao thiet ke (Schematics, Verilog, VHDL) Mo phong hanh vi Tong hp thiet ke Thc hien thiet ke (FPGA Place and Route)

Mo phong

Cau hnh FPGA (Tai thiet ke xuong FPGA)

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Ngoai ra con co the thiet ke tren FPGA, ket hp phan mem cua hang san xuat va phan mem Labviewu iem:S dung cac th vien san co Trc quan va de s dung Rut ngan thi gian thiet ke n gian hoa quy trnh thiet ke

S o thiet ke FPGA s dung phan mem Labview cua hang National Instrumetns

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Thiet ke tren FPGA, ket hp phan mem cua hang san xuat vi phan mem Matlab

S o thiet ke FPGA ket hp phan mem Quartus II cua hang Altera va Matlab cua Mathworks

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3. U VA KHUYET IEM FPGAu iem : + Thi gian thc hien thiet ke nhanh + Co the thay oi thiet ke de dang + Chi ph thap Khuyet iem : + Toc o cham + Ch hieu qua trong cac mach logic so + Khong the thay the cac linh kien ASIC Tuy nhien ngay nay khuyet iem nay ang c khac phuc nh s tien bo cua cong nghe. Do o FPGA ngay cang c s dung pho bien va rong rai trong moi lnh vc cua i song.42

So snh FPGA v CPLDFPGA Khi Logic Logic cell nm ngoi, chia chung ngun ti nguyn Phc tp SRAM LUT Va v ln CPLD Logic cell nm gia cc ngun ti nguyn n gin hn EPROM, EEPROM Mng AND-OR, PAL-like Nh43

Kt ni Cng ngh lp trnh Cu trc logic ng dng

Field-Programmable Device (FPD) a general term that refers to any type of integrated circuit used for implementing digital hardware, where the chip can be configured by the end user to realize different designs. Programming of such a device often involves placing the chip into a special programming unit, but some chips can also be configured in-system. Another name for FPDs is programmable logic devices (PLDs); although PLDs encompass the same types of chips as FPDs, we prefer the term FPD because historically the word PLD has referred to relatively simple types of devices. SPLD refers to any type of Simple PLD, usually either a PLA or PAL CPLD a more Complex PLD that consists of an arrangement of multiple SPLD-like blocks on a single chip. Alternative names (that will not be used in this paper) sometimes adopted for this style of chip are Enhanced PLD (EPLD), Super PAL, Mega PAL, and others. FPGA a Field-Programmable Gate Array is an FPD featuring a general structure that allows very high logic capacity. Whereas CPLDs feature logic resources with a wide number of inputs (AND planes), FPGAs offer more narrow logic resources. FPGAs also offer a higher ratio of flip-flops to logic resources than do CPLDs.

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LI CAM NXin chan thanh cam n cac ban a en tham d lp hoc nay. Rat mong nhan c cac y kien ong gop cua cac ban.

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