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Multiple Choice

1 . The output of a NOT gate is HIGH when

the input is LOW

the input is HIGH

power is applied to the gate's IC

power is removed from the gate's IC

2 . The output of an AND gate with three inputs, A,B, and C, is HIGH when

A = 1,B = 1, C= 0

A = 0,B = 0, C= 0

A = 1, B = 1, C= 1

A = 1, B = 0, C= 1

3 . The output of an OR gate with three inputs, A, B, and C, is LOW when

A = 0,B = 0, C= 0

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A = 0,B = 0, C= 1

A = 0,B = 1, C= 1

all of the above

4 . For a NOT gate, the input isA and the output isX. Then

X=A

X=

X= 0

none of the above

5 . With regard to an AND gate, which statement is true?

An AND gate has two inputs and one output.

An AND gate has two or more inputs and two outputs.

If one input to a two-input AND gate is HIGH, the output

reflects the other input.

A two-input AND gate has eight input possibilities.

6 . If a three-input AND gate has eight input possibilities, how many of

those possibilities will result in a HIGH output?

1

2

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7

8

7 . The Boolean expression for a three-input AND gate is

X=AB

X=ABC

X=A + B + C

X=AB + C

8 . If a three-input OR gate has eight input possibilities, how many of those

possibilities will result in a HIGH output?

1

2

7

8

9 . The Boolean expression for a three-input OR gate is

X=A + B

X=A + B + C

X=ABC

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X=A + BC

10

.

A NAND gate's output is LOW if

all inputs are LOW

all inputs are HIGH

any input is LOW

any input is HIGH

11

.

A NOR gate's output is HIGH if

all inputs are HIGH

any input is HIGH

any input is LOW

all inputs are LOW

12

.

If a three-input NOR gate has eight input possibilities, how many of

those possibilities will result in a HIGH output?

1

2

7

8

13 A two-input NOR gate is equivalent to a

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. negative-OR gate

negative-AND gate

negative-NAND gate

none of the above

14

.

The logic expression for a NOR gate is

X=A + B

15

.

The exclusive-OR gate's output is HIGH if

all inputs are LOW

all inputs are HIGH

the inputs are different

none of the above

16

.

The exclusive-NOR gate's output is HIGH if

the inputs are the same

one input is HIGH, and the other input is LOW

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the inputs are different

none of the above

17

.

The switching speed of CMOS is now

competitive with TTL

three times that of TTL

slower than TTL

twice that of TTL

18

.

The basic types of programmable arrays are made up of

AND gates

OR gates

NAND and NOR gates

AND gates and OR gates

19

.

One advantage TTL has over CMOS is that TTL is

less expensive

not sensitive to electrostatic discharge

faster

more widely available

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20

.

TTL operates from a

9-volt supply

3-volt supply

12-volt supply

5-volt supply

21

.

A CMOS IC operating from a 3-volt supply will consume

less power than a TTL IC

more power than a TTL IC

the same power as a TTL IC

no power at all

22.

CMOS IC packages are available in

DIP configuration

SOIC configuration

DIP and SOIC configurations

neither DIP nor SOIC configurations

23

.

The terms low speedand high speed, applied to logic circuits, refer to the

rise time

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fall time

propagation delay time

clock speed

24

.

The power dissipation, PD, of a logic gate is the product of the

dc supply voltage and the peak current

dc supply voltage and the average supply current

ac supply voltage and the peak current

ac supply voltage and the average supply current

25

.

Fan-out is specified in terms of

voltage

current

wattage

unit loads

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Boolean Algebra and Logic Simplification

Multiple Choice

1 .Determine the values ofA, B, C, and Dthat make the sum term equal to zero.

A = 1, B = 0, C= 0, D = 0

A = 1, B = 0, C= 1, D = 0

A = 0, B = 1, C= 0, D = 0

A = 1, B = 0, C= 1, D = 1

2 . Determine the values ofA, B, C, and Dthat make the product term equal to 1.

A = 0, B = 1, C= 0, D = 1

A = 0, B = 0, C= 0, D = 1

A = 1, B = 1, C= 1, D = 1

A = 0, B = 0, C= 1, D = 0

3 . Applying the distributive law to the expression , we get

AB + AC + AD

ABCD

A + B + C + D

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4 . Applying DeMorgan's theorem to the expression , we get

A(B + C)

5 . Applying DeMorgan's theorem to the expression , we get

6 . Applying DeMorgan's theorem to the expression , we get

7 . Applying DeMorgan's theorem to the expression , we get

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(X + Y)Z

8 . Derive the Boolean expression for the logic circuit shown below:

CA + CB + CD

C(A + B) + D

CA + CB + D

9 . Derive the Boolean expression for the logic circuit shown below:

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C(A + B)DE

[C(A + B)D + E]

[[C(A + B)]D]E

ABCDE

10

.

How many gates would be required to implement the following Boolean expression

before simplification? XY + X(X + Z) + Y(X + Z)

1

2

4

5

11

.

Referring to Question 10, how many gates would be required to implement the Boolean

expression after simplification?

1

2

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4

5

12

.

The expression W(X + YZ) can be converted to SOP form by applying which law?

associative law

commutative law

distributive law

none of the above

13

.

Converting the Boolean expression LM + M(NO + PQ) to SOP form, we get

LM + MNOPQ

L + MNO + MPQ

LM + M + NO + MPQ

LM + MNO + MPQ

14

.

The binary values for the standard SOP expression, , when equal to

1 are

1110 + 0110 + 0001

0001 + 1001 + 1110

1111 + 1111 + 1111

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0000 + 0000 + 0000

15

.

Determine the binary values of the variables for which the following standard POS

expression is equal to 0.

(0 + 1 + 0)(1 + 0 + 1)

(1 + 1 + 1)(0 + 0 + 0)

(0 + 0 + 0)(1 + 0 + 1)

(1 + 1 + 0)(1 + 0 + 0)

16

.

Convert the following SOP expression to an equivalent POS expression.

17

.

A truth table for the SOP expression, , has how many input

combinations?

1

2

4

8

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18

.

For the SOP expression below, how many 1s are in the truth table's output column?

1

2

3

5

19.

The truth table for the SOP expression, , has how many input combinations?

1

2

4

8

20

.

For the SOP expression below, how many 0s are in the truth table's output column?

zero

1

4

5

21 From the truth table below, determine the standard SOP expression.

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.

X=ABC+ABC+ABC

22

.

From the truth table below, determine the standard POS expression.

23

.

Mapping the following SOP expressions, , we get

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24

.

Mapping the following standard SOP expression, , we get

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25

.

Referring to the PAL diagram, which is the correct logic function?

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Multiple Choice

1 . A 4-variable AND-OR circuit produces a 1 at its Y output. Whichcombination of inputs is correct?

A = 0, B = 0, C= 0, D = 0

A = 0, B = 1, C= 1, D = 0

A = 1, B = 1, C= 0, D = 0

A = 1, B = 0, C= 0, D = 0

2 . A 4-variable AND-OR circuit produces a 0 at its Y output. Whichcombination of inputs is correct?

A = 0, B = 0, C= 1, D = 1

A = 1, B = 1, C= 0, D = 0

A = 1, B = 1, C= 1, D = 1

A = 1, B = 0, C= 1, D = 0

3 . A 4-variable AND-OR-Invert circuit produces a 1 at its Y output. Whichcombination of inputs is correct?

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AB + CD

4 . A 4-variable AND-OR-Invert circuit produces a 0 at its Y output. Whichcombination of inputs is correct?

none of the above

5 . An exclusive-OR gate's Youtput is 1. Which input combination iscorrect?

10111100

10111000

11100111

11111000

6 . An exclusive-NOR gate's output is 1. Which input combination iscorrect?

A = 1, B = 0

A = 0, B = 1

A = 0, B = 0

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none of the above

7 . Before a SOP implementation, the expression would

require a total of how many gates?

1

2

4

5

8 . How many NOT gates are required to implement the Booleanexpression, ?

1

2

4

5

9 . The Boolean SOP expression obtained from the truth table below is

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10

.

How many AND gates are required to implement the Boolean

expression, ?

1

2

3

4

11

.

Implementation of the Boolean expression results in

three AND gates, one OR gate

three AND gates, one NOT gate, one OR gate

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three AND gates, one NOT gate, three OR gates

three AND gates, three OR gates

12

.

How many two-input NOR gates does it take to produce a two-input

NAND gate?

1

2

3

4

13

.

Implementing the expression AB + CDEusing NAND logic, we get:

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14

.

Implementing the expression using NAND logic, we get

15

.

Implementing the expression using NAND logic, we get:

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16

.

Implementing the expression with NOR logic, we get:

17

.

A logic circuit with an output consists of

two AND gates, two OR gates, two inverters

three AND gates, two OR gates, one inverter

two AND gates, one OR gate, two inverters

two AND gates, one OR gate

18

.

To implement the expression , it takes one OR gate

and

three AND gates and three inverters

three AND gates and four inverters

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three AND gates

on AND gate

19

.

The output expression for an AND-OR-Invert circuit having one AND

gate with inputs A, B, and C and one AND gate with inputs Dand Eis

20

.

The inverter can be produced with how many NAND gates?

1

2

3

4

21

.

One positive pulse with tW = 75 s is applied to one of the inputs of an

exclusive-OR circuit. A second positive pulse with tW = 15 s is applied

to the other input beginning 20 s after the leading edge of the first

pulse. Which statement describes the output in relation to the inputs?

The exclusive-OR output is a 20 s pulse followed by a 40 s pulse, with

a separation of 15 s between the pulses.

The exclusive-OR output is a 20 s pulse followed by a 15 s pulse, with

a separation of 40 s between the pulses.

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The exclusive-OR output is a 15 s pulse followed by a 40 s pulse.

The exclusive-OR output is a 20 s pulse followed by a 15 s pulse,

followed by a 40 s pulse.

22

.

Referring to the GAL diagram, which is the correct logic function?

23 Which waveform pattern is correct for a two-input OR gate?

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.

24

.

Which waveform pattern is correct for a two-input AND gate?

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25

.

Which waveform pattern is correct for an exclusive-OR gate?

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