積分器とsaradcを用いた1ps分解能の時間・デジタル変換器 · 2013. 3. 12. · t...

Matsuzawa& Okada Lab.

Matsuzawa Lab.Tokyo Institute of Technology



積分器とSARADCを用いた1ps分解能の時間・デジタル変換器

Ο徐祖楽、宮原正也、松澤昭

東京工業大学理工学研究科・電子物理工学専攻

松澤・岡田研究室

学生17





2 Abstract

• We propose a time-to-digital converter (TDC) that uses a

Gm-C integrator to translate the time interval into voltage,

and quantizes this voltage with a SAR-ADC. The proposed

method is capable of achieving pico-second resolution,

avoiding limitations in delay-chain-based TDCs, such as

logic gate propagation delay, mismatches, and voltage

surges. Furthermore, taking the advantages of SAR-ADC,

small area and low power consumption of voltage

quantization are attainable. The chip was fabricated in

90nm CMOS. Its measured DNL and INL are -0.6/0.7 LSB

and -1.1/2.3 LSB, respectively, with 1ps per LSB in a 9-bit

range.





3 Outline

• Motivation and Previous Solutions

• Integrator-Based Time-to-Digital Converter

• Circuits Design

– Level Shifter

– Gm-C Integrator

– SAR-ADC

• Implementation and Measurement

• Conclusion





4 Motivation

• Pico second time resolution is challenging

• Delay-chain TDC does not serve for it

• Systems that demand

pico second resolution

• ToF imaging

• Laser range finder

• Digital PLL, etc.

CK1

CK2

D[1] D[n-1] D[n]

...

...

td td td td

td = 20ps in 90nm CMOS





5 Previous Solutions

• Vernier TDC typically uses a DLL

against PVT but consumes extra power

• Mismatch among stages still exists

CK1

CK2

D[1] D[2] D[n-1] D[n]

td1 td1 td1 td1

td2 td2 td2 td2

(td1 – td2) varies on each stage by PVT






• Time amplifiers (TA) suffer nonlinearity

and mismatch

• Too many calibrations are required

Delay chain

TA array

CK1

CK2

DOUT

Delay chain

MUX Logic

Coarse - fine

1.5b

MDAC

(w/ TA)

CK1

CK2

1.5b

MDAC

Digital correction

...

DOUT

Pipeline

[M.Lee, JSSC 08]

[Y.H.Seo, VLSI 11]






• Stochastic TDC suffers short range

• Delta-sigma TDC’s input bandwidth is low

N arbiters w/ mismatches

CK1

CK2

Dout

Σ td

DTC

Time

Quantizer

CK1

CK2

Dout

Stochastic Delta-Sigma

[V.Kratyuk, TCAS-I 09] [J.P.Hong, ISSCC 12]





8 Integrator-Based TDC

• Integral is proportional to time

• No limitation of logic gate delay

• Few calibrations are required

VP-VN

td

Vi

VP

VN

Integral

equivalent

VOP

VON

Vi

do tV

VP

VN

1

s ADCDout






• Solutions in old days…

• Large capacitance and ADC pose

resolution, density and power issues

ADCCK

RST

Dout

On-chip Off-chip

CK

RST

DoutCounter

SYS_CK

One chip solution

· Still large capacitance

· Low bandwidth

ICVt /

[E.R.Ruotsalainen, JSSC 00]






• Proposal: use MoM capacitors and

SAR-ADC

0

1

2

3

4

5

0 10 20 30 40 50 60 70 80

BD

Sampling freq. (MHz)

Po

wer

dis

sip

ati

on

(m

W)

VDD=1.2V

VDD=1.0V

Pd vs. fs

0.5

0.6

0.7

0.8

0.9

1

2

3

50 60 70 80 90 100 200

MOM

MIM

Design rule (nm)

De

ns

ity (

fF/u

m2)

MoM: better density

SAR-ADC: low and

dynamic power






• When capacitors become small

charge injection, charge sharing, and

clock feed-through can be worse

• Solution: fully-differential Gm-C

CK

RST

· Small capacitor

more error

from the switch

Gm

· Differential and no switch

controlled integration

Vi Vo i

o

GmV

CVt





12 Architecture

• Level shifter interfaces digital and analog

• OTA enhances Gm’s output resistance

GmCK2

CK1

C

Level

shifter

SAR

ADC

DelayConv. start

C

OTADOUT

CK2

CK1

IP

IN

Vi Vo





13 Level Shifter

• Level shifting during rising of CK1 and CK2

• Larger amplitude (Vi) finer resolution but

poorer linearity

C1

C2

CK1

CK2C1

C2

Vinit

VP

VN

VDD

VDD

DDi VCC

CV

21

1

No static

current

CK1

CK2

VP

VN

Vi

Vinit





14 Gm-C Integrator

• Source degeneration and neutralization

capacitor

Switched-

cap. CMFB

VNVP

Cc

VBP

A2

A1

VOP1VON1

VCP

VOP1 VON1

VON VOP

Rs

To increase linearity

To balance kickback

and input feed-through





15 SAR-ADC

• ENOB = 9.8-bit

• 1mW@10MHz, 0.15mm2

...

...

Cs4C 8C 1C 2C 64C2C

VREFNVREFP

VCM

VON

VREFNVREFP

VCM

VOPL

og

ic

4C2C1C1/2C1/4C

Pa

ras

itic

co

mp

en

sa

tio

n c

od

e

10

Dout

1C

CLK CLK

Vip Vin

Latch

SAR-ADC (12-bit topology) Dynamic comparator





16 Implementation

• CMOS 90nm, 0.31mm2

• Area of SAR-ADC can be reduced to 1/8

if a 10-bit topology is designed

SG1

SG2

TEGLogic

Analyzer

10MHz

10MHz + 40Hz

Measurement setup





17 Measurement

• 1ps LSB was obtained without calibrations

• Power can be reduced by improving the

integrator

0 64 128 192 256 320 384 448 512-1

-0.5

0

0.5

1

Code

DN

L [

LS

B]

0 64 128 192 256 320 384 448 512

-2

-1

0

1

2

Code

INL [

LS

B]

TNS’07 VLSI’11 ESSCIRC’10 This work

Type Vernier Pipeline Stochastic Integrator

CMOS [nm] 130 130 65 90

Supply [V] 3.3 1.3 1.2 1.2

Resolution [ps] 37.5 0.63 3 1

Range [ps] 2000 1300 52 ±256

DNL [LSB] 0.2 0.5 1.4 -0.6/0.7

INL [LSB] 0.35 2 1.5 -1.1/2.3

Area [mm2] 0.22 0.32 0.04 0.31

Frequency [MS/s] 0.1 65 40 10

Power [mW] 150 10.5 8 20.4

Performance comparison DNL/INL





18 Conclusion

• Voltage domain is still more resolvable

for high resolution TDC

• SAR-ADC is a promising solution to

integrator-based TDC

• Few calibrations are required

comparing with time-domain solutions

• Power and area will be improved

積分器とsaradcを用いた1ps分解能の 時間・デジタル変換器 · 2013. 3. 12. · t...

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積分器とsaradcを用いた1ps分解能の時間・デジタル変換器 · 2013. 3. 12. · t...