ddv ppt cha1
TRANSCRIPT
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Introduction to
Verilog
ECE DepartmentGVP College of Engg
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Verilog as an HDL First developed by Gateway Design Automation in 1983
Became IEEE standard in 1995
The Standard is called IEEE Std 1364-1995
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Verilog as an HDL Used for Design
Also used for verifying design for
1. Functionality
2. Timing Contstraints like propagation delay,critical path delay etc
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Levels of Design Description
Switch is the basic element used in digital circuit building
Verilog is having inbuilt constructs for it
Circuit Level
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Levels of Design Description
It is next higher level of abstraction in which design is carried out in
terms of basic gates All the gates are readily available as Premitives
It is good to build in digital circuit in Bread Board or on a PCB.
Gate Level
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Levels of Design Description
It is next higher level of abstraction.
Signals and variables are represented in terms of assignments. Data manipulated equations.
Ex A-O-I Relationship
Data Flow
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Levels of Design Description
It is the highest level of Design description
Essentially looks like C Code With assignment looping , Branching is possible.
Behavioral Level
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Simulation and Synthesis
Desing is simulated for functionality and fully debugged
Translation of debugged design into the hardware ckt (FPGS orASIC) is called synthesis.
Translation in synthesis is from Behavioural to gate or data flowlevels.
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Functional Verification
Testing is essintial
Functional test and timing test. Test Bench , test signals.
Inputs for testing.
Outputs for analysis.
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Functional Verification
Carryout all the expected activates for design shouldn't malfunctionunder any set of input conditions.
Purely combinational,periodic,numeric sequence, random inputs,conditional inputs or combination of these.
Module verification.
Top level verification.
Test inputs for test benches
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Functional Verification
Gate Delay Net Delay
Path Delay
Pin to Pin Delay.
Setup, hold and clock width time specifications.
Simulate realistic conditions in digital ckt.
With this testing one can estimate the minimum Freq ofoperation,Max speed of responce.
Constructs for modelling timing delays
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System Tasks Facilitate control and flow of testing process.
Functions that keep track of the progress of simulation time
to display. To generate Random numbers
And So on.
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Programming Language
Interface. Interface to a compiled verilog module
Can read the data from a file and pass it to a verilog module as input
Blocks written in C language can be linked to verilog modules. Delay values or logic values etc can be accessed and altered.
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Module Program begins with Keyword called Module
Input ports
Output ports Inout ports
Possible tokens are
White spaces
Commnets
Operaters
Numbers
Strings
Identifiers keywords
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SIMULATION AND
SYNTHESISSIMULATION
MODELSIM -- Mentor Graphics
VCS -- Synopsys
NCVERILOG CadenceSYNTHESIS FPGA VENDORS
XILINX
ALTERA
ACTEL
CYPRESS
LATTICE
QuickLogic etc
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TEST BENCHES Check ensure that all functions are carried out as desired
Logical inputs are applied and logic values at another point areobserved
Ensure all the functional sequences are carried out as desired Checking for timing behaviour
Example : - followed here.
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LANGUAGE CONSTRUCTS AND
CONVENTIONS IEEE standard constructs and conventions
Resembles C language
Case sensitive language like C.
sense,Sense,SENSE,sENse are all different.
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KEYWORDS Programmer can not change meaning of keyword
All keywords in verilog are in small letters
Example : - module
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Identifiers Any program requires block of statements ,signals ..etc to be
identified with an name tag
Examples:
Clock, Enable,gate_1
Rules:
All characters of the alphabet or an underscore ( _ ) can be used asfirst character
Subsequent characters can be of alpha numeric type or _ or $ signExamples:
name_name,Name,name1,name_$ are valid
name aa ,$name,1_name,@name A+b are invalid
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Escape Identifiers Start with \ character
Character set between first \ character and first white spacecharacter is treated as an identifier.
Example:\b=c
\abc
\control-signal
\&logic
These are not encouraged in coding for confusion.
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Comments Single line comment //
// clock generator
Multi line comment /* .....*/
/* usage of state machine is to control power ,reset sequence, andprocess start and end operations */
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NumbersInteger numbers
2,25,253,-253 are valid
2a,B8,-2a,-B8 are invalid
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Numbers
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Numbers
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Real Numbers. Real numbers can be specified as decimal or scientific notation.
Ex:
a.b
4.3e2
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STRINGS. String is sequence of characters within double quotes.
Must be contained on a single line cannot be carried over.
Examples:
This is a stringThis string lin line 1 \n and this string is in line 2
x = numb
assigns binary value 0110 1110 0111 0101 0110 1101 0110 0010
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Logical Values. 1
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Strengths A logic state can have strength associated with it
It represents internal impedance value of corresponding hardwareckt.
In many digital ckts multiple assignments are often combined. tofacilitate this one can assign strength to logic levels
Verilog has 8 strength levels.
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Strengths
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DataTypes
Net data type : signifies connection from one ckt to another
Example : wire,tri
Variable data type : abstraction for storage device
stores logic 1,0,x,zExample : reg
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Scalars and Vectors
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Parameters
In some designs certain values are fixed. All such constants aredeclared as Parameters.
Example :
parameter word_size = 16;parameter mem_size = 256;
The parameter values cannot be changed (normally)at runtime.
There is a way to change this parameter with module instantiationthrough defparameter statement.
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Memory
Different types and sizes of memory can be formed by extendingvector concept.
Example :
reg [15:0] MemA [511:0]reg [7:0] MemB [1024:0]
C[15:0] = MemA [76];
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Operators
Unary Operator:
associated with single operand, the operator precedes operand
Ex : ~a.
Binary Operator:associated with two operands , the operator is in between
operandsEx : a & b.
Ternary Operator:
associated with three operands. Two operaters seperate theoperands
Ex: A ? B : C;
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System Tasks
During the simulation, a number of activities are to be carried out tomonitor and control simulation.
$ symbol identified task and the task format is
$
Ex : $display, $time, $monitor and so on.
Tasks for control simulation:
$finish : task to exit simulation.$stop : task to resume simulation.