PowerPoint

Department of ElectronicsAdvanced Information Storage16Atsufumi Hirohata

16:00 28/November/2013 Thursday (V 120)1

Quick Review over the Last Lecture

FeRAM :* http://loto.sourceforge.net/feram/doc/film.xhtml;

** http://www.wikipedia.org/;

PRAM :

*** http://phys.nsysu.edu.tw/ezfiles/85/1085/img/588/Oxide-basedResistiveMemoryTechnology_CHLien.pdfReRAM :216 Cache MemoryLevel 1Level 2Level 3Racetrack memoryRegister3Cache Memory

* http://www.engineersgarage.com/mygarage/how-cache-memory-works?page=3

In a PC, cache is used to make processing data fast : *To overcome the von Neumann bottleneck : Access speed : Processor memories4Roles of Cache

* http://www.engineersgarage.com/mygarage/how-cache-memory-works?page=3

To hold the instructions / data which are very commonly used or computer uses frequently.To read the likely data; that is data which is to be most probably read in near future.5Cache Types

* http://www.engineersgarage.com/mygarage/how-cache-memory-works?page=3

6Level 1 Cache

Static memory integrated with a processor coreTo store information recently accessed by a processorTo improve data access speed in cases when the CPU accesses the same data multiple timesAccess time : L1 cache > system memory* http://www.cpu-world.com/Glossary/L/Level_1_cache.html;

Level 1 / primary cache (L1 cache) : *In a modern PC, Split into two caches of equal sizeOne for storing programme dataAnother for storing microprocessor instructions

** http://wccftech.com/review/intel-core-i7-975-extreme-edition/7Level 2 Cache

* http://www.cpu-world.com/Glossary/L/Level_1_cache.html;

Level 2 / secondary cache (L2 cache) : *

** http://wccftech.com/review/intel-core-i7-975-extreme-edition/Large static memory (may be) integrated with a processor coreTo store recently accessed informationTo reduce data access time when the same data was already accessed beforeAccess time : L1 cache > L2 cacheIn a modern PC, Data pre-fetching feature to buffer programme instructions and data to be requestedInclusive cache : requested data staysExclusive cache : requested data removed after transfer to L1 cacheUnified for storing both programme data and microprocessor instructions8Level 3 Cache

* http://www.wisegeek.com/what-is-l3-cache.htm;

Level 3 cache (L3 cache) : *** http://wccftech.com/review/intel-core-i7-975-extreme-edition/Very Large static memory outside a processor core and shared by the coresTo store copies of requested items in case a different core makes a subsequent request.Access time : L1 cache > L2 cache > L3 cache > DRAMIn a modern PC, Inclusive cache : requested data staysExclusive cache : requested data removed after transfer to L1 cacheUnified for storing both programme data and microprocessor instructions

9Data Associativity

Cache memory stores data by a blocked line (64 Bytes for Intel Pentium 4 L1) : ** http://www.wikipedia.org/

Direct mapped : Fastest hit times and best trade-off for large caches2-way set / skewed associative : Best trade-off for 4 ~ 8 kbyte caches4-way set associativeFully associative : Lowest miss rates and best trade-off for very high penalty10Cache Miss* http://www.wikipedia.org/SPEC CPU2000 benchmark test carried out by Hill and Cantin :

Refill process is performed once cache miss occurs :Round robin : Refill data in orderLeast Recently Used (LRU) : Refill from the oldest data accessedRandom Hit rate : LRU > Random > Round robin Complexity : LRU > Random > Round robin11Example : Cache Sizes* http://pc.watch.impress.co.jp/docs/2008/0321/kaigai427.htmIntel Nehalem (2008) :

12Example : Cache Architecture* http://pc.watch.impress.co.jp/docs/2008/0321/kaigai427.htmIntel Nehalem (2008) :

13Memory Development* http://pc.watch.impress.co.jp/docs/2008/0321/kaigai427.htmDeeper memory hierarchy :

14Racetrack MemoryIn 2008, 3-bit racetrack memory was demonstrated by Stuart S. P. Parkin (IBM) : *

* http://www.i-micronews.com/news/IBM-moves-closer-class-memory,1231.html;

Utilise domain-wall motion by STT* S. S. P. Parkin, Sci. Am. 300, 76 (2009).

15Read / Write Operation* S. S. P. Parkin, Sci. Am. 300, 76 (2009).Fully electrical read-out / write-in :

16Racetrack-Memory PropertiesRacetrack memory architecture :

* http://www.ibm.com/Utilise magnetic domain walls1 : head-to-head wall0 : tail-to-tail wallCMOS process compatible3-dimensional (3D) structureReproducible domain-wall trapping3D fabrication

17Racetrack Memory DemonstrationMRAM cell structure :

* http://www.ibm.com/150 nm wide, 20 nm thick and 10 mm long ferromagnetic wiresCMOS implementation

18

Information Technology Pyramid

Layered structures between CPU and storages : *

* http://www.howstuffworks.com/computer-memory1.htm19

Register

Register is a very fast memory directly attached to a processor : ** http://withfriendship.com/user/levis/processor-register.php;

* http://www.wikipedia.org/20