Design of a RISC Processor Compatible with ARM Instruction Set

AHMET GÜRHANLI

LAB: BL405

SUPERVISER: 陳中平 教授

OUTLINE

General Architecture Inputs and Outputs Components Instructions Simulation Results Conclusion

GENERAL ARCHITECTURE

multiply

data out register

instruction

decode

&

control

incrementer

registerbank

address register

barrelshifter

A[31:0]

D[31:0]

data in register

ALU

control

PC

PC

ALU bus

A bus

B bus

register

ARM multi-cycle instruction pipeline operation

fetch ADD decode execute

time

1

fetch STR decode calc. addr.

fetch ADD decode execute

2

3

data xfer

fetch ADD decode execute4

5 fetch ADD decode execute

instruction

Fetch Stage

Decode Stage

Decode/E

xecute Pipeline R

egisters

Execute Stage

INPUTS & OUTPUTS

COMPONENTS

Register Bank

Program Status Register

ALU

Multiplier

The Enhancements We Made

Shortening the Branch Process From 3 cycles to 2 cycles

Fastening the Abort Entry Procedure

The Original Instruction Pipeline

Our Design

Abort Entry

In the original design in case of an abort the running instruction is processed until the end, and then re-processed after abort interrupt.

This may cause unnecessary stalls up to 16 cycles

In our design processor can stop instruction execution immediately in case of a memory abort.

INSTRUCTIONS

Branch

cond 1 0 1 L 24-bit signed word offset

31 28 27 25 24 23 0

Data Processing

Data Processing

ADD R1,R0,#15

ARM Data Processing Instructions

Opco de[2 4 :2 1 ]

Mnemoni c Meani ng Effect

0000 AND Logical bit-wise AND Rd := Rn AND Op20001 EOR Logical bit-wise exclusive OR Rd := Rn EOR Op20010 SUB Subtract Rd := Rn - Op20011 RSB Reverse subtract Rd := Op2 - Rn0100 ADD Add Rd := Rn + Op20101 ADC Add with carry Rd := Rn + Op2 + C0110 SBC Subtract with carry Rd := Rn - Op2 + C - 10111 RSC Reverse subtract with carry Rd := Op2 - Rn + C - 11000 TST Test Scc on Rn AND Op21001 TEQ Test equivalence Scc on Rn EOR Op21010 CMP Compare Scc on Rn - Op21011 CMN Compare negated Scc on Rn + Op21100 ORR Logical bit-wise OR Rd := Rn OR Op21101 MOV Move Rd := Op21110 BIC Bit clear Rd := Rn AND NOT Op21111 MVN Move negated Rd := NOT Op2

Multiply

Rd = Rs*Rm Multiply Rd = Rs*Rm+Rn Multiply Accumulate

Multiply

MUL R4,R2,R1

Multiple Transfer

LDMIA R0!,{R5-R8}

SIMULATION RESULTS

before simulation: memory [ 200] = xxxxxxxx before simulation: memory [ 201] = xxxxxxxx before simulation: memory [ 202] = xxxxxxxx before simulation: memory [ 203] = xxxxxxxx before simulation: memory [ 204] = xxxxxxxx before simulation: memory [ 205] = xxxxxxxx before simulation: memory [ 206] = xxxxxxxx before simulation: memory [ 207] = xxxxxxxx before simulation: memory [ 208] = xxxxxxxx before simulation: memory [ 209] = xxxxxxxx before simulation: memory [ 210] = xxxxxxxx before simulation: memory [ 211] = xxxxxxxx before simulation: memory [ 212] = xxxxxxxx before simulation: memory [ 213] = xxxxxxxx before simulation: memory [ 214] = xxxxxxxx before simulation: memory [ 215] = xxxxxxxx before simulation: memory [ 216] = xxxxxxxx before simulation: memory [ 217] = xxxxxxxx before simulation: memory [ 218] = xxxxxxxx before simulation: memory [ 219] = xxxxxxxx

SIMULATION RESULTS

after simulation: memory [ 200] = 00000111 after simulation: memory [ 201] = 00000000 after simulation: memory [ 202] = 00000000 after simulation: memory [ 203] = 00000000 after simulation: memory [ 204] = 00001111 after simulation: memory [ 205] = 00000000 after simulation: memory [ 206] = 00000000 after simulation: memory [ 207] = 00000000 after simulation: memory [ 208] = 11010000 after simulation: memory [ 209] = 00000000 after simulation: memory [ 210] = 00000000 after simulation: memory [ 211] = 00000000 after simulation: memory [ 212] = 01101001 after simulation: memory [ 213] = 00000000 after simulation: memory [ 214] = 00000000 after simulation: memory [ 215] = 00000000 after simulation: memory [ 216] = 00001111 after simulation: memory [ 217] = 00000000 after simulation: memory [ 218] = 00000000 after simulation: memory [ 219] = 00000000

CONCLUSIONS

Architecture coding is almost finished. Simple synthesis of the design is successful. We will finish the design flow as soon as

possible and make the design ready for tape-out.

THANK YOU