Điều khiển thiết bị qua pc

8/3/2019 iu khin thit b qua PC

1/88

Trang 1

LI MU

Vi vic pht trin ca k thut vi x l hin nay th vic p dng vo thc tini sng l mt nhu cu cn thit ca con ngi. Vi xu hng hin i ha nh hin

nay th vic iu khin thit b bi mt h thng s gip vic iu khin thit bngin v d s dng cho ngi dng.

Nm bt c tnh hnh nhm sinh vin chng em la chn ti iu KhinThit B Qua PC nhm nghin cu cung cp cho ngi dng mt h thng iukhin n gin m hiu qu, l h thng iu khin nhiu thit b ti ch qua vickt ni vi cng COM my tnh, chng ta c thiu khin c cc thit b dn dngnh n dy tc, n hunh quang, v cc thit b c c iu khin bng chcnng ON/OFF.

Thng qua vic nghin cu vi iu khin AT89S8252, cc cng giao tip mytnh v cc linh kin in t, ti s mang li mt h thng n nh, chnh xc v anton vi ngi s dng.

Vi shng dn ca c Nguyn Lan Anh gip chng em hon thnh tt ti ny.

Trong qu trnh tm hiu khng th khng c nhng iu thiu st, mong quThy C v ngi c gp , chnh sa ti ca chng em c hon thin tthn.

Nhm Sinh Vin


2/88

iu khin thit b qua PC Mc lc

Trang 2

MC LC

LI MU .........................................................................................................................1

MC LC ................................................................................................................................2

CHNG 1: DN NHP ....................................................................................................6

1.1 L DO CHN TI ............................................................................................6

1.3 I TNG NGHIN CU V PHM VI NGHIN CU ..........................6

1.3.1 i tng nghin cu. .......................................................................................6

1.3.2 Phm vi nghin cu............................................................................................6

CHNG 2: TM HIU VI IU KHIN AT89S8252 ..............................................7

2.1 M T ........................................................................................................................7

2.2 CU TRC VDK AT89S8252, CHC NNG TNG CHN ........................7

2.3 T CHC B NH .............................................................................................. 11

2.3.1 RAM mc ch chung..................................................................................... 12

2.3.2 RAM nh v. ................................................................................................... 12

2.3.3 Ccbng thanh ghi (Register Banks). .......................................................... 12

2.3.4 Cc thanh ghi chc nng c bit (Special Function Register). ................ 13

2.3.4.1 T trng thi chng trnh (PSW: Program Status Word): .................... 14

2.3.4.2 Thanh ghi B:................................................................................................. 162.3.4.3 Con tr Stack SP (Stack Pointer): ............................................................. 16

2.3.4.4 Hai con tr d liu DPTR (Data Pointer) ................................................. 16

2.3.4.5 Cc thanh ghi Port (Port Register): ........................................................... 16

2.3.4.6 Cc thanh ghi Timer (Timer Register):..................................................... 16

2.3.4.7 Cc thanh ghi Port ni tip (Serial Port Register): .................................. 17

2.3.4.8 Cc thanh ghi ngt (Interrupt Register): ................................................... 17

2.3.4.9 Thanh ghi iu khin ngun PCON (Power Control Register): ............ 182.3.4.10 Thanh ghi iu khin b nhv kim sot gi(WMCON) ............... 19

2.3.4.11 Thanh ghi giao tip ni tip bn ngoi SPI (Serial PeripheralInterface) .................................................................................................................... 20

2.4 TM TT TP LNH CA AT89S8252 ......................................................... 21

2.4.1 Cc chnh v ( addressing mode ) ....................................................... 21

2.4.1.1 Snh v thanh ghi ( Register Addressing) ............................................ 21

2.4.1.2 Snh a ch trc tip ( Direct Addressing ) ........................................ 222.4.1.3 Snh va ch gin tip ( Indirect Addressing) ................................. 22


3/88


Trang 3

2.4.1.4 Snh va ch tc thi (Immediate Addressing) ............................... 23

2.4.1.5 Snh va chtng i ....................................................................... 23

2.4.1.6 Snh a ch tuyt i ( Absolute Addressing) ................................... 24

2.4.1.7 Snh va ch di ( Long Addressing ) .............................................. 24

2.4.1.8 Snh a ch ph lc (Index Addressing )............................................ 242.4.2 Cc kiu lnh (instruction types) ................................................................... 25

2.4.2.1 Cc lnh s hc (Arithmetic Instrustion): ................................................ 25

2.4.2.2 Cc hot ng logic (Logic Operation): ................................................... 26

2.4.2.3 Cc lnh r nhnh ........................................................................................ 27

2.4.2.4 Cc lnh dch chuyn d liu. .................................................................... 29

2.4.2.5 Cc lnh lun l (Boolean Instruction) ..................................................... 30

2.5 HOT NG CA PORT NI TIP AT89S8252. ........................................ 312.5.1 Gii thiu .......................................................................................................... 31

2.5.2 Thanh ghi iu khin port ni tip SCON (Serial Port Control Register) 32

2.5.3 Cc mode hot ng (Mode Of Operation) ................................................. 33

2.5.4 S khi ng, truy xut cc thanh ghi port ni tip .................................... 34

2.5.4.1 S cho php b thu (Recive Enable) ......................................................... 34

2.5.4.2 Bit data th 9 ( the 9th data bit) .................................................................. 34

2.5.4.3 S thm vo bit kim tra chn l Parity .................................................... 342.5.4.4 Cngt .......................................................................................................... 35

2.5.5 S truyn ca b xl a knh ................................................................. 35

2.5.6 Tc baud ca port ni tip ........................................................................ 36

2.6 HOT NG TIMER CA AT89S8252 .......................................................... 39

2.6.1 Gii thiu .......................................................................................................... 39

2.6.2 Timer 0 v Timer 1 ......................................................................................... 39

2.6.2.1 Thanh ghi iu khin Timer TCON (Timer Control Register).............. 412.6.2.2 Cc Mode v ctrn (Timer Modes And Overflow). ............................. 41

2.6.2.2.1 Mode Timer 13 bit (MODE 0) ............................................................. 41

2.6.2.2.2 Mode Timer 16 bit (MODE 1) ............................................................. 42

2.6.2.2.3 Mode tng np 8 bit (MODE 2) ..................................................... 42

2.6.2.2.4 Mode Timer tch ra (MODE 3)............................................................ 43

2.6.2.3 Cc ngun xung clock (Clock Sources).................................................... 43

2.6.2.3.1 S bm gibn trong (Interval Timing) ............................................. 43

2.6.2.3.2 Sm cc s kin (Event Counting) ................................................. 44


4/88


5/88


Trang 5

4.6.1 Tc Baud. .................................................................................................... 65

4.6.2 Bit chn l hay Parity bit. .............................................................................. 65

4.7 S KT NI ................................................................................................... 66

CHNG 5. THIT K MCH PHN CNG IU KHIN ............................. 67

5.1 KHI NGUN NUI VI IU KHIN, MCH. ........................................... 675.2 KHI CHUYN I TN HIU RS232 THNH TTL DNG MAX232... 68

5.2.1 Gii thiu v MAX232 ................................................................................... 68

5.2.2 S kt ni. ................................................................................................... 68

5.3 MCH IU KHIN NG NGT TI AC. ................................................ 69

CHNG 6: THIT K CODE V GIAO DIN IU KHIN.......................... 71

6.1 THIT KCODE IU KHIN VI XL .................................................... 71

6.1.1 tng thit k ............................................................................................... 716.1.2 Lu gii thut ............................................................................................. 72

6.1.3 Code iu khin ............................................................................................... 72

6.2 THIT K GIAO DIN IU KHIN .............................................................. 75

6.3 MCH NGUYN L ........................................................................................... 83

6.4 MCH M PHNG.............................................................................................. 84

CHNG 7: HNG PHT TRIN CA TI................................................. 85

TI LIU THAM KHO ................................................................................................. 86PH LC 1........................................................................................................................... 87

PH LC 2........................................................................................................................... 88


6/88

iu khin thit b qua PC Chng 1: Dn Nhp

Trang 6

CHNG 1: DN NHP

1.1 L DO CHN TIVi s pht trin khng ngng ca cc ngnh khoa hc k thut nhn p ng

ngy cng a dng v phong ph cho i sng con ngi, vic nghin cu v phttrin cc sn phm iu khin t ng thay th sc lao ng ca con ngi l mtnhim v rt cn thit.

Vic gim st v iu khin cc thit b t xa qua h thng gm cc phn t nivi nhau bng dy dn thng qua chun RS232 em li mt li ch ht sc to lncho nhu cu pht trin ca x hi, tit kim c rt nhiu thi gian, sc lc v mangli hiu qu kinh t ln.

Nm bt c tnh hnh quan trng, vi quyt nh la chon ti iu khinthit b qua PC nhm gp phn mang li s tin nghi, tin ch cho cuc sng ngynay.

1.2 MC CH NGHIN CU TI ti s dng iu khin cc thit b dn dng trong gia nh nh n, qut,..

thng qua ngn ng lp trnh ph bin hin nay. T vic tm hiu v cc thit b giaotip cho n vic thit k mch nhm gip ngi c d dng tip nhn v mun cungcp h thng iu khin cho ngi s dng.

1.3 I TNG NGHIN CU V PHM VI NGHIN CU1.3.1 i tng nghin cu.Tm hiu v cc cng giao tip: cng ni tip, cng song song, cng USB,

chun kt ni RS232, kho st vi iu khin AT89S8252.

1.3.2 Phm vi nghin cu.Thc hin vic kt ni thit biu khin vi PC thng qua RS232, iu khin

cc thit b dn dng.


7/88

iu khin thit b qua PC Chng 2: Tm hiu VDK AT89S8252

Trang 7

CHNG 2: TM HIU VI IU KHIN AT89S8252

2.1 M TAT89S8252 l mt vi iu khin do ATMEL sn xut, ch to theo cng ngh

CMOS vi 8KB Flash (Flash programmable and erasable read only memory) v 2KB

EEPROM. Thit b ny c ch to bng cch s dng k thut b nh khng bchi mt cao ca ATMEL v tng thch vi chun cng nghip MSC-52TM v lptp lnh v cc chn ra. AT89S8252 l mt vi iu khin mnh c cng sut ln ctnh linh ng cao v ph hp v gi ci vi cc ng dng vi iu khin.

Cc c im ca AT89S8252 c tm tt nh sau:

Tng thch hon ton vi h MSC-52TM ca Intel. 8 KB b nhc th lp trnh li nhanh, c khnng ti 1000 chu k ghi

xa.

Tn s hot ng t0Hz n 24 MHz.

3 mc kha b nhlp trnh. 3 b Timer/Counter 16 bit. 256 Byte RAM ni. 4 Port xut nhp I/O 8 bt. Giao tip ni tip. 2KB EEPROM bn trong dng lu trchng trnh. bn EEPROM: 100.000 ln ghi/xa. Ch h ngun v ch li tiu tn cng sut thp. 9 ngun ngt. iu khin truyn d liu trc tip qua cc chn MISO, MOSI, SCK.2.2 CU TRC VDK AT89S8252, CHC NNG TNG CHNChc nng hot ng ca tng chn (PIN) c tm tt nh sau:


8/88


Trang 8

Hnh 2.1: S chn AT89S8252

Tchn 18 Port 1 (P1.0, P1.1, , P1.7) dng lm Port xut nhp I/O giaotip bn ngoi vi in tr ko ln bn trong. Cc b m xut ca Port 1 c thcp/ht dng cho 4 ng vo TTL loi LS. Cc chn Port 1 c cc bit 1 c ghi c ko ln mc cao bi cc in trko ln bn trong v trong trng thi ny chngc dng lm cc ng nhp. Khi l Port nhp cc chn ca Port 1 ang c ko

xung mc thp do bn ngoi s cp dng do cc in trbn trong ko ln. Cc chnP1.0 v P1.1 ca Port 1 cng c dng cho cc chc nng T2 v T2EX. Cc chnP1.5, P1.6, P1.7 l cc chn c dng cho cc chc nng MOSI, MISO, SCK iukhin truyn v xut d liu cho vi iu khin. Cng dng chuyn i c lin h vicc t tnh ca AT89S8252 nh sau:

Bng 2.1: Chc nng chuyn i Port 1

Bit Tn Chc nng chuyn i

P1.0 T2 Ng vo ca bnh thi/m 2P1.1 T2EX Np li/thu nhn ca bnh thi 2

P1.4 Ng vo la chn cng Slave

P1.5 MOSI Chn xut d liu Master, nhp d liu Slave

P1.6 MISO Chn nhp d liu Master, xut d liu Slave

P1.7 SCK Ng ra xung clock ca Master, ng vo xung clock Slave


9/88


Trang 9

Chn 9 (RST) l chn RESET cho AT89S8252. Bnh thng cc chn ny mc thp. Khi ta a tn hiu ln mc cao (ti thiu 2 chu k my), th nhng thanhghi ni ca AT89S8252 c LOAD nhng gi tr thch hp khi ng li hthng.

Tchn 1017 l Port 3 (P3.1, P3.1, P3.7) dng vo hai mc ch: dng lmPort xut nhp I/O hoc mi chn li gi mt chc nng c bit c tm tt s bnh sau:

Bng 2.2: Cc chc nng chuyn i Port 3

Bit Tn Chc nng chuyn i

P3.0 RXD D liu nhn cho port ni tip

P3.1 TXD D liu pht cho port ni tip

P3.2 Ngt 0 bn ngoiP3.3 Ngt 1 bn ngoi

P3.4 T0 Ng vo ca timer/counter 0

P3.5 T1 Ng vo ca timer/counter 1

P3.6 Xung ghi b nhd liu ngoi

P3.7 Xung c b nhd liu ngoi

Cc chn 18, 19 (XTAL2 v XTAL1) c ni vi b dao ng thch anh 12MHz to dao ng trn Chp. Hai t30 pF c thm vo n nh dao ng.

Hnh 2.2 Dao ng trn chip vi thch anh

Chn 20 (Vss) ni t (Vss = 0).

T chn 2128 l Port 2 ( P2.0, P2.1, , P2.7) dng vo hai mc nh: dnglm Port xut nhp I/O hoc dng lm byte cao ca bus a ch th n khng cn tc


10/88


Trang 10

dng I/O na. Bi v ta mun EPROM v RAM ngoi nn phi s dng Port 2 lmbyte cao ca bus a ch.

Chn 29 ( ) l tn hiu iu khin xut ra ca AT89S8252, n cho phpchn b nh ngoi v c ni chung vi chn ca OE (Out Enable) ca EPROM

ngoi cho php c cc byte ca chng trnh. Cc xung tn hiu h thptrong sut thi gian thi hnh lnh. Nhng m nh phn ca chng trnh c c tEPROM i qua bus d liu v c cht vo thanh ghi lnh IR ca AT89S8252 bi

m lnh. Khi thi hnh chng trnh trong ROM ni s mc th ng (mc

cao). Khi AT89S8252 ang thc thi lnh t b nhchng trnh ngoi, ctch cc hai ln cho mi chu k my, ngoi tr thi gian mi ln truy xut b nh

d liu ngoi, hai ln tch cc ca c b qua.

Chn 30 (ALE/ : Adress Latch Enable) l tn hiu iu khin xut ra caAT89S8252, n cho php phn knh bus a ch v bus d liu ca Port 0. Cc xungtn hiu ALE c tc bng 1/6 ln tn s dao ng trn chip v c th dng lmngun xung nhp cho cc phn khc ca h thng. Nu nhp xung trn AT89S8252l 12 MHz th ALE c tn s l 2MHz. Tuy nhin cn ch l mt xung ALE s bmt khi truy xut b nh bn ngoi. C th hy b chc nng set ca bit 0 ca thanhghi SFR v tr 8EH. Khi bit ny c set, ALE ch tch cc khi c lnh MOVXhoc MOVC, nu khng c lnh ny ALE mc cao. Vic set bit 0 ca thanh ghi v tr 8EH khng lm nh hng n vi iu khin khi truy cp b nhngoi.

Chn 31 (EA: Eternal Acess) c a xung thp cho php chn b nhmngoi i vi 8031.

i vi AT89S8252 th:

EA = 5V: Chn ROM ni. EA=0V: Chn ROM ngoi. EA=12V: Lp trnh EPROM ni.Cc chn t3239 l Port 0 (P0.0, P0.1, , P0.7) dng cho c hai mc ch:

va lm byte thp cho bus a ch, va lm bus d liu, nu Port 0 khng cn chc

nng xut nhp I/O na.Chn 40 (Vcc) c ni ln ngun 5V.


11/88


Trang 11

2.3 T CHC B NHBn b nhdata trn Chip nh sau:

7F

30

RAM a dng

2F 7F 7E 7D 7C 7B 7A 79 78

2E 77 76 75 74 73 72 71 70

2D 6F 6E 6D 6C 6B 6A 69 68

2C 67 66 65 64 63 62 61 60

2B 5F 5E 5D 5C 5B 5A 59 58

2A 57 56 55 54 53 52 51 50

29 4F 4E 4D 4C 4B 4A 49 48

28 47 46 45 44 43 42 41 40

27 3F 3E 3D 3C 3B 3A 39 38

26 37 36 35 34 33 32 31 30

25 2F 2E 2D 2C 2B 2A 29 28

24 27 26 25 24 23 22 21 2023 1F 1E 1D 1C 1B 1A 19 18

22 17 16 15 14 13 12 11 10

21 0F 0E 0D 0C 0B 0A 09 08

20 07 06 05 04 03 02 01 00

1F

18

Bank 3

17

10Bank 2

0F

08Bank 1

07

00

Bank thanh ghi 0

(mc nh cho R0-R7)

Hnh 2.3: Cu trc b nhtrn AT89S8252


12/88


Trang 12

2.3.1 RAM mc ch chungTrong bn nh trn, 80 byte ta ch 30H7FH l RAM mc ch chung.

K c 32 byte phn di t00H1FH cng c th s dng ging nh 80 byte trn,tuy nhin 32 byte cn c mc ch khc s cp sau.

Bt k v tr no trong RAM mc ch chung cng c thc truy xut ty ging nh vic s dng cc mode nh a ch trc tip hay gin tip. V dcni dung RAM ni c c ch5FH vo thanh ghi tch ly th ta dng lnh

MOV A, 5FH.

Lnh ny chuyn 1 byte d liu dng cch nh a ch trc tip xc nha ch ngun (ngha l 5FH). ch nhn d liu c xc nh ngm trong m lnhl thanh ghi tch ly A.

RAM ni cng c truy xut bi vic dng a ch gin tip qua R0 v R1.

Hai lnh sau y stng ng lnh trn:MOV R0, #5FH

MOV A, @R0

Lnh th nht dng s nh v tc thi a gi tr 5FH vo thanh ghi R0,lnh th 2 dng snh v gin tip a d liu c trn bi R0 vo thanhghi tch ly A.

2.3.2 RAM nh v .AT89S8252 cha 210 v tr c thnh vbit, trong c 128 bit nm cc a

ch t 20H2FH v phn cn li l cc thanh ghi chc nng c bit.

tng truy xut tng bit ring l bng phn mm l mt c tnh tin lica hu ht cc vi iu khin. Cc bit c th t, xo, AND, OR, vi mt lnhn. Trong khi a s cc vi x l i hi mt chui lnh c-sa-ghi thiu qu tng t. Hn na cc port I/O cng c a ch ha theo bit a ch lmn gin ha phn mm xut nhp tng bit.

C 128 bit a dng c a ch ha cc byte 20H n 2FH (8bit/byte x16 bytes = 128 bits). Cc a ch ny c truy cp nh cc byte hoc nh cc bit tytheo lnh s dng. V d, t bit 67H ln gi tr 1, c th dng lnh sau:

SETB 67H

Ch rng, a ch bit 67H l bit c trng s ln nht (MSB) a chbyte 2CH. Lnh trn s khng tc ng n cc bit khc a ch ny.

2.3.3 Cc bng thanh ghi (Register Banks).32 v tr nhcui cng ca b nhta ch byte 00H1FH cha cc dy thanh

ghi. Tp hp cc lnh ca AT89S8252 cung cp 8 thanh ghi t R0R7 a ch

00H07H nu my tnh mc nhin chn thc thi. Nhng lnh tng ng dng snh v trc tip. Nhng gi tr d liu dc dng thng xuyn chc chn s s dngmt trong cc thanh ghi ny.


13/88


Trang 13

Lnh sau sc a ch 05H vo thanh ghi tch ly:

MOV A, R5

y l lnh 1 byte dng cch nh a ch thanh ghi. D nhin, cng tc vc th thc hin bng lnh hai byte dng a ch trc tip nm trong byte th hai:

MOV A, 05HCc lnh dng thanh ghi R0 n R7 th s ngn hn v nhanh hn cc

lnh tng ng nhng dng cch nh a ch trc tip. Cc gi tr d liuc dng thng xuyn nn dng mt trong cc thanh ghi ny.

Bng thanh ghi tch cc c th chuyn i bng cch thay i cc bit chnbng thanh ghi trong t trng thi chng trnh (PSW). Gi s rng thanh ghi3 c tch cc, lnh sau s ghi ni dung ca thanh ghi tch ly vo a ch 18H:

MOV R0, A

tng dng cc bng thanh ghi cho php chuyn ng cnh chng trnhnhanh v hiu qu m tng phn ring r ca phn mm s c mt b thanhghi ring c lp vi cc phn khc.

2.3.4 Cc thanh ghi chc nng c bit (Special Function Register).


14/88


Trang 14

Hnh 2.4: Bn cc thanh ghi c bitCc thanh ghi trong AT89S8252 c t cu hnh nh mt phn ca RAM

trn chip. V vy mi thanh ghi s c mt a ch (ngoi tr thanh ghi m chngtrnh v thanh ghi lnh v cc thanh ghi ny him khi b x l trc tip, nn khng cli g khi t chng trong RAM trn chip). l l do m AT89S8252 khng cnhiu thanh ghi. C 33 thanh ghi chc nng c bit SFR nh ca RAM ni tach cc thanh ghi chc nng c bit c nh r, cn phn cn li khng nh r.

Mc d thanh ghi A c th truy xut trc tip nhng hu ht cc thanh ghi chc

nng c bit c truy sut bng cch s dng snh va ch trc tip. Ch rngvi thanh ghi SFR c c bit nh v v cbyte nh v. Ngi thit k s cn thn khitruy xut bit m khng truy xut byte.

2.3.4.1 Ttrng thi chng trnh (PSW: Program Status Word):

T trng thi chng trnh a chD0H c tm tt nh sau:

Bng 2.3: Tm tt thanh ghi PSW

BIT SYMBOL ADDRESS DESRIPTION

PSW.7 CY D7H Carry FlagPSW.6 AC D6H Auxiliary Carry Flag


15/88


16/88


Trang 16

Bit Parity thng c dng trong s kt hp vi nhng th tc ca Port nitip to ra bit Parity trc khi pht i hoc kim tra bit Parity sau khi thu.

2.3.4.2 Thanh ghi B:

Thanh ghi B c chF0H c dng i i vi thanh ghi A cho cc hot ng

nhn chia.Thanh ghi B c thc dng nh mt thanh ghi m trung gian a mc ch.N l nhng bit nh v thng qua nhng a ch F0HF7H.

2.3.4.3 Con tr Stack SP (Stack Pointer):

Stack Pointer l mt thanh ghi 8 bit a ch 81H. N cha a ch ca d liuang hin hnh trn nh Stack. Cc hot ng ca Stack bao gm vic y d liu voStack (PUSH) v ly d liu ra khi Stack (POP).

Vic PUSH vo Stack stng SP ln 1 trc khi d liu vo.

Vic POP t Stack ra s ly d liu ra trc ri gim SP i 1.2.3.4.4 Hai con tr dliu DPTR (Data Pointer)

Data Pointer c truy xut b nhm ngoi hoc b nhd liu ngoi, nl hai thanh ghi 16 bit m byte thp l DP0L a ch 82H cn byte cao l DP0H ach 83H, 84H (DP1L l byte thp) v 85H (DP1H l byte cao). a ni dung 55Hvo RAM ngoi c c ch 1000H ta dng 3 lnh sau:

MOV A,#55H

MOV DPTR,#1000H

MOVX @ DPTR,A

Lnh th nht dng s nh v trc tip a hng s 55H vo A. Lnh th haicng tng t lnh th nht a hng s d liu 1000H vo trong DPTR. Lnh cuicng dng snh v gin tip chuyn dch gi tr 55H trong A vo vng nhRAMngoi nm trong DPTR.

2.3.4.5 Cc thanh ghi Port (Port Register):

Cc Port 0, Port 1, Port 2, Port 3 c cc a ch tng ng 80H, 90H, A0H,

B0H. Cc Port 0, Port 1, Port 2, Port 3 khng cn tc dng xut nhp na nu b nhngoi c dng hoc mt vi c tnh c bit ca AT89S8252 c dng (nhInterrupt, Port ni tip,...). Do vy ch cn c Port 1 c tc dng xut nhp I/O.

Tt ccc Port u c bit a ch, do n c khnng giao tip vi bn ngoimnh m.

2.3.4.6 Cc thanh ghi Timer (Timer Register):

AT89S8252 cha 3 b nh thi / m 16 bit c dng cho vic nh thihoc m s kin. Timer 0 a ch 8AH (TL0 l byte thp) v 8CH (TH0 l byte

cao). Timer 1 a ch 8BH (TL1 l byte thp) v 8DH (TH1 l byte cao). Timer 2 a ch CCH (TL2 l byte thp) v CDH (TH2 l byte cao).


17/88


Trang 17

Hot ng ca Timer 0 v Timer 1 ca AT89S8252 th ging nh hot ngca Timer 0 v Timer 1 ca AT89C51. Hot ng ca Timer 0 v Timer 1 ct bi thanh ghi Timer Mode (TMOD) a ch89H v thanh ghi iu khin Timer(TCON) a ch 88H. Hot ng ca Timer 2 c t bi cc thanh ghiT2MOD a ch C9H v thanh ghi iu khin T2CON a ch C8H. Cc Timer

c bn chi tit phn sau.2.3.4.7 Cc thanh ghi Port ni tip (Serial Port Register):

AT89S8252 cha mt Port ni tip trn Chip cho vic truyn thng tin vinhng thit b ni tip nh l nhng thit b u cui, modem, hoc giao tip ICkhc vi nhng b bim i A/D, nhng thanh ghi di chuyn, RAM,... Thanh ghi md liu ni tip SBUF c ch 99H gi c d liu pht ln d liu thu. Vic ghi lnSBUF LOAD d liu cho vic truyn v c SBUF truy xut d liu cho vicnhn nhng mode hot ng khc nhau c lp trnh thng qua thanh ghi diu khin

Port ni tip SCON.2.3.4.8 Cc thanh ghi ngt (Interrupt Register):

AT89S8252 c hai cu trc ngt u tin, 6 b ngun ngt. Nhng Interrupt bmt tc dng sau khi h thng reset (b cm) v sau c cho php ghi ln thanhghi cho php ngt IE (Interrupt Enbale Register) a ch A8H. Mc u tin c tvo thanh ghi u tin ngt IP (Interrupt Priority Level) ti a ch B8H. C hai thanhghi trn u c bit a ch.

V tr cc bit nh sau:

EA - ET2 ES ET1 EX1 ET0 EX0

Bit = 1 cho php.

Bit = 0, khng cho php.

Chc nng ca tng bit nhu sau:

Bng 2.4: Tm tt thanh ghi IE (Interrupt Register)

Bit V tr M t

EA IE.7

Khng cho php tt c cc ngt. Nu EA=0, khngcho php ngt, nu EA=1 mi ngun ngt sckch hot hay tt bi vic thit lp hay xa cc bit chophp ca n.

- IE.6 Reserved

ET2 IE.5 Bit cho php Timer 2 ngt

ES IE.4 Bit cho php ngt SPI v UART

ET1 IE.3 Bit cho php Timer 1 ngt.


18/88


Trang 18

EX1 IE.2 Bit cho php ngt ngoi 1

ET0 IE.1 Bit cho php Timer 0 ngt.

EX0 IE.0 Bit cho php ngt ngoi 0

2.3.4.9 Thanh ghi iu khin ngun PCON (Power Control Register):

Thanh ghi PCON khng c bit nh v. N a ch 87H bao gm cc bit tnghp. Cc bit PCON c tm tt nh sau:

Bng 2.5: Tm tt thanh ghi PCON

Bit K hiu M t bit

7 SMOD

Bit tng gp i tc baud; khi c t ln 1 th tc baud c tng gp i trong ch cng ni tip 1, 2 hoc3.

6 - Khng c nh ngha.

5 - Khng c nh ngha.

4 POF

C ngt ngun (Power Off Flag). POF = 1 khi ngun tng.POF c th set v reset bng phn mm iu khin, khng bnh hng bi reset.

3 GF1 Ca dng (General Purpose Flag), bit 1.2 GF0 Ca dng, bit 0.

1 PDCh tt ngun (Power Down); c t ln 1 kchhot ch tt ngun, ch thot khi b xo v 0.

0 IDLCh ngh; c t ln 1 kch hot ch ngh, chthot khi c ngt hoc reset h thng.

Cc bit iu khin Power Down v Idle c tc dng chnh trong tt c cc IC

MSC-51 nhng chc thi hnh trong s bin dch ca CMOS.Ch ngh Idel: Lnh t bit IDL ln 1 s l lnh cui cng c thc thi

trc khi vo ch ngh. Trong ch ngh, tn hiu xung nhp bn trong khng

cung cp cho CPU m ch cung cp cho cc chc nng ngt, nh th v cng nitip. Trng thi CPU v tt c ni dung cc thanh ghi c gi nguyn. Cc chn cc cng cng gi nguyn mc logic ca chng. Tn hiu ALE vc gi mccao. Ch ngh b kt thc bi bt c ngt no c cho php hoc bi reset hthng. Chai iu kin ny xo bit IDL v 0.

Ch tt ngun Power Down: Lnh t bit PD ln 1 s l lnh cui cngc thc thi trc khi vo ch tt ngun.Trong ch tt ngun:


19/88


Trang 19

Dao ng trn chip b dng. Tt c cc chc nng b dng. Tt ccc ni dung ca RAM trn chip c gi nguyn. Cc chn cng cng gi nguyn cc mc logic ca chng. Tn hiu ALE v c gimc thp.

Cch duy nht thot khi ch ny l reset h thng.

Trong ch tt ngun, Vcc c th thp c 2V. Ch l ch c th h Vccsau khi vo ch tt ngun v phc hi Vcc v 5V t nht 10 chu k dao ng

trc khi chn RST xung thp ln na (khi ri khi ch tt ngun).

2.3.4.10 Thanh ghi iu khin b nhv kim sot gi(WMCON)Thanh ghi WMCON (Watchdog And Memory Control Register) a ch 96H

cha cc bit iu khin cho Watchdog Timer c trnh by bng sau. Cc bit

EEMEN v EEMWE c s dng la chn 2 KB trn chip EEPROM v c thghi byte. Bit DPS c s dng la chn 1 trong 2 thanh ghi con tr d liu.

Bng 2.6: Thanh ghi iu khin b nhv Watchdog

Bit K hiu Chc nng

7

6

5

PS2

PS1

PS0

Khi tt c 3 bit ny c t v0, nh thi Watchdog cchu k l 16s, khi tt c 3 bit ny t ln 1, nh thiWatchdog c chu k 2048s

4 EEMWE

Bit ghi b nh d liu EEPROM (EEPROM Data MemoryEnable). Bit ny c t ln 1 trc khi byte u tin ghiln chip EEPROM bng lnh MOVX. Nn dng phn mms dng t bit ny v0 sau khi EEPROM ghi xong.

3 EEMEN

Bit Truy Nhp Eeprom Bn Trong (Internal Eeprom AsscessEnable).Khi EEMEN = 1, lnh MOVX vi con tr d liuDPTR truy cp EEPROM thay v l truy cp b nh d liubn ngoi. Khi EEMEN = 0, lnh MOVX vi DPTR truy cp

d liu bn ngoi.

2 DSPBit chn thanh ghi con tr d liu (Data Pointer RegisterSelect). Khi DPS = 0 chn bng u tin ca thanh ghi contr d liu DP0. Khi DSP = 1 chn bng th hai PD1.

1WDTRST

RDY/

Bit reset nh thi watchdog v c bo Ready/ caEEPROM (Watchdog Timer Reset and EEPROM

Ready/ Flag). Mi ln bit ny c t ln 1 bng phn

mm th s c mt xung pht ra reset nh th watchdog.Khi , bit WDTRST s tng reset v 0 trong chu k lnh


20/88


Trang 20

k tip. Bit WDTRST l bit ch dng ghi. Bit ny cng lc bo sn sng/bn RDY/ dng trong b nh ch c

trong sut qu trnh ghi EEPROM. RDY/ = 1, EEPROMsn sng c lp trnh. Trong khi hot ng lp trnh

ang c thc hin, bit RDY/ s bng 0 v t ngreset v1 khi lp trnh kt thc.

0 WDTEN

Bit cho php nh thi watchdog (Watchdog Timer EnableBit). WDTEN = 1 cho php nh thi watchdog, WDTEN = 0khng cho php nh thi watchdog

2.3.4.11 Thanh ghi giao tip ni tip bn ngoi SPI (Serial PeripheralInterface)

Bit trng thi v iu khin cho SPI c cha trong thanh ghi SPCR a

ch D5H trnh by bng 2.6 v SPSR a ch AAH trnh by bng 2.7. Cc bit dliu SPI cha trong thanh ghi SPDR a ch 86H. Thanh ghi d liu SPI s ghi dliu trong sut qu trnh truyn d liu ni tip t vo bit WCOL (Write Collition)trong thanh ghi SPSR. Thanh ghi SPDR l b m i ghi v gi tr trong SPDRkhng b thay i khi reset.

Bng 2.7: Thanh ghi iu khin SPI

Bit K hiu Chc nng

7 SPIE Bit cho php ngt SPI (SPI Interrupt Enable). Bit ny cng vi bitES trong thanh ghi IE bng 1 cho php ngt SPI. SPIE bng 0khng cho php ngt SPI.

6 SPE Bit cho php SPI (SPI Enable). SPI = 1 cho php knh SPI v kt

ni , MOSI, MISO v SCK n cc chn P1.4, P1.5, P1.6 vP1.7. SPI = 0 khng cho php knh SPI.

5 DORD DORD = 1 chn truyn d liu th nht LSB. DORD = 0 chntruyn d liu th nht MSB.

4 MSTR MSTR = 1 chn kiu Master SPI. MSTR = 0 chn kiu Slave SPI.

3 CPOL Khi CPOL = 1, SCK mc cao khi ch ngh. Khi CPOL =0, SCK mc thp khi khng c truyn thng tin.

2 CPHA Bit CPOL v bit CPHA iu khin xung clock v d liu lienquan gia Master v Slave.

1

0

SPR0

SPR1

Hai bit ny iu khin tc SCK ca thit b kt ni Master.Mi quan h gia SCK v tn s FOSC l:

SPR1 SPR0 SCK = FOSC


21/88


Trang 21

0 0 40 1 16

1 0 64

1 1 128

Bng 2.8: Thanh ghi trng thi SPI

Bit K hiu Chc nng

7 SPIF C ngt SPI (SPI Interrupt Flag). Khi s truyn d liu ni tiphon tt, bit SPIF c t v mt xung ngt pht ra nu SPIE = 1v ES = 1.

6 WCOL Bit WCOL c t nu thanh ghi d liu SPI c ghi trong khid liu c truyn. Trong khi truyn d liu, kt qu c ca

thanh ghi SPDR c th khng ng v qu trnh ghi khng bnhhng.

2.4 TM TT TP LNH CA AT89S8252Cc chng trnh c cu to t nhiu lnh , chng c xy dng logic,s

ni tip ca cc lnh c ngh ra mt cch hiu qu v nhanh,kt qu ca chngtrnh th kh quan.

Tp lnh h MSC-51 c s kim tra ca cc mode nh v v cc lnh cachng c cc Opcode 8 bit.iu ny cung cp khnng 28=256 lnh c thi hnh vmt lnh khng c nh ngha. Vi lnh c 1 hoc 2 byte bi d liu hoc a chthm vo Opcode. Trong ton b cc lnh c 139 lnh 1 byte,92 lnh 2 byte v 24 lnh3 byte.

2.4.1 Cc chnh v ( addressing mode )Cc mode nh v l mt b phn thng nht ca tp lnh mi my tnh. Chng

cho php nh r ngun hoc ni gi ti ca d liu cc ng khc nhau ty thucvo trng thi ca lp trnh. AT89S8252 c 8 mode nh vc dng nh sau:

Thanh ghi.

Trc tip. Gin tip. Tc thi. Tng i. Tuyt i. Di. nh v.2.4.1.1 Snh v thanh ghi ( Register Addressing)Vi cch nh a ch ny ngi ta s dng cc thanh ghi cha d liu.

Ngi ta t ton hng (d liu) trong thanh ghi v x l n bng cch tham chiu


22/88


Trang 22

thanh ghi (bng tn) trong lnh. Khi s dng cc thanh ghi thng dng c hiungm theo ng cnh ca lnh th thanh ghi khng cn cc bit m ha, tuy nhinvi cc thanh ghi khc (R0R7) th cn thm cc bit m ha trong lnh.

C 4 dy thanh ghi 32 byte u tin ca RAM d liu trn Chip a ch00H1FH, nhng ti mt thi im ch c mt dy hot ng cc bit PSW3, PSW4ca t trng thi chng trnh s quyt nh dy no hot ng. Cc lnh nh vthanh ghi c ghi mt m bng cch dng bit trng s thp nht ca Opcode lnh ch mt thanh ghi trong vng a ch theo logic ny. Nh vy 1 m chc nng v ach hot ng c thc kt qu to thnh mt lnh ngn 1 byte nh sau:

n n n

2.4.1.2 Snh a ch trc tip ( Direct Addressing )Snh a ch trc tip c th truy xut bt k gi tr no trn Chip hoc thanh

ghi phn cng trn Chip. Mt byte a ch trc tip c a vo Opccode nh rv tr c dng nh sau:

Ty thuc cc bit bc cao ca a ch trc tip m 1 trong 2 vng nh cchn. Khi bit 7 = 0, th a ch trc tip trong khong 0127 (00H7FH) v 128 v trnh thp ca RAM trn Chip c chn. Tuy nhin, tt c cc I/O v cc SFR, ccthanh ghi trng thi, iu khin c a ch trong khong 80H FFH. Khi MSB ca ach trc tip l 1 th truy cp n cc SFR. Th d cng P0 v P1 c a ch trc tip

tng ng l 80H v 90H. Khng nht thit nh cc a ch ny v trnh hp ngcho php v hiu cc vit tt gi nh cho chng (v d P0 ch Port 0, TMOD chthanh ghi ch timer, ).

2.4.1.3 Snh va ch gin tip ( Indirect Addressing)

Snh va ch gin tip c tng trng bi k hiu @ c t trc R0,R1 hay DPTR. R0 v R1 c th hot ng nh mt thanh ghi con tr m ni dung can cho bit mt a ch trong RAM ni ni m d liu c ghi hoc c c. Bitc trng s nh nht ca Opcode lnh s xc nh R0 hay R1 c dng con tr

Pointer.

Opcode

Opcode

Direct Addressin


23/88


Trang 23

i

V da ni dung 60 H vo RAM ni ti a ch50 H ta lm nh sau:

MOV R1, #50HMOV @R1, 60H

2.4.1.4 Snh va ch tc thi (Immediate Addressing)Khi ton hng ngun l hng s ch khng phi l bin th c th a hng

s vo lnh nh byte d liu tc thi. Snh a ch tc thi c tng trng bik hiu # c ng trc 1 hng s,1 bin k hiu hoc 1 biu thc s hc c sdng bi cc hng , cc k hiu, cc hot ng do ngi iu khin. Trnh bin dchtnh ton gi tr hay thay th d liu tc thi. Byte lnh thm vo cha tr s d liu

tc thi nh sau:

V d:MOV A, #12


24/88


Trang 24

S nh v tng i em li thun li cho vic cung cp m v tr c lp,nhng bt li l ch nhy ngn trong phm vi -128 127 byte.

2.4.1.6 Snh a ch tuyt i ( Absolute Addressing)

Snh a ch tuyt i c dng vi cc lnh ACALL v AJMP. Cc lnh 2

byte cho php phn chia trong trang 2K ang lu hnh ca b nh m ca vic cungcp 11 bit thp nht xc nh a ch trong trang 2K (A0A10 gm A10A8 trongOpcode v A7A0 trong byte ) v 5 bit cao chn trang 2K (5 bit cao ang lu hnhtrong bm chng trnh l 5 bit Opcode).

S nh v tuyt i em li thun li cho cc lnh ngn ( 2 byte ), nhng btli trong vic gii hn phm vi ni gi n v cung cp m c v tr c lp.

2.4.1.7 Snh va ch di ( Long Addressing )

S nh v di c dng vi lnh LCALL v LJMP. Cc lnh 3 byte ny baogm 1 a chni gi ti 16 bit y l 2 byte v 3 byte ca lnh.

u im ca s nh di l vng nh m 64K c th c dng ht, nhcim l cc lnh di 3 byte v v tr l thuc. S ph thuc vo v tr s bt li bichng trnh khng th thc thi ti a ch khc.

2.4.1.8 Snh a ch ph lc (Index Addressing )

S nh a ch ph lc dng 1 thanh ghi c bn ( cng nh b m chngtrnh hoc bm d liu ) v Offset ( thanh ghi A) trong s hnh thnh 1 a ch lienquan bi lnh JMP hoc MOVC.

Base Register Offset Effective Address

Addr 10 Addr 8 Opcode

Addr 7 Addr 0

Opcode

Addr 15 Addr 8

Addr 7 Addr 0

PC (or DPTR) ACC


25/88


Trang 25

Index Addressing

2.4.2 Cc kiu lnh (instruction types)AT89S8252 chia ra 5 nhm lnh chnh:

Cc lnh s hc. Lnh logic. Dch chuyn d liu. L lun. Rnhnh chng trnh.Tng kiu lnh c m tnh sau:

2.4.2.1 Cc lnh s hc (Arithmetic Instrustion): ADD A, ADD A, Rn : (A) (A) + (Rn)ADD A, direct : (A) (A) + (direct)

ADD A, @ Ri : (A) (A) + ((Ri))

ADD A, # data : (A) (A) + # data

ADDC A, Rn : (A) (A) + (C) + (Rn)

ADDC A, direct : (A) (A) + (C) + (direct)

ADDC A, @ Ri : (A) (A) + (C) + ((Ri))

ADDC A, # data : (A) (A) + (C) + # data SUBB A, SUBB A, Rn : (A) (A) (C)(Rn)

SUBB A, direct : (A) (A) (C)(direct)

SUBB A, @ Ri : (A) (A) (C)((Ri))

SUBB A, # data : (A) (A) (C)# data

INC INC A : (A) (A) + 1INC direct : (direct) (direct) + 1

INC Ri : ((Ri)) ((Ri)) + 1

INC Rn : (Rn) (Rn) + 1

INC DPTR : (DPTR) (DPTR) + 1

DEC DEC A : (A) (A) 1

DEC direct : (direct) (direct) 1DEC @ Ri : ((Ri)) ((Ri)) 1


26/88


Trang 26

DEC Rn : (Rn) (Rn) 1

MULL AB : (A) LOW [(A) x (B)], c nh hng cOV

: (B) HIGH [(A) x (B)], cCarry c xa.

DIV AB : (A) Integer Result of [(A)/(B)], cOV

: (B) Remainder of [(A)/(B)], cCarry xa.DA A : iu chnh thanh ghi A thnh sBCD ng trong

php cng BCD (thng DA A di km vi ADD, ADDC)

Nu [(A3 A0) > 9] v [(AC) = 1] 9] v [(C) = 1]


27/88


Trang 27

XRL direct, # data : (direct) (direct) ) # data.

Y = a ) b = ab + ab

CLR C : (C) 0.

CLR Bit : (Bit) 0.

RL A : quay vng thanh ghi A qua tri 1 bit(An + 1) (An), n = 06

(A0) (A7)

RLC A : quay vng thanh ghi A qua tri 1 bit c cCarry

(An + 1) (An), n = 06

(C) (A7)

(A0) (C)

RR A : quay vng thanh ghi A qua phi 1 bit(An + 1) (An), n = 06

(A0) (A7)

RRC A : quay vng thanh ghi A qua phi 1 bit c cCarry

(An + 1) (An), n = 06

(C) (A7)

(A0) (C)

SWAP A : i ch 4 bit thp v 4 bit cao ca A cho nhau(A3A0)(A7A4)

2.4.2.3 Cc lnh r nhnh

C nhiu lnh diu khin r nhnh ln chng trnh bao gm vic gi hoctr li tchng trnh con hoc chia nhnh c iu kin hay khng c diu kin.

Tt c cc lnh rnhnh u khng nh hng n c. Ta c thnh nhn cnnhy ti m khng cn ch ra ch, trnh bin dch st a chni cn nhy ti vong khu lnh a ra.

Sau y l s tm tt tng loi hot ng nhy.

JC rel : nhy n rel nu cCarry C = 1.

JNC rel : nhy n rel nu cCarry C = 0.

JB bit, rel : nhy n rel nu (bit) = 1.

JNB bit, rel : nhy n rel nu (bit) = 0.

JBC bit, rel : nhy n rel nu bit = 1 v xa bit.

ACALL addr11 : lnh gi tuyt i trong page 2K.

(PC) (PC) + 2(SP) (SP) + 1


28/88


Trang 28

((SP)) (PC7PC0)

(SP) (SP) + 1

((SP)) (PC15PC8)

(PC10PC0) page address

LCALL addr16 : lnh gi di chng trnh con trong 64K(PC) (PC) + 3

(SP) (SP) + 1

((SP)) (PC7PC0)

(SP) (SP) + 1

((SP)) (PC15PC8)

(PC) Addr15Addr0

RET : kt thc chng trnh con tr v chng trnhchnh.

(PC15PC8) (SP)

(SP) (SP) 1

(PC7PC0) ((SP))

(SP) (SP) 1

RETI : kt thc th tc phc v ngt quay vchng trnhchnh hot ng tng tnh RET.

AJMP Addr11 : nhy tuyt i khng iu kin trong 2K

(PC) (PC) + 2

(PC10PC0) page Address

LJMP Addr16 : nhy di khng iu kin trong 64K

Hot ng tng tnh LCALL.

SJMP rel : nhy ngn khng iu kin trong (-128127) byte

(PC) (PC) +2

(PC) (PC) + byte 2

JMP @ A + DPTR : nhy khng iu kin n a ch (A) + (DPTR)

(PC) (A) + (DPTR)

JZ rel : nhy n A = 0. Thc hnh lnh k nu A 0.

(PC) (PC) + 2

(A)= 0 0


29/88


Trang 29

CJNE A, direct, rel : so snh v nhy n A direct

(PC) (PC) + 3

(A)< > (direct)


30/88


Trang 30

MOV Rn, # data : (Rn) # data

MOV direct, A : (direct) (A)

MOV direct, Rn : (direct) (Rn)

MOV direct, direct : (direct) (direct)

MOV direct, @ Ri : (direct) ((Ri))MOV direct, # data : (direct) # data

MOV @ Ri, A : ((Ri)) (A)

MOV @ Ri, direct : ((Ri)) (direct)

MOV @ Ri, # data : ((Ri)) # data

MOV DPTR, # data 16 : (DPTR) # data 16

MOV A, @ A + DPTR : (A) (A) + (DPTR)

MOV @ A + PC : (PC) (PC) + 1(A) (A) + (PC)

MOVX A, @ Ri : (A) ((Ri))

MOVX A, @ DPTR : (A) ((DPTR))

MOVX @ Ri, A : ((Ri)) (A)

MOVX @ DPTR, A : (DPTR) (A)

PUSH direct : ct d liu vo Stack

(SP) (SP) + 1 (SP) (direct)

POP direct : ly t Stack ra direct

(direct) ((SP))

(SP) (SP) 1

XCH A, Rn : i ch ni dung ca A vi Rn

(A) (Rn)

XCH A, direct : (A) (direct)XCH A, @ Ri : (A) ((Ri))

XCHD A, @ Ri : i ch 4 bit thp ca (A) vi ((Ri))

(A3A0) ((Ri3Ri0))

2.4.2.5 Cc lnh lun l (Boolean Instruction)

AT89S8252 cha mt b x l lun l y cho cc hot ng bit n. y lmt im mch ca hvi iu khin MSC-51 m cc h x l khc khng c.

RAM ni cha 128 bit n v v cc vng nhcc thanh ghi chc nng c bit

cp ln n 128 bit n v khc. Tt ccc ng Port l bt nh v, mi ng c thc x l nh Port n v ring bit. Cch truy xut cc bit ny khng ch cc lnh r


31/88


Trang 31

nhnh khng, m l mt danh mc y cc lnh MOVE, SET, CLEAR,COMPLEMENT, OR, AND.

Ton b s truy xut ca bit dng s nh v trc tip vi nhng a ch t00H7FH trong 128 vng nh thp v 80HFFH cc vng thanh ghi chc nng cbit.

Bit Carry C trong thanh ghi ca t trng thi chng trnh v c dngnh mt s tch ly n ca b x l lun l. Bit Carry cng l bit nh vv c a

ch trc tip v n nm trong . Hai lnh CLR C v CLR CY u c tc dng lxa bit cCarry nhng lnh ny mt 1 byte cn lnh sau mt 2 byte.

Hot ng ca cc lnh lun l c tm tt nh sau:

CLR C : xa cCarry xung 0. Cnh hng cCarry.

CLR BIT : xa bit xung 0. Khng c nh hng cCarry.

SET C : set cCarry ln 1. C nh hng cCarry.SET BIT : set bit ln 1. Khng nh hng cCarry.

CPL C : o bt cCarry. C nh hng cCarry.

CPL BIT : o bit. Khng nh hng cCarry

ANL C, BIT : (C) (C) AND (BIT). C nh hng cCarry.

ANL C, /BIT : (C) (C) AND NOT (BIT). Khng nh hng cCarry.

ORL C, BIT : (C) (C) OR (BIT). Tc ng cCarry.ORL C, /BIT : (C) (C) OR NOT (BIT). Tc ng cCarry.

MOV C, BIT : (C) (BIT). C Carry btc ng.

MOV BIT, C : (BIT) (C). Khng nh hng cCarry.

2.5 HOT NG CA PORT NI TIP AT89S8252.2.5.1 Gii thiuHot ng port ni tip ca AT89S8252 cng ging nh hot ng ni tip ca

h 8051, v th ta s xt Port ni tip AT89S8252 nh h 8051.

Port ni tip ca AT89S8252 c th hot ng trong cc mode ring bit trnphm vi cho php ca tn s. Chc nng ch yu ca Port ni tip l thc hin schuyn i song song thnh ni tip cho d liu ra v s chuyn i ni tip thnhsong song cho d liu vo.

Phn cng truy xut ti Port ni tip qua cc chn TXD (P3.1) v RXD (P3.0).Port ni tip tham d hot ng y ( s pht v thu cng lc), v thu vo b

m m n cho php 1 k t nhn vo v c ct b m trong khi k t th 2c nhn vo. Nu CPU c k t th nht trc khi k t th2 c nhn vo hon

ton th d liu khng b mt.


32/88


Trang 32

Hai thanh ghi chc nng c bit cung cp cho phn mm truy xut n Portni tip l SBUF v SCON. Sm Port ni tip ( SBUF) a ch 99H l 2 smtht s : Ghi ln SBUF LOAD d liu pht v c SBUF truy xut d liu nhn.y l 2 thanh ghi ring bit v r rt, m thanh ghi pht ch ghi cn thanh ghi thu chc. S khi ca Port ni tip nh sau:

Hnh 2.5: S khi Port ni tip

Thanh ghi iu khin Port ni tip SCON (98H) l thanh ghi c nh v bitbao gm cc trng thi v cc bit iu khin. Cc bit iu khin set mode ca Port nitip, cn cc bit trng thi cho bit s kt thc vic thu pht 1 k t. Cc bit trng thic thc kim tra trong phn mm hoc c th lp trnh sinh ra s ngt.

Tn s hot ng ca Port ni tip hoc tc BAUD c thc ly t daong trn Chip AT89S8252 hoc thay i. Nu 1 tc Baud thay i c dng, th

Timer cung cp 1 tc Baud ghi giv phi c lp trnh 1 ccah1 ph hp.2.5.2 Thanh ghi iu khin port ni tip SCON (Serial Port Control

Register)Mode hot ng ca Port ni tip AT89S8252 c set bi vic ghi ln thanh

ghi mode ca Port ni tip SCON a ch 99H. Bng tm tt thanh ghi iu khinPort ni tip SCON nh sau:


33/88


Trang 33

Bng 2.9: Tm tt thanh ghi SCON

Bit K kiu a ch M t hot ng

SCON.7 SM0 9FH Bit 0 ca mode Port ni tip

SCON.6SM1 9EH Bit 1 ca mode Port ni tip

SCON.5 SM2 9DH

Bit 2 ca mode Port ni tip. Cho php struyn ca b x l a knh mode 2, 3.RI s khng tch cc nu bit th9 thuvo l 0.

SCON.4 REN 9CH REN = 1 s cho thu k t

SCON.3 TB8 9BHPht bit 8. Bit 9 pht trong mode 2 v 3,

n c st hoc xa bi phn mm.

SCON.2 RB8 9AH Thu bit 8, bit 9 thu.

SCON.1 TI 99HC ngt pht. c set khi kt thc struyn k tv c xa bi phn mm.

SCON.0 RI 98HCngt thu. c set khi kt thc s thu

v c xa bi phn mm

SCON Register Sumary

2.5.3 Cc mode hot ng (Mode Of Operation)Bng 2.10: Bng MODE hot ng ca Port ni tip.

SM0 SM1 Mode M t Tc Baud

0 0 0 Thanh ghi dch

C nh (tn s dao ng

FOSC/12).

0 11

URAT 8 bit Thay i (c t bi Timer).

1 0 2 URAT 9 bitCnh (tn sdao ng FOSC/64hoc FOSC/32.

1 13

URAT 9 bit Thay i (c t bi Timer).

SCON Register Sumary


34/88


Trang 34

Trc khi dng Port ni tip, SCON phi c gn ng mode. V d khign Port ni tip MODE 1 (SM0/SM1 = 0/1), cho php thu ( REN = 1), v set cngtca vic pht sn sng hot ng (TI =1 ), ta dng lnh sau:

MOV SCON, # 01010010H.

Port ni tip ca AT89S8252 c 4 mode hot ng ty thuc theo 4 trng thica SM0/SM1.

Ba trong 4 mode cho php truyn s ng b vi mi k t thu hoc pht sc b tr bi bit Start hoc bit Stop.

2.5.4 Skhi ng, truy xut cc thanh ghi port ni tip2.5.4.1 Scho php b thu (Recive Enable)Bit cho php thu REN trong thanh ghi SCON phi c set bi phn mm

cho php s thu cc k t. iu ny thng c lm u chng trnh khi cc Port

ni tip v cc Timer c khi ng.Ta c th khi ng bng lnh :SETB REN hoc MOV CON, #XXX1XXXXB2.5.4.2 Bit data th9 ( the 9th data bit)Bit data th 9 c pht trong mode 2 v mode 3 phi c LOAD vo TB8

bi phn mm, cn bit data th9 c thu th t trong RB8.Phn mm c th ( hoc khng ) i hi 1 bit data th 9 tham gia vo nhng chi

tit k thut ca thit b ni tip vi iu kin m s truyn data c thnh lp.2.5.4.3 Sthm vo bit kim tra chn l Parity

Cch tng qut dng chung bit data th 9 l cng bit Parity vo 1 k t.Bit P (Parity) trong t trng thi chng trnh PSW sc set hoc xa vi

mi chu kmy thnh lp bit Parity chn vi 8 bit trong thanh ghi tch ly A.V d nu s truyn yu cu 8 bit data cng thm 1 bit Parity chn, th cc lnh

sau y c thc dng pht 8 bit vo thanh ghi A vi Parity chn c cng vobit th 9.

MOV C, P

MOV TB8, C

MOV SBUF, ANu Parity lc yu cu th cc lnh trn c sa li l:MOV C, P

CPL C

MOV TB8, C

MOV SBUF, A

Vic dng bit Parity khng b gii hn trong mode 2 hoc mode 3.8 bit datac pht trong mode 1 c th bao gm 7 bit data, v 1 bit Parity. pht 1 m ASCII

7 bit vi 1 bit Parity chn vo 8 bit, cc lnh sau y c dng :CLR ACC, 7 : xa bit MSB trong A m bo Parity chnMOV C, P : a Parity chn vo C


35/88


Trang 35

MOV ACC.7, C :a Parity chn vo bit SB ca AMOV SBUF, A :gi bit data cng bit Parity chn2.5.4.4 CngtC ngt thu RI v pht TI trong thanh ghi SCON vn hnh 1 rle quan trng

trong s truyn ni tip AT89S8252. C2 bit u c set bi phn cng nhng phi

xa bi phn mm.in hnh l RI c set cui s thu k t v cho bit : thanh ghi m thu

y. iu kin ny c th kim tra trong phn mm hoc c thc lp trnh sinhra s ngt. Nu phn mm mun nhp 1 k t t 1 thit b c kt ni n Port nitip, th n phi chn khi RI c set, sau khi xa RI v c k t tSBUF. iuny c lp trnh nh sau :

WAIT :

JNB RI, WAIT : kim tra RI c set cha

CLR RI :xa cngt thu RIMOV A, SBUF : CPU c k t

TI c set cui s pht k t v cho bit thanh ghi m ca s pht rng. Nu phn mm mun gi 1 k tn 1 thit b c kt ni n Port nitip, trc tin n phi kim tra xem Port ni tip sn sng cha. Nu k t trc c gi i, th n phi ch cho n khi spht i hon thnh. Cc lnh sau ydng pht 1 k t trong thanh ghi A ra :

WAIT :

JNB RI, WAIT : kim tra TI c set chaCLR RI :xa cngt thu TIMOV A, SBUF : CPU c k t

2.5.5 Struyn ca b xl a knhMode 2 v mode 3 c 1 s cung cp c bit cho vic truyn a knh x l.

cc mode ny, 9 bit data c thu v bit th9 i vo RB8. Port c th lp trnh nhiu m bit Stop thu c, s ngt ca Port chc tch cc nu RB8 = 1. c imny cho php bi vic set bit MS2 trong thanh ghi SCON. ng dng ny l 1 s cit mng c dng bi nhiu AT89S8252 s sp t my chv my con nh sau


36/88


Trang 36

Hnh 2.6: S b xl a knh AT89S8252

Khi b x l ch mun pht 1 khi d liu n b x l con ring l, trc tinn gi ra 1 byte a ch nhn din b x l con mong mun. Byte a chc phnbit vi byte d liu bi bit th 9 : bit th 9 bng 1 trong bit a ch v bng 0 trongbyte d liu. Tuy nhin byte a ch s ngt ton b cc b x l con, do c thkhm ph byte thu kim tra nu n ang nh a ch. B xl con c nha ch s xa bit SM2 ca n v chun b thu cc byte d liu theo sau . Nhng bx l con khng c nh a ch vn c gi cc bit SM2 ca n v set trv ccbn ca chng ng thi li cc byte d liu thu thp. Chng sc ngt li khibyte a ch k tip c pht bi b x l c.

Bit SM2 khng c tc dng trong mode 0 v trong mode 1 n c thc dng kim tra s thch hp ca bit Stop. Trong s thu mode 1, nu SM2 = 0 th s ngtthu s khng tch cc tr khi bit Stop thch hp c thu.

2.5.6 Tc baud ca port ni tipTc Baud ca port ni tip cnh mode 0 v mode 2. Trong mode 0 n

lun lun l tn sdao ng trn Chip chia cho 12. Thng thng thch anh 12 MHzl dao ng trn Chip AT89S8252 nn tc Baud ca mode 0 l 1 MHz.

On Chip OscillatorBaud Rate Clock

MODE 0

Bng s mc nhin sau khi reset h thng, tc Baud mode 2 l tn s daong chia cho 64, tc Baud cng bnh hng bi bit SMOD ca thanh ghi PCON.

Vic set bit SMOD stng gp i tc Baud trong cc mode 1, 2 v 3. Trongmode 2, tc Baud c thc gp i t gi tr mc nh 1/64 tn s /Chip ( ngSMOD = 0 ) ln n 1/32 tn sdao ng trn Chip ( ng vi SMOD = 1 ).

+12


37/88


Trang 37

SMOD = 0

On Chip Oscillator

Baud Rate Clock

SMOD = 1

MODE 1

Bi thanh ghi PCON khng c bit nh v, nn set bit SMOD m khng thayi cc bit khc ca thanh ghi PCON th i hi phi c 1 hot ng c b sungghi.

Cc lnh sau y set bit SMOD :MOV A, PCON :nhp vo A gi tr hin hnh ca PCONSETB ACC, 7 :set bit 7 ca ACC ( bit SMOD )MOV PCON, A : ghi gi tr trvPCON m SMOD c set

Cc tc Baud trong mode 1 v mode 3 ca AT89S8252 c xc nh bitc trn ca Timer 1. Bi v Timer hot ng tn s cao lin tc nn trn xa hnna c chia cho 32 ( chia cho 16 nu SMOD = 1 ) trc khi cung cp xung clocktc Baud n Port ni tip. Tc Baud mode 1 v 3 ca AT89S8252 c xc

nh bi tc trn ca Timer 1 hoc Timer 2, hoc c 2.

SMOD = 0

On Chip Oscillator

Baud Rate Clock

SMOD = 1

MODE 2

Mun sinh ra tc Baud, ta khi gn TMOD mode tng np 8 bit ( mode2 ca Timer ) v t gi trReload ng vo byte cao ca thanh ghi Timer 1 (TH1) sinh ra tc trn chnh xc cho tc Baud. C nhng tc Baud rt chm ta dngmode 16 bit l mode 1 ca Timer, nhng ta phi khi gan sau mi s trn choTL1/TH1 trong th tc phc v ngt ISR.

Hot ng khc c m gibi vic dng Timer 1 ngoi l T1 (P3.5). Cngthc chung xc nh tc Baud trong mode 1 v mode 3 l:

BAUD RATE = TIMER 1 OVERFLOW RATE32

+64

+32

+32

+16


38/88


Trang 38

V d 1 hot ng 1200 Baud i hi 1 tc trn l 1200/32 = 38,4KHz. Nuthch anh 12 MHz li dao ng trn Chip, th Timer 1 c m gitc ca tns 1 MHz. Bi v Timer phi trn tc tn s38,4 KHz v Timer m gitc ca tn s 1 MHz, nn 1 s trn c yu cu vi 1000:38,4 = 26,04 clock (lm trn26). Bi v cc Timer m ln v trn trn s chuyn i t FFH 00H ca bm, nn

26 s m thp di 0 l gi tr Reload cn np cho TH1 ( gi trng l -26 ). Tadng lnh MOV TH1, #26.

V d sau khi ng Port ni tip hot ng ging nh UART 8 bit tc Baud 2400, dng Timer 1 cung cp sm gitc Baud :

MOV SCON, #01010010B : port ni tip mode 1.MOV TMOD, #20 : timer 1 mode 2.

MOV TH1, # -13 :np vo bm tc 2400 Baud.SETB TR1 : Start Timer 1.

Trong SCON c SM0/SM1 vo mode UART 8 bit, REN = 1 cho php Portni tip thu cc k t v TI = 1 cho php pht k tu tin bi vic cho bit thanhghi m rng. TMOD c M1/M0 = 1/0 t Timer 1 vo mode tng np 8 bit.Vic set bit TR1 m my chy Timer. Tc Baud 2400 s cho ta tc trnTimer 1 l 2400/32 = 76,8 KHz ng thi Timer 1 c m gitc ca tn s1000KHz ( ng vi thch anh 12MHz ) s cho s xung Clock sau mi s trn l1000:76,8 = 13,02 (ly trn 13 ). Vy -13 l gi tr cn np vo TH1 c tc Baudl 2400 Baud.

Sau y l bng tm tt tc Baud ph bin ng vi 2 loi thch anh 12 MHzv 11,059 MHz :

Bng 2.11: Tm tt tc Baud ph bin

Baud RateCrytal

FrequencySMOD

TH1ReloadValue

ActuaBaud Rate

Error

9600 12 MHz 1 -7 (F9H 8923 7%

2400 12 MHz 0 -13 (F9H) 2404 0.16%

1200 12 MHz 0 -23 (F9H) 1202 0%

19200 11.059 MHz 1 -3 (F9H) 19200 0%

9600 11.059 MHz 0 -3 (F9H) 9600 0%

2400 11.059 MHz 0 -12 (F9H) 2400 0%

1200 11.059 MHz 0 -24 (F9H) 1200 0%

Baud Rate Sumary


39/88


Trang 39

2.6 HOT NG TIMER CA AT89S82522.6.1 Gii thiuBnh thi ca Timer l mt chui cc Flip Flop c chia lm 2, n nhn tn

hiu vo l mt ngun xung clock, xung clock c a vo Flip Flop th nht lxung clock ca Flip Flop th hai m n cng chia tn s clock ny cho 2 v c tiptc.

V mi tng k tip chia cho 2 nn Timer tng phi chia tn s clock ng vocho 2n. Ng ra ca tng cui cng l clock ca Flip Flop trn Timer hoc cm nkim tra bi phn mm hoc sinh ra ngt. Gi tr nh phn trong cc Flip Flop ca bTimer c thc ngh nh m xung clock hoc cc s kin quan trng bi v Timerc khi ng. V d Timer 16 bit c thm t FFFFH sang 0000H.

Cc Timer c ng dng thc t cho cc hot ng nh hng. AT89S8252c 3 b Timer 16 bit, mi Timer c 4 mode hot ng. Cc Timer dng m gi,m cc s kin cn thit v s sinh ra tc ca tc Baud bi s gn lin Port nitip.

Trc ht ta st Timer 0 v Timer 1 ca AT89S8252.

2.6.2 Timer 0 v Timer 1Timer 0 v Timer 1 ca AT89S8252 ging nh h 8051.

Mi s nh thi l mt Timer 16 bit, do tng cui cng l tng th 16 schia tng s clock vo cho 216 = 65536.

Trong cc ng dng nh thi, 1 Timer lp trnh trn mt khong thi gianu n v c set c trn Timer. C c dng ng bchng trnh thchin mt hot ng nh vic a ti mt tng ng vo hoc gi d liu n ng ra.Cc ng dng khc c s dng vic ghi giu u ca Timer o thi gian tri quagia hai trang thi (v dnh o rng xung). Vic m mt d kin c dng xc nh s ln xut hin ca s kin , tc thi gian tri qua gia cc s kin.

Cc Timer 0 v Timer 1 ca AT89S8252 c truy sut bi vic dng 6 thanhghi chc nng c bit nh sau:

Bng 2.12: Cc thanh ghi truy sut Timer 0 v Timer 1

Timer SFR Purpose Address Bi t - Addressable

TCON Control 88H YES

TMOD Mode 89H NO

TL0 Timer 0 lowbyte 8AH NO

TL1 Timer 1 lowbyet 8BH NO

TH0 Timer 0 highbyte 8CH NO


40/88


Trang 40

TH1 Timer 1 highbyte 8DH NO

Thanh ghi Mode Timer TMOD (Timer Mode Register)

Thanh ghi mode gm 2 nhm 4 bit l: 4 bbit thp t mode hot ng cho

Timer 0 v 4 bit cao t mode hot ng cho Timer 1 8 bit ca thanh ghi TMOD ctm tt nh sau:

Bng 2.13: Tm tt hot ng thanh ghi TMOD

Bit Name Timer Description

7 GATE 1Khi GATE = 1, Timer ch lm vic khiINTI = 1

6 C/T 1

Bit cho m s kin hay ghi gi

C/T = 1: m s kin

C/T = 0: ghi giu n

5 M1 1 Bit chn mode cua Timer 1


3 GATE 0 Bit cng ca Timer 0

2 C/T 0 Bit chn Counter/Timer ca Timer 0



Hai bit M0 v M1 ca TMOD chn mode cho Timer 0 hoc Timer 1.

Bng 2.14: Hot ng 2 bt M0 v M1

M1 M0 MODE Description

0 0 0 Mode Timer 13 bit (mode 8048)

0 1 1 Mode Timer 16 bit1 0 2 Mode tng np 8 bit

1 1 3

Mode Timer tch ra:

Timer 0: TL0 l 8 bit c diu khin bicc bit ca Timer 0. TH0 tng t nhngc iu khin bi cc mode Timer 1.

Timer 1: c ngc li


41/88


Trang 41

TMOD khng c bit nh v, n thng c LOAD mt ln phn mm uchng trnh khi ng mode Timer. Sau snh gic th dng li, c khing li nh th bi s truy sut cc thanh ghi chc nng c bit ca Timer khc.

2.6.2.1 Thanh ghi iu khin Timer TCON (Timer Control Register)

Thanh ghi iu khin bao gm cc bt trang thi v cc bit iu khin bi Timer0 v Timer 1. Thanh ghi TCON c bt nh v. Hot ng ca tng bit c tm ttnh sau:

Bng 2.15: Tm tt hot ng thanh ghi TCON

Bit SymbolBit

AddressDescription

TCON.7 TF1 8FH

C trn Timer 1 c set bi phn cng

s trn, c xa bi phn mm hocbi phn cng khi cc vecto xl n thtc ngt ISR.

TCON.6 TR1 8EH

Bit iu khin chy Timer 1 c sethoc xa bi phn mm chy hocngng chy Timer.

TCON.5 TF0 8DHC trn Timer 0 ( hot ng tng t

TF1).TCON.4 TR0 8CH Bit iu khin chy Timer 0 (ging TR1).

TCON.3 IE1 8BH

C kiu 1 ngt ngoi. Khi cnh xungxut hin trn INT1 th IE1 c xa biphn mm hoc phn cng khi CPU nhhng n th tc phc v ngt ngoi.

TCON.2 IT1 8AH

C kiu 1 ngt ngoi c set hoc xabng phn mm bi cnh kch hot bi sngt ngoi.

TCON.1 IE0 89H Ccnh ngt 0 ngoi.

TCON.0 IT0 88H Ckiu ngt 0 ngoi.

2.6.2.2 Cc Mode v ctrn (Timer Modes And Overflow).

AT89S8252 c Timer l Timer 0 v Timer 1. Ta dng k hiu TLx v THx ch 2 thanh ghi byte thp v byte cao ca Timer 0 hoc Timer 1.

2.6.2.2.1

Mode Timer 13 bit (MODE 0)


42/88


Trang 42

Timer Clock

Overflow

MODE 0

Mode 0 l mode Timer 13 bit, trong byte cao ca Timer (THx) c t thpv 5 bit trng s thp ca byte thp Timer (TLx) t cao hp thnh Timer 13 bit. 3bit cao ca TLx khng dng.

2.6.2.2.2 Mode Timer 16 bit (MODE 1)Timer Clock

OverFlow

MODE 1

Mode 1 l mode Timer 16 bit, tng tnh mode 0 ngoi tr Timer ny hotng nh mt Timer y 16 bit, xung clock c dng vi s kt hp cc thanh ghicao v thp (TLx, THx). Khi xung clock c nhn vo, b m Timer tng ln0000H, 0001H, 0002H,... v mt s trn s xut hin khi c s chuyn trn bmTimer t FFFFH sang 0000H v s set ctrn Timer, sau Timer m tip.

C trn l bit TFx trong thanh ghi TCON m n sc c hoc ghi bi phn

mm.Bit c trng s ln nht (MSB) ca gi tr trong thanh ghi Timer l 7 bit ca

THx v bit c trng s thp nht (LSB) l bit 0 ca TLx. Bit LSB i trng thi tnsclock vo c chia 216 = 65536.

Cc thanh ghi Timer TLx v THx c thc c hoc ghi ti bt k thi imno bi phn mm.

2.6.2.2.3 Mode tng np 8 bit (MODE 2)

Timer Clock

Overflow

Reload

MODE 2

Mode 2 l mode tng np 8 bit, byte thp TLx ca Timer hot ng nh mtTimer 8 bit trong khi byte cao THx c a Timer gi gi tr Reload. Khi bm trn t

TFxTHx (8 bit)TLx (5 bit)

TLx (8 bit) THx (8 bit) TFx

THx (8 bit)

TLx (8 bit) TFx


43/88


Trang 43

FFH sang 00H, khng ch c trn c st m gi tr trong THx cng c np voTLx. Bm ny c tip tc t gi trny ln n s chuyn trng thi t FFH sang00H k tip v c th tip tc. Mode ny th ph hp bi v cc s trn xut hin cth m mi lc ngh thanh ghi TMOD v THx c khi ng.

2.6.2.2.4 Mode Timer tch ra (MODE 3)Timer Clock

Overflow

Timer Clock

Overflow

Timer Clock

Overflow

MODE 3

Mode 3 l mode tch ra v l s khc bit cho mi Timer.

Timer 0 mode 3 c chia lm 2 Timer 8 bit. TL0 v TH0 ho t ng nhnhng Timer ring l vi su75 trn sset cc bit TL0 v TF1 tng ng.

Timer 1 b dng li mode 3, nhng c thc khi ng bi vic ngt nvo 1 trong cc mode khc. Chc nhc im l c trn TF1 ca Timer 1 khng nhhng bi cc s trn ca Timer 1 bi v TF1 c ni vi TH0.

Mode 3 tt yu cung cp 1 Timer ngoi 8 bit l Timer th ba ca AT89S8252.Khi vo Timer 0 mode 3, Timer c th hot ng hoc tt bi s ngt n ra ngoi vvo trong mode ca chnh n hoc c thc dng bi Port ni tip nh l mt mypht tc Baud, hoc c thdng trong hng no m khng s dng Interrupt.

2.6.2.3 Cc ngun xung clock (Clock Sources)

C 2 ngun xung clock c thm giv snh gibn trong v sm skin bn ngoi. Bit C/T trong TMOD cho php chn mt trong hai khi Timer chot ng.

2.6.2.3.1 Sbm gibn trong (Interval Timing)Nu bit C/T = 0 th hot ng ca Timer lin tc v c chn vo b Timer

c ghi gi t dao ng trn Chip. Mt b chia 12 c thm vo gim tn sclock n 1 gi tr ph hp hu ht cc ng dng. Cc thanh ghi TLx v THx tng tc

1/12 ln tn sdao ng trn Chip. Nu dng thch anh 12 MHz th sa n tc clock 1 MHz.

TLx (8 bit) THx (8 bit)

TF0TLx (8 bit)

TLx (8 bit) TF1


44/88


Trang 44

Cc s trn Timer sinh ra sau mt con s cnh ca nhng xung clock n phthuc vo gi tr khi to c LOAD vo cc thanh ghi Thx v TLx.

2.6.2.3.2 Sm cc skin (Event Counting)Nu bit C/T = 1 th bTimer c ghi gi t b ngun bn ngoi trong nhiu

ng dng, b ngun bn ngoi ny cung cp 1 s nh gi vi 1 xung trn s xy raca s kin. Snh gi l sm s kin. Con s skin c xc nh trong phnmm bi vic c cc thanh ghi Timer. TLx/THx, bi v gi tr 16 bit trong cc thanhghi ny tng ln cho mi s kin.

Ngun xung clock bn ngoi a chn P3.4 l ng nhp ca xung clock biTimer 0 (T0) v P3.5 l ng nhp ca xung clock bi Timer 1 (T1).

Trong cc ng dng m cc thanh ghi Timer c tng trong p ng ca schuyn trang thi t 1 sang 0 ng nhp Tx. Ng nhp bn ngoi c th trong sut

S5P2 ca mi chu kmy. Do khi ng nhp a ti mc cao trong mt chu k vmc thp trong mt chu k k tip th bm tng ln mt. Gi tr mi xut hin trongcc thanh ghi Timer trong sut S5P1 ca chu k theo sau mt s kn chuyn i ckhm ly. Bi v n chim 2 chu kmy (2s) nhn ra s chuyn i t 1 sang 0,nn tn s bn ngoi ln nht l 500 KHz nu dao ng thch anh 12 MHz.

2.6.2.4 Sbt u, kt thc v siu khin cc Timer (Starting, StopingAnd Controlling The Timer)

Bit TRx trong thanh ghi c bit nh vTCON c khin bi phn mm bt

u hoc kt thc cc Timer. bt u cc Timer ta set bit TRx v kt thc Timerta clear TRx. V d Timer 0 c bt u bi lnh SETB TR0 v c kt thc bilnh CLR TR0 (bit GATE = 0). Bit TRx b xa sau s seset h thng, do cc Timerb cm bng s mc nh.

Thm phng php na iu khin cc Timer l dng bit GATE trong thanhghi TMOD v ng nhp bn ngoi INTx. u ny c dng o cc rng xung.Gi s xung a vo chn INT0 ta khi ng Timer 0 cho mode 1 l mode Timer 16bit vi TL0/TH0 = 0000H, GATE = 1, TR0 = 1. Nh vy khi INT0 = 1 th Timer

c m cng v ghi gi vi tc ca tn s 1 MHz. Khi INT0 xung thp thTimer ng cng v khong thi gian ca xung tnh bng s l s m c trongthanh ghi TL0/TH0.

2.6.2.5 Skhi ng v truy sut cc thanh ghi Timer.

Cc Timer c khi ng mt ln u chng trnh t mode hot ngcho chng. Sau trong thn chng trnh cc Timer c bt u, c xa, ccthanh ghi Timer c c v cp nht... theo yu cu ca tng ng dng c th.

Mode Timer TMOD l thanhg ghi u tin c khi gn, bi v t mode hot

ng cho cc Timer. V d khi ng cho Timer 1 hot ng mode 1 (mode Timer16 bit) v c ghi gi bng dao ng trn Chip ta dng lnh: MOV TMOD, #00001000B. Trong lnh ny, M1 = 0, M0 = 0 vo mode 1 v C/T = 0, GATE = 0


45/88


Trang 45

cho php ghi gi bn trong ng thi xa cc bit mode ca Timer 0, sau lnh trnTimer vn cha m gi, n ch bt u m gikhi set bit iu khin chy TR1 can.

Nu ta khng khi gn gi tr u cho cc thanh ghi TLx/THx th Timer s btu m t 0000H ln v khi trn t FFFFH sang 0000H li m t 0000H ln.

Nu ta khi gn gi tr u cho TLx/THx, th Timer s bt u m t gi trgn ln nhng khi trn t FFFFH sang 0000H li m t 0000H ln.

Ch c trn TFx tng sc st ln bi phn cng sau mi su75 trn vsc xa bi phn mm. Chnh v vy ta c th lp trnh chsau mi ln trn ta sxa c TFx v quay vng lp khi gn cho TLx/THx Timer lun lun bt u mt gi tr khi gn ln theo ta mong mun.

c bit nhng s khi gn nhhn 256 s, ta s gi mode Timer tng np

8 bit ca mode 2. Sau khi khi gn gi tru vo THx, khi set bit TRx th Timer sbt u m gi tr khi gn v khi trn t FFH sang 00H trong TLx, cTRx tngc set ng thi gi tr m ta khi gn cho THx c n \p t ng vo TLx vTimer li m t gi tr khi gn ny ln. Ni cch khc, sau mi trn ta khng cnkhi gn li cho cc thanh ghi Timer m chng vn m c li t gi tr ban u.

2.6.2.6 Sc thanh ghi timer trn tuyn.

Trong mt s ng dng cn thit c gi tr trong cc thanh ghi Timer trntuyn, c mt vn tim nng n gin bo v li phn mm. Bi v 2 thanh ghi

Timer phi c c, nn li giai on c th xut hin nu byte trn v byte caogia 2 hot ng c. Mt gii php khc phc l c byte cao trc, sau cbyte thp, v c li byte cao. Nu byte cao thay i th lp li cc hot ng c.

2.6.3 Timer 2Timer 2 c 3 ch hot ng l capture, auto-reload v baud rate generator.

Timer 2 bao gm 8-bit, TH2 v TL2. Trong cc chc nng hn gi, thanh ghi TL2c tng ln mi chu k my. K t khi mt chu k my bao gm 12 thi gian daong, t l tnh l 1 / 12 ca tn sdao ng.

Trong cc chc nng truy cp, thanh ghi c tng ln p ng mt schuyn tip 1-to-0 u vo ca n tng ng bn ngoi, T2. Trong chc nng ny,cc u vo bn ngoi l ly mu trong S5P2 mi chu k my. Khi cc mu cho thymt cao trong mt chu k v mt thp trong chu k tip theo, vic m c tng ln.Gi tr m mi xut hin trong thanh ghi trong sut S3P1 ca chu k sau m trong qu trnh chuyn i c pht hin.

K t khi hai chu k my (24 khong thi gian dao ng) c yu cu nhn ra mts chuyn i 1 - 0, t l s lng ti a l 1 / 24 ca tn s dao ng. m bo cho

mc ly mu t nht mt ln trc khi n thay i, mc cn c t chc cho tnht mt chu k my y .


46/88


Trang 46

Bng 2.16: Hot ng Timer 2

RCLK+TCLK CP/ TR2 MODE

0 0 1 16 bit auto-reload

0 1 1 16 bit capture

1 X 1 Baud Rate generator

X X 0 Off

2.6.3.1 Thanh ghi T2CON (Timer/Counter 2 Control Regi ster)Thanh ghi T2CON c nh v a ch 0C8H, y l thanh ghi 8 bit, v tr

cc bit nh sau:

TF2 EXF2 RCLK TCLK EXEN2 TR2 C/ CP/

76 5 4 3 2 1 0

Ta xt chc nng tng bit nh sau:

Bng 2.17: Chc nng tng bt T2CON

Bit M t

TF2

C trn ca Timer 2 c set ln 1 khi bm Timer 2 trn vphi c xa bng phn mm. TF2 khng sc set ln 1 khimt trong hai RCLK = 1 hoc TCLK = 1.

EXF2

C ngt ngoi ca Timer 2 c set khi c mt capture hocreload c gy ra bi mt qu trnh chuyn i v T2EX vEXEN2 = 1. Khi Timer 2 c cho php ngt, EXF2 = 1 s gyra CPU thng xuyn ngt Timer 2. EXF2 phi c xa biphn mm. EXF2 khng gy ra mt ngt trong ch ln / xungtruy cp (DCEN = 1).

RCLK

Nhn c xung clock cho php. Khi thit lp, nh hng ticng ni tip s dng s trn ca Timer 2 nhn tn hiu xung

t cng ni tip ch 1 v 3. RCLK = 0 gy ra cho Timer 1trn s dng cho nhn xung clock.

TCLK

Truyn tn hiu xung clock. Khi thit lp, nh hng ti cng nitip s dng s trn ca Timer 2 truyn tn hiu xung t cngni tip ch1 v 3. TCLK = 0 gy ra cho Timer 1 trn, sdng cho nhn xung clock.

EXEN2

Cho php ngt ngoi Timer 2. Khi c thit lp, cho phpcapture hoc reload xy ra nh l kt qu ca mt qu trnh

chuyn i trn T2EX nu Timer 2 l khng c s dng taoclock cng ni tip. EXEN2 = 0, Timer 2 b qua cc s kin


47/88


Trang 47

ti T2EX.

TR2 Start / Stop kim sot Timer 2. TR2 = 1 bt u hn gi.

C/

Chn chc nng m hay hn gi ca Timer 2. C/T2 = 0 chnchc nng hn gi. C/T2 = 1 chn m s kin (xung cnh xung

kch hot m).

CP/

Capture / Reload chn. CP/RL2 = 1 chn capture trn cc qutrnh chuyn i ti T2EX nu EXEN2 = 1. CP/RL2 = 0 chnreload tng xy ra khi Timer 2 trn hoc qu trnh chuyn ixy ra ti T2EX khi EXEN2 = 1. Khi RCLK hoc TCLK = 1, bitny c b qua v vic hn gis tng reload li khi Timer 2trn.

2.6.3.2 Thanh ghi T2MOD Timer 2 Mode Control Register

Thanh ghi T2MOD c xc nh a ch C9H, gm 8 bit nh sau:

- - - - - - T2OE DCEN

Bit 7 6 5 4 3 2 1 0

Chc nng ca tng bt:

Bit 1 T2OE: bt cho php Timer 2 xut ra.

Bit 0 DCEN: bt cho php Timer 2 m ln hay m xung.2.6.3.3 Ch Capture

Trong ch capture, hai la chn c la chn bi bit EXEN2 trongT2CON. Nu EXEN2 = 0, Timer 2 l mt b m thi gian 16 -bit hoc truy cp mkhi trn b bit TF2 trong T2CON. Bit ny sau c th c s dng to ra mtgin on. Nu EXEN2 = 1, Timer 2 thc hin cng hot ng, nhng l - 0 mt qutrnh chuyn i ti T2EX u vo bn ngoi cng lm cho gi tr hin ti TH2 v TL2 capture vo RCAP2H v RCAP2L, tng ng. Ngoi ra, chuyn tip T2EX gy ra

bit EXF2 trong T2CON c thit lp. Cc bit EXF2, nh TF2, c th to ra mtngt..


48/88


Trang 48

Hnh 2.7: Timer 2 trong ch Capture2.6.3.4 Ch Auto-Reload

Timer 2 c th c lp trnh m ln hoc xung khi cu hnh t ng 16 -bit ca ch auto-reload. Tnh nng ny c gi bi DCEN (Down Counter Enable)bit nm T2MOD SFR. Khi reset, cc bit DCEN c thit lp l 0 Timer 2 mcnh m. Khi DCEN c thit lp, Timer 2 c th m ln hoc xung, ty thucvo gi tr ca T2EX.

Hinh 2.8 cho thy Timer 2 t ng m ln khi DCEN = 0. Trong ch ny,

hai ty chn c la chn bi bit EXEN2 trong T2CON. Nu EXEN2 = 0, Timer 2m ln FFFFH v sau thit lp bit TF2 khi trn. Trn cng gy ra cc b m thigian ng k c np li vi gi tr 16- bit trong RCAP2H v RCAP2L. Cc gi trtrong RCAP2H v RCAP2L c ci sn bng phn mm. Nu EXEN2 = 1, 16 bitreload c th c kch hot bi s trn hoc bi mt s chuyn tip 1 - 0 u vo bn ngoi T2EX. iu ny chuyn i cng thit lp cc bit EXF2. C hai TF2 vEXF2 bit c th to ra mt ngt nu c kch hot.


49/88


Trang 49

Hnh 2.8: Timer 2 trong ch Auto Reload

Thit lp cc bit DCEN cho php Timer 2 m ln hoc xung, nh th hintrong hnh 2.9. Ch, PIN T2EX iu khin theo hng m. Mt logic 1 ti T2EXlm cho Timer 2 m. B m thi gian s trn ti FFFFH v thit lp cc bit TF2.Trn cng lm cho gi tr 16-bit trong RCAP2H v RCAP2L c np li vo sngk hn gi, TH2 v TL2, tng ng.

Mt logic 0 T2EX lm cho Timer 2 m ngc. Hn giunderflows khi TH2v TL2 bng gi trc lu tr trong RCAP2H v RCAP2L. Underflows thit lp bitTF2 v giFFFFH c np li vo sng k hn gi.

Bit EXF2 Toggles bt c khi no Timer 2 trn hoc underflows v c thcs dng nh mt 17 bit phn gii. Trong ch ny hot ng, EXF2 khng nhdu mt ngt

Hnh 2.9: Timer 2 trong ch Auto-Reload2.6.3.5 Ch Baud Rate Generator


50/88


Trang 50

Hnh 2.10: Timer 2 trong ch Baud Rates Generator

Timer 2 c chn l my pht in tc truyn bng cch thit lp TCLKand/or RCLK trong T2CON. Lu rng tc baud cho truyn v nhn c th khcnhau nu Timer 2 c s dng cho cc my thu hoc my pht v Timer 1 c sdng cho cc chc nng khc. Thit lp RCLK and/or TCLK a Timer 2 vo mypht in tc truyn ch, nh trong hnh 2.10.

T l chmy pht in baud l tng tnh ch tng ti li, trong

mt R trong TH2 nguyn nhn Timer 2 ng k c np li vi gi tr 16-bit vo sng k RCAP2H v RCAP2L, c ci sn bi phn mm.

Mc truyn trong cc ch1 v 3 c xc nh bng t l trn Timer 2theo phng trnh sau y:

Timer c thc cu hnh cho mt trong hai bm thi gian hoc hot ngtruy cp. Trong hu ht cc ng dng, n c cu hnh cho cc hot ng hn gi

(CP/T2 = 0). Cc hot ng hn gikhc nhau hn gi2 khi n c s dng nhmt my pht in tc truyn. Thng thng, khi mt gi, n gia tng mi chu kmy (1 / 12 tn s dao ng). Nh mt my pht in tc truyn, tuy nhin , ntng mi khi nh nc (1 / 2 tn sdao ng). Cng thc tc truyn a ra diy

()

Vi (RCAP2H, RCAP2L) l ni dung ca RCAP2H v RCAP2L c thc

hin nh l mt 16 -bit kiu s.


51/88

iu khin thit bqua PC Chng 3: Tm hiu cc cng giao tip

Trang 51

CHNG 3: TM HIU CC CNG GIAO TIP

3.1 GIAO TIP CNG SONG SONG (CNG MY IN)3.1.1 Tn giCng song song: D liu c truyn qua cng ny theo cch song song, c th

d liuc truyn 8 bit ng thi hay cn gi byte ni tip bit song song.Cng my in: L do l hu ht cc my in u c ni vi my tnh qua cng

ny.

C ng Centronic: y l tn ca mt cng ty thit k ra cng ny. Centronic

l tn mt cng ty chuyn sn xut my in kiu ma trn ng hng u th gii. Chnhcng ty ny ngh ra kiu thit k cng ghp ni my in vi my tnh.

3.1.2 Mc in p cngu s dng mc in p tng thch TTL(Transiztor - Transiztor - Logic)

0V5V trong: 0V l mc logic LOW 2V5V l mc logic HIGH

V vy khi ghp ni vi cng ny ta ch ghp ni nhng thit b ngoi vi c mcin p tng thch TTL. Nu thit b ngoi vi khng c mc in p tng thch TTLth ta phi p dng bin php ghp mc hoc ghp cch ly qua b ghp ni quang.

3.1.3 Khong cch ghp niKhong cch cc i gia thit b ngoi vi v my tnh ghp qua cng songsong thng b hn ch. L do l hin tng cm ng gia cc ng dn v in

dung k sinh hnh thnh gia cc ng dn c th lm bin dng tn hiu. Khongcch gii hn cc i l 8m. Thng thng ch1,5 n 2m v l do an ton d liu. Nus dng khong cch ghp ni trn 3m th cc ng dy tn hiu v ng dy nit phi c son vi nhau thnh tng cp gim thiu nh hng ca nhiu. Binphp khc s dng cp dt, trn mi ng d liu c t gia hai ng dy nit.

3.1.4 Tc truyn d liuTc truyn d liu qua cng song song ph thuc vo phn cng c s

dng. Trn l thuyt tc c th t n 1Mb/s nhng vi khong cch truyn hnch trong phm vi 1m. Vi nhiu mc ch s dng th khong cch ny hon tontha ng, tuy vy cng c nhng ng dng i hi phi truyn trn khong cch xahn. Trong trng hp ta phi ngh ngay n kh nng ghp ni khc (nh ghpni qua cng RS232).

3.1.5 Cu trc cng song songCng song song c hai loi: cm 36 chn v cm 25 chn. Ngy nay, loi cm 36 chn khng cn c s dng, hu ht cc my tnh PC u trang b cm 25

chn nn ta ch cn quan tm n loi 25 chn.


52/88


Trang 52

Cng song song gm c 4 ng iu khin, 5 ng trng thi v 8 ng dliu bao gm 5 ch hot ng:

Chtng thch (compatibility). Ch nibble. Ch byte. Ch EPP (Enhanced Parallel Port). Ch ECP (Extended Capabilities Port).Ba chu tin s dng port song song chun (SPPStandard Parallel Port)

trong khi ch 4, 5 cn thm phn cng cho php hot ng tc cao hn.

Bng 3.1 S chn ca my in

CHN K HIU

NG

VO/RAM T

1 STROBE RA

2 n 9 D0 n D9 RA Cc bit d liu tD0 n D7

10 ACK VO Bo nhn

11 BUSY VO Bo bn

12 PE VO Ht giy

13 SEL Vo La chn

14 AF RA Tng tip ng

15 ER VO Li

16 INIT RA Thit lp thit b

17 SELIN RA La chn u vo

18 n 25 GND VO Ni t

Cng song song c ba thanh ghi c th truyn d liu v iu khin my in. a

chc sca cc thanh ghi cho tt c cng LPT (line printer) tLPT1 n LPT4 clu tr trong vng d liu ca BIOS. Thanh ghi d liu c nh v offset 00h,thanh ghi trng thi 01h, v thanh ghi iu khin 02h. Thng thng, a chc s


53/88


Trang 53

ca LPT1 l 378h, LPT2 l 278h, do a ch ca thanh ghi trng thi l 379h hoc279h v a ch thanh ghi iu khin l 37Ah hoc 27Ah. Tuy nhin trong mt strng hp, a ch ca cng song song c th khc do qu trnh khi ng ca BIOS.BIOS slu trcc a chny nh sau:

Bng 3.2: a chc scc tthanh ghi cng song song

a ch Chc nng

0000H0408H a chc sca LPT1

0000H040AH a chc sca LPT2

0000H040CH a chc sca LPT3

3.1.6 Cc thanh ghi cng song song.Thanh ghi d liu (hai chiu):

Tn hiu D7 D6 D5 D4 D3 D2 D1 D0

Chn s 9 8 7 6 5 4 3 2

Thanh ghi trng thi my in (chc):

Tn hiu my BUSYACK PAPER

EMPTYSELECT ERROR IPR X X

S chn cm 11 10 12 13 15 - - -

Thanh ghi iu khin my in:

Tn hiumy in

X X DIR IRQ SELECTIN INIT AUTOFEED STROBE

S chn - - - - 17 16 14 1

x: khng s dng

IRQ Enable: yu cu ngt cng; 1 = cho php; 0 = khng cho php

Ch rng chn BUSY c ni vi cng o trc khi a vo thanh ghi

trng thi, cc bit SELECTIN , AUTOFEED v STROBE c a qua cng otrc khi a ra cc chn ca cng my in. Thng thng tc x l d liu ca ccthit b ngoi vi nh my in chm hn PC nhiu nn cc ng ACK , BUSY v STRc s dng cho k thut bt tay. Khi u, PC t d liu ln bus sau kch hotng STR xung mc thp thng tin cho my in bit rng d liu n nh trnbus. Khi my in x l xong d liu, n s tr li tn hiu ACKxung mc thp ghinhn. PC i cho n khi ng BUSY t my in xung thp (my in khng bn) thsa tip d liu ln bus.

3.2 GIAO TIP CNG NI TIP (RS232)3.2.1 Cu trc cng ni tip.


54/88


Trang 54

Cng ni tip c s dng truyn d liu hai chiu gia my tnh v ngoivi, c cc u im sau:

Khong cch truyn xa hn truyn song song. S dy kt ni t. C th truyn khng dy dng hng ngoi. C th ghp ni vi vi iu khin hay PLC (Programmable Logic

Device).

Cho php ni mng. C th tho lp thit btrong lc my tnh ang lm vic. C th cung cp ngun cho cc mch in n gin.Cc thit b ghp ni chia thnh 2 loi: DTE (Data Terminal Equipment) v

DCE (Data Communication Equipment). DCE l cc thit b trung gian nh MODEMcn DTE l cc thit b tip nhn hay truyn d liu nh my tnh, PLC, vi iu khin,

Vic trao i tn hiu thng thng qua 2 chn RxD (nhn) v TxD (truyn). Cctn hiu cn li c chc nng h tr thit lp v iu khin qu trnh truyn, cgi l cc tn hiu bt tay (handshake). u im ca qu trnh truyn dng tn hiu bttay l c th kim sot ng truyn.

Tn hiu truyn theo chun RS-232 ca EIA (Electronics IndustryAssociations). Chun RS-232 quy nh mc logic 1 ng vi in p t -3V n -25V(mark), mc logic 0 ng vi in p t3V n 25V (space) v c khnng cung cpdng t 10 mA n 20 mA. Ngoi ra, tt c cc ng ra u c c tnh chng chp

mch. Chun RS-232 cho php truyn tn hiu vi tc n 20.000 bps nhng nucp truyn ngn c thln n 115.200 bps.

Cc phng thc ni gia DTE v DCE:

n cng (simplex connection): d liu chc truyn theo 1 hng.

Bn song cng ( half-duplex): d liu truyn theo 2 hng, nhng mi thiim chc truyn theo 1 hng.

Song cng (full-duplex): s liu c truyn ng thi theo 2 hng.

nh dng ca khung truyn d liu theo chun RS-232 nh sau:Start

0 STOP

Khi khng truyn d liu, ng truyn s trng thi mark (in p -10V).Khi bt u truyn, DTE sa ra xung Start (space: 10V) v sau ln lt truyn tD0 n D7 v Parity, cui cng l xung Stop (mark: -10V) khi phc trng thing truyn.

Cc c tnh k thut ca chun RS-232 nh sau:

D0 D1 D2 D3 D4 D5 D6 D7 P


55/88


Trang 55

Chiu di cable cc di 15m

Tc d liu cc i 20 Kbps

in p ng ra cc i 25V

in p ng ra c ti5V n 15V

Trkhng ti 3K n 7K

in p ng vo 15V

nhy ng vo 3V

Trkhng ng vo 3K n 7K

Cc tc truyn d liu thng dng trong cng ni tip l: 1200 bps, 4800bps, 9600 bps v 19200 bps.

S chn cng ni tip

Cng COM c hai dng: u ni DB25 (25 chn) v u ni DB9 (9 chn) mtnh bng 4.3.

Bng 3.3: ngha ca cc chn cng ni tip

D25 D9 Tn hiu Hng truyn M t

1 - - - Protected ground: ni t bo v

2 3 TXD DTE DCE Transmitted data: d liu truyn

3 2 RXD DCE DTE Received data: d liu nhn

4 7 RTS DTE DCE Request to send: DTE yu cu truyn d liu

5 8 CTS DCE DTE Clear to send: DCE sn sng nhn d liu


56/88


Trang 56

6 6 DSR DCE DTE Data set ready: DCE sn sng lm vic

7 5 GND - Ground: ni t (0V)

8 1 DCD DCE DTE Data carier detect: DCE pht hin sng mang

20 4 DTR DTE DCE Data terminal ready: DTE sn sng lm vic

22 9 RI DCE DTE Ring indicator: bo chung

23 - DSRD DCE DTE Data signal rate detector: d tc truyn

24 - TSET DTE DCETransmit Signal Element Timing: tn hiunh thi

15 - TSET DCE DTETransmitter Signal Element Timing: tn hiunh thi

17 - RSET DCE DTE Receiver Signal Element Timing: tn hiunh thi

18 - LL Local Loopback: kim tra cng

21 - RL DCE DTERemote Loopback: To ra bi DCE khi tnhiu nhn

14 - STxD DTE DCE Secondary Transmitted Data

16 - STxD DCE DTE Secondary Received Data

19 - SRTS DTE DCE Secondary Request To Send

13 - SCTS DCE DTE Secondary Clear To Send

12 - SDSRD DCE DTE Secondary Received Line Signal Detector

25 - TM Test Mode

9 - Dnh ring cho ch test

10 - Dnh ring cho ch test

11 - Khng dng

3.2.2 Truyn thng ni tip gia 2 nt.Cc s khi kt ni dng cng ni tip:

DTE1 DTE2 DTE DCE

Kt ni n gin trong truyn thng ni tip

TXD

RXD

GND

TXD

RXD

GND

TXD

RXD

GND

TXD

RXD

GND


57/88


Trang 57

Khi thc hin kt ni nh trn, qu trnh truyn phi bo m tc u phtv thu ging nhau. Khi c d liu n DTE, d liu ny sc a vo bm vto ngt.

Ngoi ra, khi thc hin kt ni gia hai DTE, ta cn dng s sau:

Kt ni trong truyn thng ni tip dng tn hiu bt tay

Khi DTE1 cn truyn d liu th cho DTR tch cc tc ng ln DSR ca DTE2cho bit sn sng nhn d liu v cho bit nhn c sng mang ca MODEM (o).Sau , DTE1 tch cc chn RTS tc ng n chn CTS ca DTE2 cho bit DTE1

c th nhn d liu. Khi thc hin kt ni gia DTE v DCE, do tc truyn khcnhau nn phi thc hin iu khin lu lng. Qu trinh iu khin ny c th thchin bng phn mm hay phn cng. Qu trnh iu khin bng phn mm thc hinbng hai k t Xon v Xoff.

K tXon c DCE gi i khi rnh (c th nhn d liu). Nu DCE bn th sgi k t Xoff. Qu trnh iu khin bng phn cng dng hai chn RTS v CTS. NuDTE mun truyn d liu th s gi RTS yu cu truyn, DCE nu c kh nngnhn d liu (ang rnh) th gi li CTS.

3.3 TM HIU V USB3.3.1 Khi nimMy in c ni vi my tnh qua cng song song trong khi hu ht cc my

tnh ch c trang b mt cng ny. S rt kh khn nu s dng thm Zip, lun ihi tc kt ni cao vi my tnh v cn thit phi dng cng song song.

Modem c ni vi my tnh qua cng ni tip ging nh mt vi dng thit b khc nh Digital Camera, Palm Pilots trong khi mi my tnh thng ch c haicng ni tip v chng rt chm.

TXD

RXD

GND

RTS

CTS

DSR

DCD

DTR

TXD

RXD

GND

RTS

CTS

DSR

DCD

DTR


58/88


Trang 58

Cc thit b i hi cc kt ni nhanh hn nh cc Card c bit c cm trctip vo khe cm (Slot) trn bo mch. Thc t s lng cc khe cm (Slot) l c hn vcn phi ci t cc phn mm cho thit b ny.

Mc ch ca USB l gii quyt cc vn ca ngi s dng khi cc cng ktni trn khng hiu qu. USB cung cp cho ngi s dng kh nng kt ni chun, ddng vi 127 thit b trn cng mt my tnh. Mi thit b ngoi vi hin nay u c thkt ni trn cng mt phin bn USB chng hn nh: my in, my qut nh, chut,Joystick, Digital Camera, Webcam, Modem, loa, in thoi, Network Connection,thit b lu tr thng tin ( Zip)...

3.3.2 Kt ni qua USBVic ni mt thit b vi my tnh qua USB ht sc n gin, ch vic cm cc

u ni ca thit b vi cc cng USB trn my tnh. Nu thit b c kt ni vi mytnh ln u, h iu hnh s t ng d tm v yu cu np a Driver. Vi thit b c ci t, my tnh t ng kch hot v kt ni vi thit b. Cc thit b kt ni quaUSB c th thit lp hay ngt kt ni bt k lc no. Nhiu loi thit b USB c chto lin vi cp ni vi hai kiu u ni A Connection v B Connection.

Chun USB s dng A Connection v B Connection trong hai trng hpc th sau:

USB Type B

Chn 1 v 4 cp ngun 5 VDC.

Chn 2 v 3 l chn truyn d liu.

3.3.3 Mrng cng USBThng thng cc my tnh hin nay ch c mt hoc hai khe cm USB (USB

Socket). Ngy nay vi a s cc thit b u s dng USB, my tnh rt d b thiu khecm. V d, trn my tnh c cc thit b nh: my in, my qut, Webcam,... s dngUSB trong khi my tnh ch c mt cng USB (USB Connector).

gii quyt vn ny, ch cn lp thm mt USB Hub. Chun USB h trti 127 thit b v USB Hub l mt trong s ny. Cc Hub ny thng c bn cngnhng cng c th c nhiu hn tu thuc tng loi. Ch cn cm USB Hub vo my

tnh sau cm cc thit b hoc Hub khc vo cc cng trn USB Hub.


59/88


Trang 59

Hub c hai loi: loi c cung cp ngun v khng cung cp ngun in chothit b cm vo Hub. Chun USB cho php cc thit b s dng ngun in t cngUSB. Cc thit b nh my in, my qut s dng ngun in ring cung cp t bngun (Power Supply) ca chng trong khi cc thit b s dng rt t in nng nhchut, Digital Camera li dng in nng (khong 500mA - 5V) t Bus.

Nu my tnh kt ni vi nhiu thit b s dng ngun in ring (My in,my qut...) th USB Hub khng cn thit phi l loi cung cp c ngun in. Nu my tnh kt ni vi nhiu thit b khng c ngun in ring (Chut, DigitalCamera) th Hub nht thit phi c kh nng cung cp ngun cho cc thit b ny. TrnHub c mt b phn nh bin th cung cp dng in ti Bus v lm my tnhkhng b qu ti.

3.3.4 Cc t tnh ca USB Cc c im ca USB bao gm:

My tnh hot ng nh mt Host. C ti 127 thit b c th kt ni vo my tnh bao gm c ni trc tip

hay qua USB Hub.

Cc cp USB (USB Cable) ca tng thit b c th di ti 5m hay 30mvi Hub.

Chun USB2.x cho php truyn d liu trn Bus ti tc 480 Mbps. Mt cp USB c hai dy cung cp in v mt i dy xon truyn d

liu. Trn dy cung cp in nng, in p c th ln ti 500mA - 5V. Cc thit b s dng t in nng c cung cp in nng trc tip t

Bus. Cc Hub c th cung cp in nng cho cc thit b ni vi n t ngun inring ca chng.

Cc thit b USB c kh nng hon i nhanh, c th cm vo hay rt rakhi Bus bt k lc no.

Cc thit b USB c th t ch ng (Sleep Mode) khi my tnhchuyn sang ch Power-Saving.

Cc thit b ni vi cng USB dng cp USB truyn ti dng in hayd liu. Khi my tnh hot ng, n truy vn ti tt c cc thit b ni vo Bus v gncho mi thit b mt a ch. Qu trnh ny c gi l lit k cc thit b. My tnhcng s tm ra cch truyn d liu ca tng thit b:

Interrupt: Cc thit b nh bn phm gi lng d liu rt nh v ngton s c chnkiu Interrupt Mode.

Bulk: Cc thit b nh my in thng nhn nhng gi d liu ln, dngkiu Bulk Transfer Mode. Tng on d liu (64 Byte) c gi ti my in v c

kim tra tnh chnh xc.


60/88


Trang 60

Isochronous: Cc thit b truyn d liu theo dng Stream nh loa sdng Isochronous Mode. D liu tc thi c truyn gia thit b v my tnh vkhng c c ch sa li.

My tnh cng c th gi i cc lnh hay truy vn cc thng s vi cc giControl Packet. Khi mt thit b c my tnh lit k, my tnh s ginh ti 90% bngthng (Bandwidth) phc v cc yu cu ca cc thit b kiu Interrupt v Isochronous.Sau khi dng 90% ca 480 Mbps bng thng, my tnh s t chi cc truy nhp cabt k thit b kiu Interrupt hay Isochronous no khc. Cc Control Packet v thit bkiu Bulk Transfer s s dng khong 10% bng thng cn li.

USB phn chia bng thng thnh cc Frame v my tnh s iu khin ccFrame ny. Mi Frame cha 1.500 Byte v Frame mi c sinh ra sau mi mili giy.Trong mt Frame, cc thit b kiu Isochronous v Interrupt phn chia thnh cc khenn chng m bo c bng thng cn thit trong khi cc thit b Bulk Transfer v

Control Packet s dng phn bng thng cn li.

3.3.5 USB 2.0Chun USB2.0 xut hin vo thng T nm 2000 v c nng cp t USB1.1.

USB2.0 cung cp thm bng thng cho cc ng dng Multimedia v lu tr c tc truyn d liu ln gp 40 ln so vi USB1.1. vic chuyn t chun USB1.1 sangUSB2.0 thun tin cho c ngi s dng v nh sn xut, USB2.0 c thit k honton tng thch v lm vic c vi cp cng nh cng ni ca thit b USB nguynthu.

USB2.0 h tr ba ch truyn d liu: 1,5Mbps, 12Mbps v 480Mbps. Ngoira USB2.0 h tr cc thit b bng thng thp nh bn phm v chut cng nh ccthit b bng thng ln nh Webcam, my in, my qut nh v h thng lu tr.

3.3.6 USB 3.0USB 3.0, cn c gi l SuperSpeed USB, l giai on tin ha k tip ca

Universal Serial Bus, inarguably tiu chun giao din ph bin v thnh cng nhttng c to ra. Khi phn cng my tnh v cc thit b ngoi vi tip tc m rng

cng sut, tc , v tnh di ng, cc giao din kt ni vi h cng phi np tin tmng trong cc khu vc ny.

Xy dng s thnh cng ca USB 2.0, phin th ba ca Universal Serial Busnhm mc ch gii quyt ba tr ct ca thit k giao din:

Tc - So vi tc 12Mbps t i ca USB 1.1 v 450Mbps trung bnhca "High-Spee

Điều khiển thiết bị qua pc

Documents