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Ph.D. DISSERTATION

A STUDY ON MULTI-OCTAVE

GAN POWER AMPLIFIER USING

REACTIVELY MATCHED GAIN

CELL

리액티브 정합된 이득 셀을 사용한 다중 옥타브

GaN 전력증폭기에 관한 연구

BY

HONGJONG PARK

AUGUST 2018

SCHOOL OF ELECTRICAL ENGINEERING AND

COMPUTER SCIENCE COLLEGE OF ENGINEERING

SEOUL NATIONAL UNIVERSITY

i

Abstract

In this thesis, a study on two-stage reactively matched gain cells

are proposed to implement a high-gain multi-octave distributed

power amplifier (DPA). The analytic analysis of proposed high-gain

distributed amplifier (DA) is presented and supported with simulation

and measurement results. Also, a shared bias network using simple

microstrip line is introduced. The bias network not only enables the

use of high-gain structures in DA configuration, especially in

monolithic microwave integrated circuit (MMIC) with compound

semiconductor process, but also has advantage on layout efficiency.

To further enhance the RF performances and circuit reliability, the

layout technique with reduced thermal coupling is applied. Finally, the

high power amplifier module implemented with four MMIC dies,

thanks to its high efficiency and low junction temperature.

The DA analysis starts off with lossy m-derived configuration in

artificial transmission lines, considering the effects of the gate

coupled series capacitor used in DPA. After that, reactively matched

cell, the proposed high-gain structure, is introduced and analyzed

using Thévenin equivalent. The gain of two DPAs, conventional

cascaded DPA and proposed reactively matched distributed amplifier

ii

(RMDA) is then compared to derive the design criteria of the

reactively matched cell. The simulated results are presented to show

the potential advantage on achieving high gain performance.

The biasing of transistors is one of the common difficulties in

MMIC design with compound semiconductor process. The standard

compound semiconductor process only consists two metal layers,

making the interconnection of the bias network to be difficult.

Therefore, the most of the gain enhancement techniques for DA are

implemented using CMOS process. The shared bias network is

proposed to overcome the layout limitation. Simple microstrip lines

are used for the proposed bias network, which behave similar to the

ideal bias network: short at dc, open at radio frequency (RF). Precise

analysis with active load modulation is done to design the shared bias

network. The shared bias network is verified with the RMDA

structure, and could be employed for other topologies.

The electro-thermal effect of GaN high power amplifier is also

studied. Power amplifiers (PAs) operating in a wide bandwidth have

limited efficiency and GaN power amplifiers dissipate large amount

of dc power. Therefore, the electro-thermal effect of a multi-octave

GaN power amplifier should be considered for circuit performance

and stability. Thermal coupling reducing approach and heat spreading

approach are presented and verified by measured results.

The implemented RMDA with the compact transistor layout has

been implemented in a small die size of 10.7 mm2 and shows output

iii

powers reaching 40.3-43.9 dBm, power added efficiencies (PAEs)

of 16–27% and small signal gains of 15.3–23.2 dB. The RMDA with

the reduced thermal coupling achieves 40.6–43.4 dBm with a peak

PAE of 29% in a slightly larger die size of 13.8 mm2.

Keyword: Broadband amplifier, distributed amplifier (DA), GaN

monolithic microwave integrated circuit (MMIC), multi-octave, high

power amplifier (HPA)

Student Number: 2012-20778

iv

Contents

Abstract ....................................................................................... i

Contents ..................................................................................... iv

List of Figures ........................................................................... vi

List of Tables............................................................................ xii

Chapter 1 Introduction ............................................................. 1

1.1 Motivation .......................................................................... 1

1.2 Outline of This Thesis ....................................................... 7

Chapter 2 Multi-octive, High-Power, and High-Gain

Distributed Amplifier Structure Using Reactively Matched

Cells .................................................................................... 9

2.1 Introduction ....................................................................... 9

2.2 Previous Work and Proposed Structure for High-Gain

Distributed Power Amplifier ............................................. 12

2.3 Analysis of Gain of Proposed Reactively Matched

Distributed Amplifier ......................................................... 20

2.4 Design criteria and Detailed Design of Reactively Matched

Distributed Amplifier ......................................................... 37

2.5 Conclusion ....................................................................... 44

Chapter 3 Shared Bias Network for Proposed Reactively

Matched Distributed Amplifier Structure .......................... 45

3.1 Introduction ..................................................................... 45

v

3.2 Shared Bias Network Using Simple Microstrip Lines ..... 48

3.3 Analysis of the proposed bias network ........................... 53

3.4 Multi-section analysis and detailed design ..................... 61

3.5 Conclusion ....................................................................... 65

Chapter 4 Chip Layout with Consideration of Thermal Coupling

.......................................................................................... 66

4.1 Introduction ..................................................................... 66

4.2 Design of Standard and Staggerd Layout Technique ...... 69

4.3 Measurements of the Fabricated MMICs ........................ 76

4.4 Conclusion ....................................................................... 92

Chapter 5 High Power Amplifier Module Combining Four RMDA

MMICs ............................................................................... 93

5.1 Introduction ..................................................................... 93

5.2 Design of Power Dividing and Combining Structure ....... 95

5.3 HPA Module Fabrication and Measurement .................. 103

5.4 Conclusion ..................................................................... 110

Chapter 6 Conclusions ......................................................... 111

Bibliography ........................................................................... 112

Abstract in Korean ................................................................ 118

vi

List of Figures

Fig. 1.1. Schematic of multi-octave power amplifier structures,

(a) RMPA and (b) DA. ........................................................ 4

Fig. 1.2. Schematic of (a) a cascode DA and (b) an equivalent

FET expression of a cascode unit cell. ............................. 11

Fig. 1.3. Schematic of (a) a CSSDA and (b) an equivalent FET

expression of a CSSDA unit cell. ...................................... 13

Fig. 1.4. Schematic of a two-tier matrix DA. ......................... 17

Fig. 1.5. Schematic of a two-stage conventional cascaded

DPA. .................................................................................. 17

Fig. 1.6. Block diagram of the proposed distributed power

amplifier. ........................................................................... 19

Fig. 2.1. Schematic of a conventional distributed amplifier. .... 20

Fig. 2.2. Equivalent circuit of the input artificial transmission line.

.......................................................................................... 21

Fig. 2.3. Equivalent circuit of the transistor. ........................... 23

Fig. 2.4. A section of (a) constant-k line, (b) IATL, and (c)

OATL. ................................................................................ 27

Fig. 2.5. Distributed power amplifier using series capacitors. 29

Fig. 2.6. Block diagram of a cascade of two conventional

distributed amplifiers. ....................................................... 29

Fig. 2.7. Calculated power gain of distributed power amplifiers

with and without series capacitors. ................................... 36

vii

Fig. 2.8. Thevenin equivalent of the interstage of the reactively

matched cell. ..................................................................... 36

Fig. 2.9. Calculated power gain of distributed power amplifiers

with series capacitors. ...................................................... 38

Fig. 2.10. Calculated design criteria of the reactively matched

cell. .................................................................................... 38

Fig. 2.11. Schematic of the interstage matching network. ...... 40

Fig. 2.12. Simulated matched impedance contour. .................. 41

Fig. 2.13. Voltage reflection coefficient and effective gain of the

reactively matched cell. .................................................... 41

Fig. 2.14. Calculated gain of the proposed distributed power

amplifier compared to that of the conventional cascaded

distributed power amplifier. .............................................. 43

Fig. 3.1. Example of the dc bias network problem in the proposed

RMDA. ............................................................................... 47

Fig. 3.2. Schematic of a self-biasing unit cell. ........................ 47

Fig. 3.3. Concept of active load-pull. ...................................... 49

Fig. 3.4. (a) Schematic and (b) equivalent circuit of the two-

section reactively matched distributed amplifier. ............. 49

Fig. 3.5. Plot of (3.8). .............................................................. 52

Fig. 3.6. Calculated added admittance of the simplified bias

network in the two-section reactively matched distributed

amplifier. ........................................................................... 57

viii

Fig. 3.7. Calculated change of effective gain of the interstage of

the reactively matched cell caused by the simplified bias

network in the two-section reactively matched distributed

amplifier. ........................................................................... 60

Fig. 3.8. Detailed schematic of the proposed distributed power

amplifier. 200 Ω resistors are added to the gate bias

circuits of both drive and main stages to guarantee the

unconditional stability. ...................................................... 62

Fig. 3.9. Simulated results of the maximum magnitude value of

added admittance of the simplified bias network in the eight-

section reactively matched distributed amplifier. ............. 63

Fig. 3.10. Simulated added admittance from the bias network of

an eight-section reactively matched distributed

amplifier. ........................................................................... 64

Fig. 4.1. Measured junction temperature of a GaN HEMT device

according to dissipated power level, showing the self-

heating effect. ................................................................... 67

Fig. 4.2. Measured thermal coupling effect of a PA circuit. .... 67

Fig. 4.3. Layout of the proposed DPA MMIC with standard layout.

.......................................................................................... 70

Fig. 4.4. Layout of the proposed DPA MMIC with staggered

layout. ................................................................................ 71

Fig. 4.5. Conceptual diagram comparing the standard layout and

staggered layout in terms of thermal coupling. ................. 73

ix

Fig. 4.6. The simulated temperature distribution of die surface

of standard layout (left) and the staggered layout

(right). ............................................................................... 74

Fig. 4.7. Photograph of the fabricated reactively matched

distributed amplifier with standard layout. ....................... 77

Fig. 4.8. Photograph of the fabricated reactively matched

distributed amplifier with staggered layout. ..................... 78

Fig. 4.9. Photograph of the test fixture to test the proposed

amplifiers. .......................................................................... 79

Fig. 4.10. Block diagram of the (a) test fixture and (b) heat sink

configuration for RF characterization the fabricated

MMICs. .............................................................................. 80

Fig. 4.11. The measured temperature distribution of die surface

of standard layout (left) and the staggered layout

(right). ............................................................................... 81

Fig. 4.12. Measured and simulated performances of small-signal

S-parameters of the proposed distributed power amplifier

with the standard layout. ................................................... 82

Fig. 4.13. Measured and simulated performances of output power

and efficiency of the proposed distributed power amplifier

with the standard layout. ................................................... 83

Fig. 4.14. Measured and simulated performances of small-signal

S-parameters of the proposed distributed power amplifier

with the staggered layout. ................................................. 84

x

Fig. 4.15. Measured and simulated performances of output power

and efficiency of the proposed distributed power amplifier

with the staggered layout. ................................................. 85

Fig. 4.16. The simulated temperature distribution of die surface

of standard layout with CVD diamond thermal spreader (left)

and without CVD diamond thermal spreader (right). ........ 86

Fig. 4.17. Measured and simulated performances of small-signal

S-parameters of the proposed distributed power amplifier

with the CVD diamond thermal spreader. ......................... 87

Fig. 4.18. Measured and simulated performances of output power

and efficiency of the proposed distributed power amplifier

with the CVD diamond thermal spreader. ......................... 88

Fig. 5.1. Block diagram of the proposed high power amplifier

module. .............................................................................. 94

Fig. 5.2. The proposed microstrip-to-coaxial 1:2 divider and (b)

the conventional microstrip-to-coaxial divider. .............. 96

Fig. 5.3. Cross-sectional diagram of (a) the proposed

microstrip-to-coaxial 1:2 divider and (b) the conventional

microstrip-to-coaxial divider. ......................................... 97

Fig. 5.4. Simulated electric field of (a) the proposed microstrip-

to-coaxial 1:2 divider and (b) the conventional microstrip-

to-coaxial divider. ............................................................ 98

Fig. 5.5. Simulated S-parameter of (a) the proposed

microstrip-to-coaxial 1:2 divider and (b) the conventional

microstrip-to-coaxial divider. ......................................... 99

xi

Fig. 5.6. Schematic of 50-Ω-to-100-Ω Wilkinson

combiner. ......................................................................... 101

Fig. 5.7. (a) Layout of the proposed Wilkinson combiner and (b)

simulated S-parameter of the proposed Wilkinson combiner.

........................................................................................ 102

Fig. 5.8. Sections of half module: (a) transition section, (b)

Wilkinson section, (c) MMIC section, (d) Wilkinson section

and (e) transition section. ............................................... 104

Fig. 5.9. (a) Photograph and (b) measured insertion loss of the

fabricated 1:2 microstrip-to-coaxial transition. ............ 105

Fig. 5.10. (a) Photograph and (b) measured insertion loss of the

fabricated total 1:4 power divider. .................................. 105

Fig. 5.11. Photograph of the fabricated HPA half-module. ... 106

Fig. 5.12. Photograph of the fabricated HPA module. ........... 107

Fig. 5.13. Photograph of the mersurement set-up of HPA

module. ............................................................................ 107

Fig. 5.14. Measured large-signal performances of the fabricated

HPA. ................................................................................ 108

Fig. 5.15. Measured large-signal performances of the fabricated

HPA in 18 GHz. ............................................................... 109

xii

List of Tables

TABLE 1.1. Si, GaAs, SiC, and GaN Material Properties .......... 2

TABLE 1.2. Parameters for calculating the equivalent

transconductance of the CSSDA unit cell ......................... 14

TABLE 2.1. Parameters values of transistors under class-AB

bias condition .................................................................... 33

TABLE 2.2. Designed values of components of interstage

matching network of reactively matched cell ................... 40

TABLE 4.1. Performance comparison table of GaN broadband

PAs .................................................................................... 91

１

Chapter 1

Introduction

1.1. Motivation

From the beginning of the last century, electronic warfare (EW)

systems have contributed to protecting friendly forces and

weakening enemy weapons. The role of electronic warfare will

increase even more with the development of technology and the

change of battlefield environment. With the advent of network-

centric warfare (NCW), it is essential to secure the electromagnetic

spectrum for the acquirement of information assets and command and

control (C2). Also, cyber electronic warfare (CEW) technology is in

development to connect to a wireless network to perform operational

activities.

To meet the battlefield needs, the development of high-power

transmitter for the electronic attack is important. Conventional

traveling wave tube amplifiers (TWTAs) have many disadvantages:

２

bulky and heavy, long heat-up and cool-down time, and short

lifetime. In addition, digital signal processing and wide bandwidth

operation cannot be incorporated with the TWTA. Therefore, the

solid-state power amplifiers (SSPAs) based on semiconductor

technology, which can overcome many drawbacks of TWTA, have

been actively developed to replace the TWTA for electronic warfare

applications.

Table 1.1 compares the physical properties of semiconductor

devices for fabricating SSPA [1]-[2]. Since GaN has wide energy

TABLE 1.1

Si, GaAs, SiC, and GaN Material Properties

Property Si GaAs SiC GaN

Bandgap (eV) 1.11 1.43 3.2 3.4

Breakdown

Field (MV/cm) 0.6 0.65 3.5 3.5

Electron Mobility

(Cm2/V-sec)

1350 6000 800 1000

Saturated velocity

(107cm/sec)

1 1 2 1.5

３

bandgap, high breakdown field, high electron mobility and high

saturation velocity, GaN HEMT devices have high power density,

high operating voltage level and high-frequency characteristics.

Therefore, SSPAs based on GaN HEMT monolithic microwave

integrated circuit (MMIC) process are most suitable as a substitute

for TWTAs.

Design of a wideband power amplifier (PA) is a challenging task.

High power performance is associated with large sized transistors,

but large sized transistor has high Q-factor, resulting in narrow

bandwidth. In particular, EW system typically requires PA of more

than 10 watts of output power with linear power gain of 15 dB, in

multi-octave bandwidth. Efficiency is also a feature of importance,

at least more than 10% in terms of the power added efficiency (PAE)

is necessary. Therefore, every aspect of the performance of the PA

should be carefully analyzed along with achieving a multi-octave

bandwidth. Possible circuit topologies for wideband high power

amplifier (HPA) are reactively matched power amplifier (RMPA) and

distributed amplifier (DA), shown in Fig. 1.1.

In the RMPA, the strategy of lowering the Q-factor of each

transistor is performed. Lossy components and negative feedback is

typically employed. However, these approaches adds unnecessary

RF signal loss, which leads to reduced gain and efficiency [3]-[5].

In addition, the size of the RMPA is larger than DA due to the output

matching network and power combining circuit. One of the most

４

(a)

(b)

Fig. 1.1. Schematic of multi-octave power amplifier structures, (a)

RMPA and (b) DA.

RFin

RFout

input matching

network

output matching

network

Lossy match

RFin

RFout

input artificial transmission line

output artificial transmission line

５

recent work employed the non-Foster matching concept to RMPA

[6]-[7]. The authors called their topology as negative impedance

matched power amplifier (NMPA), and managed to reduce the Q-

factor without lossy elements. However, the instability of the non-

Foster circuit still limits RF performance of the PA.

DA, often referred to the traveling-wave amplifier, is most

suitable topology for any type of broadband amplifiers. The input and

output capacitances of the transistor are absorbed into the artificial

transmission lines (ATLs), thus bandwidth limitation come from

transistor Q-factor can be overcome. DA had not been considered as

a power amplifier for a long time, but non-uniform distributed power

amplifier (NDPA) theory demonstrated the possibility of the

distributed power amplifiers (DPAs) [8]. Nevertheless, DPA suffers

low gain and severe gain roll-off at high frequencies.

In this thesis, a topology for high-gain DPA is introduced. The

proposed structure is called reactively matched distributed amplifier

(RMDA), because the reactive matching concept is used to enhance

the gain of DPA. The practical layout difficulty of dc bias network

aroused in complicated circuit topology is also studied. The shared

bias network is proposed to deal with the layout problem. Also, the

staggered layout technique is introduced to reduce the thermal

coupling of the transistors, further improving RF performances. A

high power amplifier module combining four MMICs is implemented

for higher output power, thanks to the high efficiency and lower

６

junction temperature of the fabricated MMICs.

７

1.2. Outline of This Thesis

This thesis is composed of four sections. In the first section,

chapter 2, the reactive matching technique for DPA is presented. The

chapter starts off with the analysis of the limitation of the gain

performance in the conventional DPA. The reactively matching

technique is introduced, and the gain of the reactively matched cell is

analyzed to derive the design criteria. The detailed design of

reactively matched cell is presented at last, and the gain of RMDA is

compared to that of the conventional DPA.

In chapter 3, the shared bias network is introduced. The shared

bias network consists of simple microstrip lines. The principle of

operation is analyzed with active load-pull analysis. The added

admittances caused by adding bias network is calculated. To meet

the condition that the bias network should not affect the RF

performance, real and imaginary parts of the added admittance need

to be zero. The case of non-zero added admittance is also analyzed

to clearly show the effect of the shared bias network.

Chapter 4 focuses on the junction temperature and the RF

performance of the RMDA. The efficiency limitation of the broadband

PA results in large amount of power dissipated into heat. The junction

temperature should be considered not only for circuit reliability but

８

also for RF performance. The staggered layout technique is proposed

to reduce the thermal coupling of each transistor in MMIC. Precisely

designed thermal carrier using CVD diamond material is applied to

MMIC with standard layout, and compared to the MMIC with

staggered layout.

Finally the thesis ends with conclusions in chapter 5 which

summarizes the RMDA design techniques.

９

Chapter 2

Multi-Octave, High-power, and High-

Gain Distributed Amplifier Structure Using

Reactively Matched Cells

2.1. Introduction

Solid-state wideband HPAs are essential component for

broadband applications such as EW systems. DAs and RMPAs have

been mainly used as multi-octave PAs. In the RMPA, lossy

components are typically employed for a high return loss and low Q-

factor at the interstage, which leads to the decreased efficiency. In

addition, the size of the RMPA is large due to output matching

network and power combining circuit. Therefore, the HPAs designed

by the methodology of RMPA typically shows low power density [1],

[9]. The non-foster matching concept has also been applied to the

１０

RMPA, but the RF performances are still in limited level [6]-[7].

The DA is the most suitable circuit topology for a broadband

amplifier because the input and output capacitances of the transistor

are absorbed into the artificial transmission lines (ATLs). Therefore,

the bandwidth limitation from Bode-Fano criteria can be overcome

[10]-[11]. However, DA has two disadvantages as PA: low power

and low gain. Output power of conventionally-configured DA is

limited, because the output port of each transistor cells doesn't look

an optimum power load impedance (Ropt). To solve the output power

problem, the NDPA theory was presented [8]. By tapering the

characteristic impedances of each section's drain lines, each

transistor look load impedance close to Ropt, and the output power

could be increased with sacrificing a little amount of output return

loss. The NDPA theory had become a standard topology for ultra-

wideband DPAs.

On the other hand, there are many previous efforts to overcome

the low gain characteristic of DA, yet none of any were decisive. Low

gain characteristic of DA implies low overall gain and gain roll-off at

high frequencies. To solve the low gain problem of the DA structure,

various topologies have been proposed, such as the matrix DA [12]-

[13], the cascaded single stage DA (CSSDA) [14], and the cascode

DA [15]-[17]. However, it is challenging to design an HPA over 10

W with previously proposed structures at 6-18 GHz. Thus,

enhancing gain of DPA have been studied with interest by many

１１

researchers continuously until nowadays.

(a)

(b)

Fig. 1.2. Schematic of (a) a cascode DA and (b) an equivalent FET

expression of a cascode unit cell.

RFin

RFout

2×Vdd

Cds2

Cgs2

Cds1

Cgs1

gm2

gm1

Cds2

Cgs1

Gm,cascode

１２

2.2. Previous Work and Proposed Structure for High-

Gain Distributed Power Amplifier

Previous works for high-gain DPA can be classified as two types:

multi-stage DA approaches and unit cell modification approaches.

First of all, the previous unit cell modification approach mainly

includes cascode DA and CSSDA.

In the cascode DA, cascode cells replace the common-source

transistors in the unit cells (Fig. 1.2). Cascode cells are superior to

the common-source not only for the gain but also for the output

power. However, Cascode cells are difficult to use in GaN monolithic

microwave integrated circuits (MMICs) due to the high operating

voltage. Also, the DA using cascode cells has relatively small stability

margin and high process sensitivity, which leads to lower yields when

a large number of circuits are needed for a system such as EW

applications [15]-[17].

The latter, CSSDA, is a DA in which the common-source gain

cell of DA is replaced by a cascade of single-section DA [14].

CSSDA has higher gain to that of DA, since it utilized cascade

configuration so that the gain is multiplied. However, CSSDA suffers

large mismatches at interstage, thus gain should be reduced for

１３

(a)

(b)

Fig. 1.3. Schematic of (a) a CSSDA and (b) an equivalent FET

expression of a CSSDA unit cell.

RFin

RFout

Cds2

Cgs1

Gm,CSSDA

Zint

Cgs1

gm1

gm2

Cds2

１４

bandwidth with gain-bandwidth tradeoff. CSSDA also has the

disadvantage of gain that comes from interstage termination

resistances. More obviously, the series capacitor technique, which

will be explained next chapter, has to be applied to the main stage

TABLE 1.2

Parameters for calculating the equivalent transconductance of the

CSSDA unit cell

parameter description

gm1 transconductance of the first stage

transistor

gm2 transconductance of the second

stage transistor

Zint synthetic impedance of interstage

artificial transmission line

ω radial frequency

ωg1 gate radian cutoff frequency of the

first stage transistor

ωc radian cutoff frequency of the

artificial transmission lines

１５

transistor in CSSDA design for efficient bandwidth. The CSSDA gain

cell of Fig. 1.3(a) can be simplified into an equivalent field effective

transistor (FET) as Fig. 1.3(b) with effective transconductance

Gm,CSSDA. With the parameter given by Table 1.2, Gm,CSSDA can be

derived as follows:

1 2 2int 1

, 2 2

1

1exp ( )

2

2 1 1

m m gd

m CSSDA

cg

g g Z A A

G

(1.1)

Ad1 is drain attenuation per section in first stage and Ag2 is the

gate attenuation per section in second stage. The term of Ag2 is

affected by gate series capacitor of the main stage, and it dramatically

reduces the gain. Therefore, CSSDA exhibits only small amount of

gain improved, and does not overcome high-frequency gain roll-off.

The gain limitation of main stage series capacitor will be analytically

described later.

The multi-stage approaches are generally matrix DA and

conventional multi-stage DPA. The matrix DA is a simple and useful

technique for high gain DA. In the topology, FET configuration is

two-dimensional, looks analogous to matrix (Fig. 1.4). Thanks to

using interstage ATLs, the amplifier can be multi-stage without

１６

many modifications on design of DA [12]-[13]. However, the

biggest obstacle that prevents matrix DA for DPA is interstage ATLs.

The nodes of interstage ATLs which connects two transistors look

large capacitance. Especially for DPAs, The value of drain

capacitance and that of the gate capacitances are both large, so the

added amount become too large to be absorbed into ATL. Therefore,

matrix DA is not suitable for DPA topology.

The multi-stage DPA is a fairly simple way to enhance gain. By

cascading conventional DAs with multi-stage, the gain of total circuit

becomes multiplication of the gain of cascaded DAs (Fig. 1.5).

Typically for EW applications in 6-18 GHz frequency, the multi-

stage DPA is configured as two-stage, the first stage with a higher

gain and the last stage with a higher output power. Though this

approach still suffers limited gain and high frequency gain roll-off, it

is commonly used for GaN DPA MMICs. Every reported works for

6-18 GHz GaN DPA MMIC are designed by conventional cascaded

DA topology [18]-[20].

The proposed topology utilizes reactively matched gain cell to

enhance gain efficiently. The concept of interstage impedance

matching of RMPA is employed to unit cell design of DA. The

proposed design concept belongs to the unit cell modification

approach. Two-stage reactively matched cells between the input

artificial transmission line (IATL) and the output artificial

transmission line (OATL) substitute common source stages. A

１７

Fig. 1.4. Schematic of a two-tier matrix DA.

Fig. 1.5. Schematic of a two-stage conventional cascaded DPA.

RFin

RFout

Cds1

Cds1

Cds1

Cds1

Cgs2

Cgs2

Cgs2

Cgs2

RFin

RFout

１８

simple block diagram of the proposed DPA is shown in Fig. 1.6.

The proposed DPA is designed using a commercial 0.25-μm

GaN HEMT foundry process by WIN Semiconductors Corporation.

The process provides two metal layers, a Si3N4 insulating film for

metal-insulator-metal capacitor, TaN thin film resistor, and air-

bridge for passive component design. The HEMT device shows a

cut-off frequency (fT) of 30.1 GHz, an fmax of 74.6 GHz, and a

transconductance of 227 mS/mm.

To achieve output power higher than 10 W in the 6-18 GHz

bands, the size of the main stage transistor is determined to be

6×125 μm, and the number of sections is determined to be eight.

The transistor with a size of 6×125 μm has a maximum small-

signal gain of 12 dB at 18 GHz and a maximum output power of 34

dBm with 30 V bias based on the load-pull analysis. To drive power

with high efficiency at 18 GHz, a 4×75 μm-sized transistor, which

has a maximum output power of 30 dBm with an input power of 22

dBm, is used as the drive stage. The interstage reactive matching

network is employed in each gain cell. The OATL is designed using

an NDPA theory to enhance the output power. The circuit RF

performance analysis starts off with schematic-based simulation,

and the final layout design is optimized through the electromagnetic

simulations using ADS Momentum.

１９

Fig. 1.6. Block diagram of the proposed distributed power amplifier.

２０

2.3. Analysis of Gain of Proposed Reactively Matched

Distributed Amplifier

The gain of the conventional DA and the two-stage cascaded

conventional DPA is calculated to compare to that of RMPA. To

analyze the gain of DA, the closed-form gain expression of a

conventional DA (Fig. 2.1) is calculated using the simplified circuit

as derived in previous works [16]-[17].

Fig. 2.1. Schematic of a conventional distributed amplifier.

RFin

RFoutZout

Zin

Ld/2 L

dL

d

Lg

Lg

Lg/2

Ld/2

Lg/2

Ld/2

Lg/2

Ld/2

Lg/2

1 2 3 n

Vg1

Vg2

Vg3

Vgn

Ig1

Ig2

Ig3

Ign

Id1

Id2

Id3

Idn

Iout

２１

The analysis of the gain of DA is started off with calculating the

current and voltage of each node, as shown in Fig. 2.1 [21]-[22].

First of all, to calculate the gate voltage of k-th section Vgk, the IATL

is simplified as Fig. 2.2. First of all, the current of the gate of k-th

section Igk can be derived as

2 12 gk

ingkI I e

, (2.1)

where θg = Ag + jΦg is the propagation constant of the IATL. On

the other hand, using the image impedance equation of IATL, Vgk is

derived as

Fig. 2.2. Equivalent circuit of the input artificial transmission line.

2Ri

2Ri

2Ri

2Ri

2Ri

2Ri

Cgs

/2 Cgs

/2 Cgs

/2 Cgs

/2 Cgs

/2 Cgs

/2

Lgs

/2 Lgs

/2 Lgs

/2 Lgs

/2 Lgs

/2 Lgs

/2Ig1Vg1 Ig2Vg2 IgnVgn

Zin

Vin

Iin

２２

2

1

g g

ggk gk gk

c

L CV I Z I

, (2.2)

where ω is radian frequency and ωc = 2πfc = 2/(LgCgs)1/2 =

2/(LdCds)1/2 is the radian cutoff frequency of the ATLs. Also, the

relation between input current Iin and the input voltage Vin can be

expressed as

2

1

1

inin in

gTg g c

VI V

ZL C

. (2.3)

From (2.1), (2.2), and (2.3), Vgk is expressed according to Vin,

2 12

21

gk

ingk

c

eV V

. (2.4)

To derive the drain current of k-th section, the voltage across

the k-th section transistor, Vck is calculated. In this analysis, the

transistor is assumed to be unilateral, because the gate-drain

２３

capacitance Cgd can be absorbed into Cgs and Cds. Also, the instability

from Cgd is simplified equivalent circuit of the transistor is reduced

due to the gate/drain termination of the ATLs. Vck is derived as

1tan

2

1

11

gjgs

ck gk gkgsi

g

j C eV V V

R j C

, (2.5)

where ωg = 1/RiCgs is the gate radian cutoff frequency.

The current of the output terminal, Iout is summation of the

forward-direction drain current of the k-th transistor, derived as

Fig. 2.3. Equivalent circuit of the transistor.

２４

1 2

1

d dn n k

out dkk

I I e

, (2.6)

where θd = Ad + jΦd is the propagation constant of the IATL. Using

(2.4), (2.5), and Ids equation in Fig. 2.3, (2.6) is developed to follows:

1

12

1

1tan

2

2 2 1

12

2 1 1

d d

g gd dgd

n n kjmout ck

k

jn j n km in

kg c

I g e e V e

g V e e e ee

. (2.7)

Φd and Φg are constrained to be equal to IATL and OATL to have

the same cutoff frequency and to have the highest Iout. Letting Φd =

Φg = Φ, (2.7) is further developed as

1 1tan

2

2 2 12 1 1

gg d dgd

A Aj nAj jn n k A Am inout

kg c

g V e e e e eI e

２５

1tan

2

2 2

sinh2

1sinh2 1 1

2

gg d

jj jn g nd A Am in

gg c d

nA A

g V e e ee

A A

.

(2.8)

The input power and the power delivered to the load of DA are given

by

2 2

21re 1

22in in g

cinggT

V V LP

CZ

and (2.9)

2 2

2re 1

2 2out out d

cout dTd

I I LP Z

C

, (2.10)

respectively. Therefore, the voltage gain can be calculated as

20

22 2

sinh2

12 1 1 sinh

2

g dn A A

m gg od d

DA

c g gk k d

ng Z Z A A e

A

x x A A

, (2.11)

２６

where xk = ω/ωc is the normalized frequency and Z0g and Z0d are the

characteristic impedance of IATL and OATL, respectively.

To quantify Ad and Ad, propagation function analysis of a

constant-k line is performed [23]. From a section of a constant-k

line shown in Fig. 2.11(a), the propagation function can be

determined from following relation

12

cosh 12

Z

Z , (2.12)

where θ is the propagation function of the line. θ can be expressed

as θ = A + jΦ, where A and Φ are respectively the attenuation

and phase shift per section. From (2.12), Φ can be canceled out, and

A is given as

2 2

1 1

2 2

2 2

re 1 im 12 2

1cosh sinh

Z Z

Z Z

A A

. (2.13)

when A

２７

1

2

2

1

2

im 12

1 re 12

Z

ZA

Z

Z

. (2.14)

Evaluating (2.14) for the specific circuits shown in Fig. 2.4(b) and

Fig. 2.4(c), the closed-form expressions for attenuation on IATL and

OATL is obtained:

(a) (b) (c)

Fig. 2.4. A section of (a) constant-k line, (b) IATL, and (c) OATL.

Z1/2 Z

1/2

Z2

Lg/2 L

g/2

Ri

Cgs

Ld/2 L

d/2

Rds

Cds

２８

2

221 1

c g kg

c g k

xA

x

and (2.15)

21

cd

d

k

Ax

. (2.16)

where ωd = 1/RdsCds is the drain radian cutoff frequency.

When using the DA as a PA, it is required to use large transistors

to obtain sufficient output power. However, the cut-off frequency of

the IATL is reduced with the increase of the transistor size, due to

the increase in the gate-source capacitance (Cgs). Therefore, to

ensure the multi-octave operation bandwidth, design techniques

such as series gate capacitor have been widely used, as shown in Fig.

2.5 [24]-[25]. However, the gain-bandwidth product remains

constant with the series capacitor technique, implying that there

should be significant gain degrade to cover a wide bandwidth.

The gain of two-stage cascaded DPA using series capacitors is

calculated to show the difference in gain between the conventional

cascaded DA and the RMDA. If a series capacitance of Cs = qCgs is

used, gate effective gate capacitance, the capacitance seen from the

input of the transistor, becomes

２９

Fig. 2.5. Distributed power amplifier using series capacitors.

Fig. 2.6. Block diagram of a cascade of two conventional distributed

amplifiers.

RFin

RFoutC

sC

sC

sC

s

Cgs

Cgs

Cgs

Cgs

３０

1gs gsq

C Cq

. (2.17)

As a result of decrease in the effective gate capacitance, the cut-

off frequency is increased by the factor of (1+q)/q. On the other hand,

the voltage across the gate capacitance is decreased by the factor of

q/(1+q) due to the voltage dividing,

1m mq

g gq

. (2.18)

Therefore, the formula for the DA gain using gate series capacitor is

20 0

22 2

sinh2

12 1 1 sinh

2

gdn A A

m gg d d

DA

c g gk k d

ng Z Z A A e

A

x x A A

, (2.19)

where

2 2c

g gs d dsL C L C

, (2.20)

1g

gsiRC

, (2.21)

３１

2

221 1

c g kg

c g k

xA

x

, and (2.22)

kc

x

. (2.23)

The altered terms by the series capacitance are denoted with

prime symbols. In the lower frequency sub-band, where xk ≤ 0.4,

A'DA is degraded into [q/(1+q)]A, namely the low-frequency gain

reduction ratio. The gain of the cascade of two DAs, each using the

series capacitors, can be expressed as

1 22

1 21 2

2 22 2 2

1 2

1 21 2

1 21 2

4

exp 2

1 1 1

sinh 2 sinh 2

sinh 1 2 sinh 1 2

outin intm mstage

g gd d

c cg gk k k

g gd d

g gd d

g g Z Z ZA

n A A A A

x x x

n A A n A A

A A A A

.(2.24)

The gain of the two-stage conventional cascaded DPA is

evaluated with the selected transistors and circuit component values

３２

from the available technology. The cascaded DA circuit is composed

of two eight-section DAs, DA1 and DA2, as shown in Fig. 2.6. To

determine the size of the transistors, we have set the bias of the

transistors to optimize the RF performance and then modified the

transistor size to present the required Cgs for DA operation. Under

class-AB bias chosen for PAE consideration, Cgs, Cds, Ri, and Rds

values of transistors with a size of 4×75 μm are 0.6 pF, 0.13 pF, 4

Ω, and 300 Ω, respectively. The parameter values for 6×125 μm

transistors are 1.6 pF, 0.3 pF, 4 Ω, and 120 Ω. Z0g and Z0d are set

to be 50 Ω. These transistor parameter values are presented in

Table 2.1. For a 50 Ω IATL with a 20 GHz cut-off frequency, series

capacitance of 0.68 pF and 0.40 pF should be used. Whereas the

bandwidth of DAs increases to 20 GHz with series capacitors, the

low-frequency gain reduction ratio of DA1 is 0.53 while that of DA2

is 0.20. Gain of DA1 and DA2 with and without using the series

capacitor technique is numerically evaluated in terms of frequency,

as shown in Fig. 2.7. In terms of power gain, the gain reduction can

be as much as 19 dB for the conventional two-stage cascade design.

The close-form equation of gain of RMDA is also derived to

compare the gain with the conventional cascaded DA [26]-[27].

RMDA can potentially achieve similar or higher gain than the

cascaded DA due to the high gain of the reactively matched cells that

replaces the common source transistors. The reactively matched cell

consists of two transistors and an interstage matching network as

３３

TABLE 2.1

Parameters values of transistors under class-AB bias condition

parameter description Value

Cgs1 Gate-source capacitance of

a 4×75 μm transistor 0.6 pF

Cds1 Drain-source capacitance of

a 4×75 μm transistor 0.13 pF

Ri1 Gate-source capacitance of

a 4×75 μm transistor 4 Ω

Rds1 Input resistance of

a 4×75 μm transistor 300 Ω

Cgs2 Gate-source capacitance of

a 6×125 μm transistor 1.6 pF

Cds2 Drain-source capacitance of

a 6×125 μm transistor 0.3 pF

Ri2 Gate-source capacitance of

a 6×125 μm transistor 4 Ω

Rds2 Input resistance of

a 6×125 μm transistor 120 Ω

３４

shown in Fig. 1.6. To analyze the reactively matched cell, Thevenin

equivalent circuit of the interstage of the reactively matched cell is

shown in Fig. 2.8. Assuming that the interstage matching network is

lossless, power delivered to the load can be expressed as

2 2

1

11

8L ds dsP I R

, whereas (2.25)

2

2

2

12

gk

Lin

VP

R

. (2.26)

From (2.25) and (2.26),

2

22 1 1

11

2 ingk ds dsV I R R . (2.27)

Therefore, the equivalent transconductance of the reactively

matched cell, namely Gm, defined by Ids2=GmVck1, can be found as

３５

21 2 21

2

2

1

2 1

m m indsm

g

g g R RG

. (2.28)

Define Ais, the effective gain of the interstage matching network as

21isA . (2.28)

Finally, replacement of gm in (2.19) with Gm in (2.28) results in the

explicit formula of gain of RMDA with respect to Ais,

1 2 21

1 2

2 22 2 2

1 2

1 2

1 2

4

exp 2

1 1 1

sinh 2

sinh 1 2

outinm m indsRMDA

g d

c cg gk k k

g d

g d

g g Z Z R RA

n A A

x x x

n A A

A A

. (2.29)

３６

Fig. 2.7. Calculated power gain of distributed power amplifiers with

and without series capacitors.

Fig. 2.8. Thevenin equivalent of the interstage of the reactively

matched cell.

Rds1

Ids1

Rds1

ap1

bp1

Cds1

interstage

matching

network

bp2

Vgk2 V

ck2

Rin2

Cgs2

３７

2.4. Design criteria and Detailed Design of Reactively

Matched Distributed Amplifier

The ratio of ARMDA and A2-stage in (2.29) and (2.24) provides the

design criteria for the reactively matched cell to achieve the gain of

RMDA to be higher than that of the cascade of the conventional DAs.

The ratio ARMDA / A2-stage is given by

22

2 22 1

22

1 22

22

1 22

1 21 2

1 21 2

11

exp 2

sinh 21

sinh 1 21

sinh 1 2 sinh 1 2

sinh 2 sinh 2

kRMDA

stageg d

c g dg k

g dc g k

g gd d

g gd d

xA q

A q n A A

n A Ax

A Ax

A A A A

n A A n A A

isA

.(2.30)

In the lower frequency sub-band, where xk ≤ 0.4, xk2 is zero

and (2.30) is approximated as [(1+q2)/q2]Ais. In the higher

３８

Fig. 2.9. Calculated power gain of distributed power amplifiers with

series capacitors.

Fig. 2.10. Calculated design criteria of the reactively matched cell.

３９

frequency sub-band, (2.30) is a monotonically decreasing function.

Therefore, the condition of Ais ≥ [(1+q2)/q2] is the interstage

matching network design criteria for RMDA to achieve higher gain

than that of conventional cascaded DAs. Fig. 2.9 compares the

calculated gain of an ideal RMDA (without any interstage mismatch)

with the cascaded DA, using the parameters defined earlier.

To make the gain of the proposed DA larger than that of the

conventional cascaded DA, there are the minimum effective gain and

the maximum voltage reflection conditions, defined by ARMDA / A2-stage

≥ 1 in (2.30). The minimum effective gain and the maximum voltage

reflection for the reactively matched cell is calculated in Fig. 2.10. It

is observed that as long as the voltage reflection coefficient is less

than 0.85, the gain of the RMDA can be higher than the cascaded DA.

Following paragraphs show the detailed design of reactively matched

cell to meet the design criteria.

Unlike the case of a general RMPA, where four or more

transistors are connected in parallel, the reactively matched cell is

composed of one drive transistor and one main transistor. Thus, gate

port of the main transistor in reactively matched cell does not present

excessively small impedance. Therefore, it is possible to use reactive

lossless matching to cover a multi-octave bandwidth in RMDA.

The schematic of the reactively matched cell is shown in Fig.

2.11. The specific values of designed components are presented in

Table 2.2. With the chosen values, the mismatch was minimized in 7

４０

Fig. 2.11. Schematic of the interstage matching network.

TABLE 2.2

Designed values of components of interstage matching network of

reactively matched cell

component Value

Ls 1.2 nH

Cblk1 8.3 pF

Cp 0.4 pF

Cblk2 8.3 pF

width of TLs 80 μm

length of TLs 200 μm

width of TLp 10 μm

length of TLp 280 μm

４１

Fig. 2.12. Simulated matched impedance contour.

Fig. 2.13. Voltage reflection coefficient and effective gain of the

reactively matched cell.

４２

GHz, 13 GHz, and 18 GHz for 6-18 GHz operation frequency band,

without any lossy matching technique or negative feedback. Za and

Zb, the impedance looked at both direction of node N in Fig. 2.11, is

simulated through ADS simulator with provided process design kit to

show the impedance matching at interstage of reactively matched cell.

Simulated Z*a and Zb are shown in Fig. 2.12. It can be observed that

the impedance matching is optimized in 13 GHz and 18GHz,

intentionally mismatching 7 GHz to have higher effective gain in

higher frequencies to deal with the gain roll-off. The voltage

reflection coefficient Γ and the effective gain Ais are also simulated

to compare to the design criteria, as shown in Fig. 2.13. It is evident

that proposed RMDA structure using the reactively matched cell

exhibits superior gain performance than the conventional cascaded

DA. The closed-form expression of the gain of RMDA (2.29) is

calculated using the simulated result of the reactively matched cell

(Fig. 2.14). Not only is the problem of the overall gain reduction

mitigated, but the gain roll-off at higher frequency edge is also

avoided due to the reactive matching technique.

４３

Fig. 2.14. Calculated gain of the proposed distributed power amplifier

compared to that of the conventional cascaded distributed power

amplifier.

４４

2.5. Conclusion

In this chapter, the concept of RMDA is proposed. Through

analytic analysis and numerical computation, the limitation of the

small-signal gain of the conventional cascaded DPA is presented.

The component that reduces the gain the most is specified, which is

the series capacitor of main stage transistor. To overcome the gain

limit, the reactively matched cell is proposed as a unit gain cell of the

distributed amplifier. Thanks to the reactively matched cell, IATL

composed of the main transistor can be removed, and the gain

reduction by the series capacitor of the main transistor is abolished.

The proposed reactively matched cell also has the benefit of having

two transistors only, thus interstage matching is done without any

lossy elements or negative feedback. Comparing the explicit formula

of conventional cascaded DPA and the proposed RMDA, the design

criteria of the RMDA is obtained. The detailed design of RMDA is

performed, and the simulated results clearly exhibits higher gain than

that of the conventional cascaded DPA, which implies that the

theoretical analysis is verified by the circuit simulation.

４５

Chapter 3

Shared Bias Network for Proposed

Reactively Matched Distributed Amplifier

Structure

3.1. Introduction

In this chapter, the concept of shared bias network is proposed.

In the active circuit, every transistor needs dc bias for proper

operation. In the RF circuit, the bias circuit should be carefully

designed to feed dc current whilst decoupling RF signal. To achieve

RF decoupling, various techniques are proposed. Connecting a low

pass filter, RF bypass capacitor with a quarter-wave transmission

line, and RF choke inductor are common example of the biasing

circuits.

For the RFICs and MMICs, there are some limitations for biasing

４６

networks. Biasing networks should be compact to save the size of

total circuit. Especially MMIC with compound semiconductor

technology, there are only two metallization layers. In fact, those two

metal layers are for air-bridge for RF signal: two metal layers should

be merged to feed high RF current in PA circuit. When designing a

circuit with complex topologies, it is almost impossible to feed dc bias

to "inside" transistor (see dotted red box shown in Fig. 3.1).

To overcome the biasing problem, a self-biasing scheme using

series feedback is proposed [28]-[29]. The self-biasing scheme

uses a series feedback resistor and a series feedback capacitor.

Voltage drop across the series feedback resistor produces gate-

source voltage. Series feedback capacitor provides short impedance

at RF signal, thus RF signal loss could be minimized. The schematic

of self-biasing is shown in Fig. 3.2. Although this technique is

beneficial for biasing the transistors, the voltage drop across the

resistor generates substantial dc power dissipation. Therefore, RF

performance degradation is unavoidable.

In this chapter, a compact shared DC bias network is proposed to

apply a single VDD bias to all transistors in the drive stage of RMDAs.

The proposed bias network is also applicable to any type of

distributed amplifiers or parallel power combining PAs.

４７

Fig. 3.1. Example of the dc bias network problem in the proposed

RMDA.

Fig. 3.2. Schematic of a self-biasing unit cell.

gatedrain

４８

3.2. Shared Bias Network Using Simple Microstrip

Lines

Given that the bias network should not affect the RF performance,

the design of the bias network had been focused on making RF open

circuit. However, in the presence of more than one RF signals, the

impedance is altered with the other RF signal. The active load-pull

concept explains the effect, as shown in Fig. 3.3. The impedance seen

at the junction node Z1 is expressed as

11

2

1I

Z RI

. (3.1)

Using this equation, the impedance in RF frequencies could be

maximized for bias network. In this thesis, a bias network consists of

simple microstrip lines are designed through active load-pull concept.

The two-section RMDA with the interstage drain bias line is

shown in Fig. 3.4. To understand the influence of the phase of the

bias line on the RF characteristics of the circuit, the case of a two-

section RMDA is briefly analyzed. Let the phase delay of a section of

４９

Fig. 3.3. Concept of active load-pull.

(a) (b)

Fig. 3.4. (a) Schematic and (b) equivalent circuit of the two-section

reactively matched distributed amplifier.

Gen 1 Gen 2

R

I1

I2

V

Z1

IN

OUT

Qd1

Qd2

Qm1

Qm2

φ θ

X1

X2

I1

I2

I11

I12

Y1

Y2

YL

YL

θ

X1

X2

I1

I2

I11

I12

Y1

Y2

YL

YL

５０

the bias line be θ, and the phase delay of a section of the IATL be

φ. In such case, I11 and I2 become

11 1jI kI e , and (3.2)

2 1jI I e , if (3.3)

1 2I I . (3.4)

Using the active load-pull equation in (3.1), Y2, the admittance

at node X2, can be expressed as

22

11 2

(1 )L LI

Y Y A jB YI I

, (3.5)

where

2

2

cos( )

1 cos( )

k kA

k k

and (3.6)

2

sin( )

1 cos( )

kB

k k

. (3.7)

To make Y2 to be identical to YL, which is in the case of the ideal

５１

bias network, the conditions A = 0 and B = 0 should be satisfied.

Therefore, k = 0 and φ = θ could be a solution.

In terms of physical meaning, k means the ratio of amount of

leakage RF current to that of incident RF current. Therefore, the

value k cannot be zero, but has to be minimized. On the other hand,

φ is given as a phase delay of a section of IATL, θ is possibly

designed to be equal to φ.

With the condition of φ = θ, (3.7) is zero regardless of k. The

added susceptance value (imaginary of Y2−YL) is given as BYL, and

becomes zero with the condition. The analysis shows a design criteria

for the length of the microstrip line of the proposed bias network. On

the other hand, minimizing the added conductance value (real of

Y2−YL) is not that simple. With the phase condition of above analysis,

A becomes

2

21

k kA

k k

, (3.8)

which is plotted in Fig. 3.5. It is clear from Fig. 3.5 that k should

be minimized to make the added conductance lower. One of the

methods of reducing k is utilizing the current division. The

characteristic impedance of the microstrip line of the bias network

should be minimized. In addition, connecting the bias network to a

５２

node that the impedance of load looked lowest is beneficial to

minimize k. The added conductance value at X2 is negative, implying

that the current is injected from the bias network. On the other hand,

the added conductance value at X1 is positive, meaning that the

current is leaked to the bias network.

In conclusion, the simple design criteria is acquired through

simple analysis. The design criteria is applicable to the practical

circuit design, but lacks detailed analysis and the effect of non-zero

added admittance. The precise non-zero added admittance analysis

and multiple load impedance effect will be discussed in next chapters.

Fig. 3.5. Plot of (3.8).

５３

3.3. Analysis of the proposed bias network

Given that the bias network should not affect the RF performance,

the impedance and phase of each bias line should be designed to

minimize the added admittance from the bias network itself. The

design criteria derived in the previous chapter is further specified in

this chapter, with the quantitative analysis.

The schematic of two-section RMDA shown in Fig. 3.4(a) and

the equivalent circuit for nodes X1 and X2 shown in Fig. 3.4(b). Let

the phase delay of the bias line connecting the two sections be θ,

and the phase delay of a section of the IATL be φ. Unlike the

analysis in previous chapter, both load impedances are considered

and the ratio k is not used. Instead, the characteristic impedance of

the bias line be Z0, and the ratio between Z0 and ZL is defined as k =

Z0/ZL. Assuming no reverse wave at the bias line, Y1, the admittance

seen at node X1, is Y1 = YL+Y'L, where Y'L is

2

tan

tanL Lk j

Y Yk jk

, (3.9)

５４

the load admittance of second section looked at node X1. I12 is

given as

12 1jL

L L

YI I e

Y Y

, (3.10)

by current division. Developing (3.10) with (3.9), the equation of

I12,

12 1 2tan

2 1 tan

jk jI I ek j k

(3.11)

is attained. Y2, the admittance seen at node X2 is given by the

following due the the active load-pull effect:

22

12 2L

IY Y

I I

(3.12)

by the active load-pull.

I1 and I2 denote the output current of drive stage in first section

５５

and second section, respectively. In the high-efficiency PA design,

the drive stage is almost in saturated power level. Therefore, the

output power of each drive transistor in RMDA exhibits

approximately identical current. Thus, the assumption of |I1|=|I2|

could be validated. With the assumption, I2 is expressed by

2 1jI I e . (3.13)

The added admittance Y2-YL is derived from (3.12),

122

12 2L L

IY Y Y

I I

. (3.14)

In the previous chapter, the added admittance is separated into

the added conductance and the added susceptance. In this chapter,

(3.14) is analyzed to provide insight to the shared bias network

design.

Substituting (3.11) and (3.13) in (3.14), the closed-form

expression of added admittance is expressed as a function of k and

θ:

５６

2 L L

C jDY Y Y

A jB

, where (3.15)

cos tan sin 2A k k , (3.16)

2tan cos sin 1 tanB k k , (3.17)

cos tan sinC k , (3.18)

tan cos sinD k , and (3.19)

. (3.20)

The magnitude of (3.15) is given by

2 22

tan

cos sinL Lk

Y Y Y

, where (3.21)

2 4 2 25 2 2 tank k k , (3.22)

2 2 24 2 1 tank k , and (3.23)

2 22 ( 1)tank k . (3.24)

５７

The magnitude of added admittance, should be minimized for the

proposed bias network to behave as a dc bias network. The value of

φ in the practical RMDA design in previous chapter is 63°. (3.21)

is calculated as a function of θΔ and k in Fig. 3.6. In terms of k, the

larger the k, the smaller the added admittance. The result shows that

the characteristic impedance of the microstrip line should be as high

Fig. 3.6. Calculated added admittance of the simplified bias network

in the two-section reactively matched distributed amplifier.

５８

as possible, matching the analysis of previous chapter. However, the

minimum value for added admittance does not correspond to θΔ =

0 due to the transformed load impedance of adjacent section, Y'L.

Although the minimum added admittance appear at θΔ = 30°, the

condition of θΔ = 0 is more beneficial in terms of operation

bandwidth.

To understand the effect of the non-zero value of the added

admittance, the effective gain of the reactively matched cell, Ais, is

calculated with the presence of added admittance of the bias network.

When the added admittance is zero, the change in Ais becomes zero.

The assumption of the perfectly matched interstage was made for the

worst case, which is the case of the largest decrease in Ais. For

analytical calculation of Ais, |Y2+Y*L| = |Y2+YL| is assumed. The

assumption is valid when |Y2-YL| is small enough compared to

|Y2+YL|, as in our case of broadband reactive interstage matching.

The magnitude of voltage reflection coefficient of the interstage of

the reactively matched cell |Γ| is given as

2

2

L

L

Y Y

Y Y

. (3.26)

The calculated gain reduction with respect to θΔ and k is plotted

５９

as shown in Fig. 3.7. If the interstage of the reactively matched cell

is perfectly matched at a certain frequency, then Ais = 1 (0 dB). Let

the magnitude of the added admittance be 0.3 of the load admittance,

which is in the case of θΔ = 0 and k = 1.2, then the magnitude of

Fig. 3.7. Calculated change of effective gain of the interstage of the

reactively matched cell caused by the simplified bias network in the

two-section reactively matched distributed amplifier.

６０

the voltage reflection coefficient |Γ| is 0.195, and Ais is 0.962

(−0.17 dB). The gain drop due to the added admittance is minimal in

this case, which shows that the proposed bias scheme provides

leeway in the practical design.

６１

3.4. Multi-section analysis and detailed design

The analysis of two-section RMDA can be expanded to the

multi-section RMDA. The principle of superposition is applied to

estimate the added admittance value in the multi-section RMDA

shown in Fig. 3.8. Among nodes X1–8, the nodes X2–7 is the junction of

the bias lines upwards and downwards, the magnitude of the added

admittance is expected to cancel out. Therefore, it can be assumed

that the added admittance is nearly zero at the nodes X2–7, and the

maximum value of added admittance is present at node X1 or X8.

In the case of eight-section RMDA, the effect of the proposed

bias network is examined by the RF circuit simulation. The simulation

of eight-section RMDA is done by sweeping θΔ and Z0, and the

maximum magnitude of added admittance for the nodes X1 to X8 of

each case is shown in Fig. 3.9. The simulated data follow the general

trend of two-section RMDA in Fig. 3.6. However, there is some

discrepancy. This comes from the load admittance differences; the

load admittance is assumed to be constant in the two-section

calculation, but the simulated results account for the actual load

admittance in the eight-section RMDA (see Fig 2.12). However, one

can still draw the similar conclusion. The added admittance of less

than 15 mS has minimal impact on the effective gain for 6–18 GHz

６２

operation. Therefore, the phase error below 15° and the

characteristic impedance above 75 Ω allows insignificant gain

degradation.

In the fabricated circuit, the bias lines are designed to have the

same phase shift as the input transmission line, which is 63° at 18

GHz, to ensure the broadband operation. The characteristic

Fig. 3.8. Detailed schematic of the proposed distributed power

amplifier. 200 Ω resistors are added to the gate bias circuits of both

drive and main stages to guarantee the unconditional stability.

Qd8

OUT

IN

X1

X8

X7

X6

X5

X4

X3

X2

Qd1

Qd7

Qd6

Qd5

Qd4

Qd3

Qd2

Qm1

Qm8

Qm7

Qm6

Qm5

Qm4

Qm3

Qm2

Qd1–d7

Qd8

Qm1–m8

: 4×75 μm: 2×125 μm: 6×125 μm

VD1

VD2

λ/4

λ/4

Two-stage

reactively

matched

cells

Shared

bias

network

Odd-numberdinductors

Even-numberdinductors

VG1

VG2

６３

impedance is tapered from 105 Ω to 75 Ω, considering the current

handling capability of the metals used in the shared bias line. The

magnitude of added admittance is less than 13 mS as shown in Fig.

3.10. The added admittance is almost zero at the middle sections, as

expected from the principle of superposition. Thus, the fabricated

circuit is expected to show negligible performance degradation due

Fig. 3.9. Simulated results of the maximum magnitude value of added

admittance of the simplified bias network in the eight-section

reactively matched distributed amplifier.

６４

to bias sharing.

Fig. 3.10. Simulated added admittance from the bias network of an

eight-section reactively matched distributed amplifier.

６５

3.5. Conclusion

In this chapter, the shared bias network is proposed. To make

open circuit in RF domain, the proposed biasing scheme is analyzed

with the active load-pull theory. The design criteria for proposed

bias network is provided. Through quantitative analysis, the effect of

added admittance is calculated. Also, the change in the interstage

effective gain is calculated and simulated with respect to the added

admittance. Through the analysis, the possibility of shared bias

network is verified. The amount of added admittance and change in

the interstage effective gain is negligible for RF performance of total

DPA circuit.

The proposed bias network is applied to the RMDA in this thesis.

The shared bias network is also applicable to any other type of

circuits. For example, the biasing technique can be employed to

previously mentioned DA circuits, such as CSSDA. In addition, in the

case of the power combining circuit with finite phase delay, such as

balanced amplifier, the shared bias could be used for compact biasing

scheme. Therefore, the proposed bias technique is the possibly the

useful scheme for variety of MMICs in compound semiconductor

process.

６６

Chapter 4

Chip Layout with Consideration of Thermal

Coupling

4.1. Introduction

In the HPAs with a solid-state device, especially GaN PAs, the

junction temperature needs to be considered not only for circuit

reliability but also for RF performance such as power, gain, and PAE.

Also, common GaN PA produces large amount of RF output power

with significant amount of dc dissipation power. Due to the dissipated

power, GaN HEMT device heats itself while operating, as shown in

Fig. 4.1. It is widely known that the high junction temperature results

in the lower RF drain current. Therefore, the electro-thermal model

of the GaN HEMT is composed of a normal large signal model and a

thermal sub-circuit to predict the RF performance with respect to

junction temperature. In addition, to embrace the self-heating effect,

６７

Fig. 4.1. Measured junction temperature of a GaN HEMT device

according to dissipated power level, showing the self-heating effect.

Fig. 4.2. Measured thermal coupling effect of a PA circuit.

６８

the thermal resistance, defined as rise in junction temperature per

dissipated power, is included in thermal sub-circuit.

The thermal coupling effect is another major factor for increase

in the junction temperature in the MMIC as shown in Fig. 4.2. The

thermal coupling effect refers to the case where the heat generated

in each transistor is coupled to the adjacent transistors. With the

presence of the thermal coupling, the junction temperature of the PA

MMIC can be much higher than the single transistor cases.

To reduce the junction temperature in the bare-die circuit level,

Thermal carriers with various materials are proposed, but the

materials with higher thermal coefficient are costly. Self-heating can

be minimized by enhancing the efficiency, but in the case of the HPA

with multi-octave bandwidth, PAE is limited to about 30%. Therefore,

in this chapter, the layout technique with consideration of thermal

coupling is presented.

６９

4.2. Design of Standard and Staggered Layout

Technique

The layout of RMDA designed through chapter 2 and chapter 3

is performed. With consideration of thermal coupling, two types of

layout is proposed: the standard layout and the staggered layout. The

former focuses on the layout efficiency, and the latter emphasizes on

reducing thermal coupling. For a fair comparison, the RF performance

of two types are designed to be identical.

The layout of the standard layout is straightforward. First of all,

the layout of reactively matched cell is performed to fit between

IATL and OATL. The room for shared bias network should be left for

bias layout. Each reactively matched cell is in identical layout, except

the last section. In the last section, the size of the drive transistor is

altered to 2×125 μm, due to a finite amount of incident RF signal at

the shared bias. The layout with standard configuration is shown in

Fig. 4.3. Die size is 2.1 mm × 5.1 mm, the compact layout is possible

by the virtue of the shared bias network.

To reduce the effect of thermal coupling in the MMIC, a thermally

optimized transistor layout is also implemented. The layout with

staggered configuration is shown in Fig. 4.4. The reactively matched

７０

Fig. 4.3. Layout of the proposed DPA MMIC with standard layout.

７１

Fig. 4.4. Layout of the proposed DPA MMIC with staggered layout.

７２

cells are placed in a staggered configuration in Fig. 4.4 to increase

the physical distance between the adjacent main transistors. To place

the second-stage transistors far from the first-stage transistors,

the inductor of the reactively matched cell is replaced by a long high-

impedance microstrip line in the odd-numbered sections. On the

other hand, the even-numbered section places the second-stage

transistor closer to the first-stage transistor so that the second-

stage transistors can be staggered. The die size has been increased

from 10.7 mm2 to 13.8 mm2 (2.7 mm × 5.1 mm). As the main

transistors are separated, the thermal coupling effect can be

mitigated, and the junction temperature of the circuit can be reduced

toward the similar level of the single devices.

The conceptual diagram of comparing the standard layout and the

staggered layout is shown in Fig. 4.5. In the standard layout, the

minimum separation between the main-stage transistors is 431 μm

while it has been increased to 772 μm in the new layout. As shown

in Fig. 4.5, the equi-temperature contour encloses all of the main-

stage transistors in the standard layout. On the other hand, the

contour is separated in the staggered layout, implying that thermal

coupling is less significant in the case.

For the comprehensive electro-thermal design, the thermal

simulation has to be performed with circuit simulation, as in the case

of the EM simulation and schematic simulation. The thermal

simulation is performed with both layout, under the condition of DPA

７３

operation. The dissipated power is set to 60 W in accordance with

the circuit simulation results. The boundary conditions for thermal

Fig. 4.5. Conceptual diagram comparing the standard layout and

staggered layout in terms of thermal coupling.

７４

analysis are determined correspondingly to the test fixture. The

thermal simulation is performed assuming the PA die is attached to

5-mm-thick Au-plated Cu carrier with a high-thermal-conductive

adhesive. The ambient temperature is assumed 45 ℃ at the bottom

of the thermal carrier with convection.

From the simulated result shown in Fig. 4.6, it can be seen that

Fig. 4.6. The simulated temperature distribution of die surface of

standard layout (left) and the staggered layout (right).

７５

thermal coupling effect has been reduced using the proposed layout

technique. The equi-temperature contour of 100 ℃ in the standard

layout encompasses all the main-stage transistors, showing thermal

coupling. On the other hand, it is isolated to each device in the

staggered layout. The thermal resistance of the total circuit is

reduced from 2.8 ℃/W to 2.6 ℃/W, respectively. The simulated

maximum temperature is also reduced from 219 ℃ to 210 ℃.

Attained thermal resistance values of each transistor are

incorporated to the electro-thermal model of GaN HEMT, and RF

simulation is revised with the simulated thermal resistance. The

effect of the reduced thermal coupling can also be seen in the

improved RF performance, as shown in the following section.

７６

4.3. Measurements of the Fabricated MMICs

Two RMDAs were fabricated using a commercial 0.25-μm GaN

HEMT foundry process by WIN Semiconductors Corporation. The

first RMDA is fabricated with a standard layout and the thermal

coupling reduced layout technique is applied to the second RMDA.

The photograph of the fabricated MMICs are shown in Fig. 4.7 and

Fig. 4.8. The same electrical design has been applied to both RMDAs

to compare the effect of thermal management. Fabricated MMICs are

attached to an Au-plated Cu carrier with a high-thermal-conductive

adhesive, as shown in Fig. 4.9. The adhesive is EK2000 by Epoxy

Technology Inc. with a thermal conductivity of 35.5 W/mK. The test

fixture is composed of a 5-mm-thick Au-plated Cu carrier and a

heat sink with thermal grease, as shown in Fig. 4.10. The RF tests

are performed under continuous-wave conditions with a drain bias

voltage of 30 V.

On top of RF performance, the thermal profile of the RMDA with

the staggered layout is measured. To estimate the junction

temperature drop by the proposed layout technique, IR thermal

microscope image was taken to compare the thermal profiles of the

conventional layout and the staggered layout. Thermal measurements

were performed by setting the temperature of the bottom of the test

７７

Fig. 4.7. Photograph of the fabricated reactively matched distributed

amplifier with standard layout.

７８

Fig. 4.8. Photograph of the fabricated reactively matched distributed

amplifier with staggered layout.

７９

fixture at 45 ℃ and the dissipated power level at 60 W, in

accordance with the thermal simulation in previous chapter. The

measured results are shown in Fig. 4.11. The staggered layout shows

reduced thermal coupling and lower junction temperature compared

Fig. 4.9. Photograph of the test fixture to test the proposed

amplifiers.

８０

(a)

(b)

Fig. 4.10. Block diagram of the (a) test fixture and (b) heat sink

configuration for RF characterization the fabricated MMICs.

８１

to the conventional layout. It is worth noting that the measured

thermal profile is in close agreement with the simulated results in Fig.

4.6.

Fig. 4.11. The measured temperature distribution of die surface of

standard layout (left) and the staggered layout (right).

８２

The measured small-signal S-parameter results of the standard

RMDA are compared with the simulated S-parameter results in Fig.

4.12. From 6 to 18 GHz, a small-signal gain of 15.3-23.2 dB is

achieved while S11 and S22 are lower than -10 dB. The average

value of the measured small-signal gain is 20.1 dB, which is among

Fig. 4.12. Measured and simulated performances of small-signal S-

parameters of the proposed distributed power amplifier with the

standard layout.

８３

the highest gain reported from > 10W DAs. Output power and PAE

are shown in Fig. 4.13. The measurements were done by sweeping

the input power from 27 to 30 dBm at each frequency to achieve the

required output power and PAE. The output power of 40.3-43.9 dBm

and PAE of 15.5-26.6% are achieved with a small die size of 10.7

mm2. The average output power is 42.0 dBm, and the average PAE

is 21.0%.

Fig. 4.13. Measured and simulated performances of output power and

efficiency of the proposed distributed power amplifier with the

standard layout.

８４

The measured RF performances of the RMDA with thermal

coupling-reduced layout are shown in Fig. 4.14 and Fig. 4.15. The

measured data with the staggered layout demonstrate further

improvement in RF performances. The proposed RMDA exhibits a

slightly higher small-signal gain of 16.7-24.1 dB from 6-18 GHz,

with an average gain of 21.7 dB. The PAE performance is also

Fig. 4.14. Measured and simulated performances of small-signal S-

parameters of the proposed distributed power amplifier with the

staggered layout.

８５

improved, reaching 15.0-29.4%. The simulation is performed using

the device model provided by the foundry, which does not include the

effect of thermal coupling. The average PAE in 6-18 GHz

frequencies is 22.6%, which is enhanced by 1.6% due to the reduced