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Ph.D. Dissertation

Development and characterization of

high-k / III-V MOS devices for low

power electronics

저전력 소자용 high-k / III-V MOS 소자 개발

및 특성 평가 연구

August 2019

Graduate School of Electrical and Computer

Engineering

Seoul National University

Su-Keun Eom

i

Abstract

Although gate length scaling of metal-oxide-semiconductor field-

effect-transistors (MOSFETs) with low power consumption has been

successful enabled by several innovative device technologies, extremely

scaled transistor has failed to achieve its steep power-constrained scaling

requirements and the sub-7nm logic transistor roadmap suggests alternative

channel material with high mobility. III-V compound semiconductor has

been considered to be the most promising technology among several

channel material candidates. However, its defective native oxide quality has

forbidden practical use of III-V channel in the semiconductor industry and

for several decades many research regarding III-V MOS have been

conducted to achieve improved interface which is still not comparable to the

Si results.

The scope of this work was mainly oriented to achieve high quality

interface at high-k/III-V MOS by studying the ALD process of high-k layers.

Several high-k materials such as SiNx and AlN were studied for the InGaAs

substrate and showed promising interface quality results, however, leaving

some issues of low dielectric constant that has failed to scale further

effective-oxide-thickness (EOT) down. In order to achieve an enhanced

interface characteristics along with a low EOT, the interface quality of

intrinsic HfO2/InGaAs interface was required. We have proposed a high

quality plasma-assisted atomic-layer-deposited (PA-ALD) HfOxNy by using

isopropyl alcohol (IPA) oxidant and cyclic N2 plasma treatment was

ii

demonstrated on N-type InGaAs which was the main achievement of this

work. Remarkable mid-gap Dit levels with strong inversion characteristics

were achieved which usually cannot be observed at defective HfO2/InGaAs

interface. Also, detailed study of the interface improvement mechanism and

characterization study of the advanced gate stack results were performed.

This outstanding achievement surpassed any other reported high-k/III-V

MOS results in the aspects of EOT scaling ability, mid-gap Dit suppression

and border trap reduction.

In order to realize the impact of MOS results in III-V MOSFETs,

InGaAs MOSFET fabrication processes were optimized. The trade-off

relationships in terms of the bulk and interface quality between the O3 and

IPA-based HfOxNy, respectively were optimized in perspective of the gate

stack. In this thesis, a bi-layer ALD high-k gate stack scheme that is

consisted of an IPA-based HfOxNy IL and an O3-based HfOxNy bulk layer is

proposed. Excellent subthreshold characteristics and on-performance were

achieved in the fabricated InGaAs MOSFETs using the optimized bi-layer

gate stack. Moreover, superior positive-bias-temperature-instability (PBTI)

reliability characteristics were achieved comparable to the best results

reported in III-V MOSFET research. Furthermore, MOCVD-grown InGaAs

MOSFETs were fabricated as a cost effective solution to the industry and by

optimizing both capping layer and buffer layer quality, comparable

transistor performance was achieved. And following the current trend, three-

dimensional fin-type InGaAs transistors were demonstrated. 60nm gate

iii

length of dry etched fin-type InGaAs quantum well MOSFET has resulted

in improved subthreshold characteristics compared to the planar-type. Also,

a bottom-up aspect-ratio-trapping (ART)-type InGaAs MOSFET was

demonstrated for future CMOS integration.

Additionally, the feasibility of highly advanced negative capacitance

FET (NC-FET) applications by employing ferroelectric HfO2 on the

developed InGaAs MOSFET technology has been demonstrated. NC-FET is

known to be the next generation technology that can achieve extremely low

subthreshold swing. A CMOS compatible low temperature un-doped ALD

HfO2 process was developed and it successfully exhibited ferroelectric

characteristics. In addition, in order to adopt the FE-HfO2 technology on

low thermal budget III-V materials, several technologies were studied to

improve the thermal stability and systematic study was further conducted in

order to analyze the ferroelectric formation mechanism. By integrating the

developed processes, successful demonstration of InGaAs MFMIS-FET was

observed with the characteristics of NC-FET.

Keyword : Indium gallium arsenide (InGaAs) channel, high-k oxides,

hafnium oxynitride (HfOxNy), III-V metal-oxide-semiconductor field-

effect-transistor (MOSFET), metalorganic chemical-vapor-deposition

(MOCVD), bias-temperature-instability (BTI) reliability

Student Number : 2013-20823

iv

Contents

List of Tables

List of Figures

Chapter 1. Introduction ····················································· 1

1.1. Backgrounds ······················································ 1

1.2. III-V for Low Power Electronics ·························· 6

1.3. Feasible Strategies for III-V Channel ··················· 11

1.4. Research Aims ·················································· 14

1.5. References ······················································· 16

Chapter 2. Development and Characterization of High-

quality High-k/InGaAs Interface ······································ 21

2.1. Introduction ······················································ 21

2.2. Individual Process Optimization ·························· 26

2.3. Impact of Oxidant in HfO2/InGaAs MOS-Capacitors

········································································ 36

2.3.1. Issues of Direct HfO2 Deposition ············ 41

2.3.2. IPA-based ALD HfO2 ···························· 42

2.3.3. Electrical Characteristics ······················· 47

2.3.4. Material Characteristics ························· 51

2.4. Development of Nitrogen Incorporation Technique in

III-V MOS-Capacitors ············································· 55

2.4.1. Oxygen Vacancy in HfO2 ······················· 55

v

2.4.2. Nitrogen Incorporation in ALD HfO2 ······ 57

2.4.3. Electrical Characteristics ······················· 59

2.4.4. Material Characteristics ························ 64

2.4.5. Dit-distribution Analysis ························ 68

2.4.6. Inversion Characteristics Analysis ·········· 75

2.5. Conclusion ······················································· 78

2.6. References ······················································· 79

Chapter 3. Fabrication and Characterization of InGaAs

MOS-FETs ······································································ 89

3.1. Introduction ······················································ 89

3.2. Individual Process Optimization ·························· 91

3.3. Characterization of HfOxNy/InGaAs MOSFET ······ 95

3.3.1. Bi-layer HfOxNy Gate Stack ··················· 97

3.3.2. Device Results ···································· 100

3.4. MOCVD-grown InGaAs MOSFET ···················· 116

3.4.1. Capping Layer Optimization ················· 117

3.4.2. Buffer Optimization ···························· 126

3.5. Three-dimensional InGaAs MOSFET ················ 131

3.5.1. QW III-V Tri-gate FET ························ 134

3.5.2. ART III-V Fin-FET ····························· 139

3.6. Conclusion ····················································· 142

3.7. References ····················································· 143

Chapter 4. Demonstration of InGaAs NCFET by using Ferro-

vi

electric HfO2 ····················································· 150

4.1. Introduction ···················································· 150

4.2. Development of Ferroelectric HfO2 ···················· 154

4.2.1. Process Optimization ··························· 157

4.2.2. Thermal Stability in III-V substrate ······· 163

4.2.3. Analysis of Hysteric Behavior in III-V

MFIS-Capacitors ········································· 168

4.3. Demonstration of FE-HfO2/III-V MFMIS-FET ···· 172

4.4. Conclusion ····················································· 175

4.5. References ····················································· 176

Chapter 5. Conclusions and Outlook ································181

5.1. Conclusions ·····················································181

5.2. Outlook ···························································183

Appendix. ·······································································185

A. PEALD SiNx for Interface Layer ·························185

B. PEALD AlN for Interface Layer ···························190

C. Pretreatment study for III-V substrate ····················194

Abstract in Korean ·························································198

Research Achievements ···················································202

vii

List of Tables

Table 1.1 Physical properties of semiconductor materials. ····················7

Table 1.2 Comparison of III-V material growth method. ···················· 10

Table 2.1 List of stable III-V oxides and their bulk oxide Gibbs free energies.

········································································· 22

Table 3.1 Description of III-V MOS Gate stacks. ····························· 97

Table 3.2 Benchmarking of III-V MOS Gate stacks. ························ 115

Table 3.3 Varied capping layer design effect on current and Rcap. ········· 123

Table 4.1 Properties of ferroelectric material candidates. ·················· 154

Table 4.2 IL gate stacks for InGaAs MFIS capacitors. ····················· 166

Table 4.3 Gate stacks for InGaAs MFIS capacitors. ························ 168

Table 4.4 Benchmarking of reported III-V NCFETs. ······················· 174

viii

List of Figures

Figure 1.1 Intel’s trend for scaling logic technologies. ························ 1

Figure 1.2 Power dissipation issue of physical gate length scaling, trends for

improving transistor performance and reducing active power in

the aspect of dynamic capacitance (left) and performance per

watt (right). ··························································· 2

Figure 1.3 Big data and instant data presented at the international roadmap

for devices and systems (IRDS) 2017. ···························· 3

Figure 1.4 Innovative device technologies for MOSFET scaling roadmap

(IMEC’s perspective). ··············································· 5

Figure 1.5 Comparison of III-V and Si transistor (a) Electron mobility of

group III-V compound semiconductors. (b) Superior on-current

boosting of III-V transistors. ······································· 8

Figure 1.6 (a) HSQ dummy gate (b) S/D regrowth. ··························· 9

Figure 1.7 CMOS compatible III-V channel strategies. ····················· 11

Figure 1.8 Integration of III-V on Si platform (a) Direct wafer bonding of

III-V channel (b) III-V ART fin growth FET. ··················· 13

Figure 2.1 Typical frequency dispersion phenomenon in C-V characteristic

of In0.53Ga0.47As MOSCAP. ···································· 23

Figure 2.2 (a) Schematic of trap response in energy bands of n-type

MOSCAP (b) Band valley structure of In0.53Ga0.47As (c)

Interface trap distribution of In0.53Ga0.47As MOS. ············· 25

Figure 2.3 The (2 × 4) surface reconstruction models of GaAs. Opened

circles indicate Ga and filled circles indicate As atoms. ······ 26

Figure 2.4 Process flow of InGaAs MOSCAPs. ······························ 27

ix

Figure 2.5 (a) Configuration of ISRC MEMS ALD (b) C-V characteristics

of atomic-layer-deposited dielectrics on Si substrate. ········· 29

Figure 2.6 Leakage plot of InGaAs MOSCAP fabricated in lift-off process

and etch-back process. ············································· 30

Figure 2.7 CV plot of HfO2/InGaAs MOSCAPs with varioius metal gates.

········································································· 31

Figure 2.8 (a) CV hysteresis comparison of PDA and PMA effect (b) 1 MHz

CV curves of InGaAs MOS capacitors. ························· 33

Figure 2.9 HfON/InGaAs MOS capacitors in the annealing conditions of

(a) RTA, 5torr, 5% FG, 400 oC, 10min (b) RTA, 5torr, FG, 350 oC, 60min (c) Furnace, ATM, 5% FG, 400 oC, 30min and (d)

Schematic of annealing mechanism. ····························· 35

Figure 2.10 Intel 45 nm high-k+metal gate strain enhanced transistors. ··· 36

Figure 2.11 TEMAHf and TDMAHf metal precursors for HfO2 ALD. ···· 37

Figure 2.12 HfCl4 and Hf(EtCp)2Cl2 metal precursors for HfO2 ALD. ···· 38

Figure 2.13 Thermal and plasma enhanced ALD of HfO2 on Si. ··········· 40

Figure 2.14 The vapor pressure of IPA in terms of temperature. ············ 42

Figure 2.15 Comparison of the O3 and IPA based HfO2 ALD characteristics

(a) deposition rate vs oxidant time (b) deposition rate vs

deposition temp. and (c) growth per cycle rate. . ··············· 44

Figure 2.16 Comparison of O3 and IPA based HfO2/Si MOS capacitors (a)

C-V and (b) Leakage-E plot. ······································ 46

Figure 2.17 Multi frequency C-V responses of (a) O3 and (b) IPA oxidant

based HfO2/In0.53Ga0.47As MOS capacitors; insets are the

hysteresis at 1 MHz. ················································ 48

Figure 2.18 Border trap estimation of HfO2/InGaAs MOS capacitors by

using the distributed oxide bulk trap model (a) O3-HfO2 and (b)

x

IPA-HfO2. ···························································· 49

Figure 2.19 Leakage plot of O3-HfO2 and IPA-HfO2 on InGaAs substrates.

········································································· 50

Figure 2.20 Conductance map of (a) O3-HfO2 and (b) IPA-HfO2 on InGaAs

substrates. ···························································· 50

Figure 2.21 STEM images of (a) O3-HfO2 and (b) IPA-HfO2 on InGaAs

substrates. ···························································· 51

Figure 2.22 XPS spectra of (c) As 3d5/2 (d) In 3d5/2 (e) Ga 2p3/2 core level

from HfO2/In0.53Ga0.47As with O3 oxidant (top) and IPA oxidant.

········································································· 52

Figure 2.23 TOF-SIMS results of (a) O3 based HfO2 (b) IPA based HfO2 and

impurity results of (c) O3 based HfO2 (d) IPA based HfO2 at

InGaAs substrates. ·················································· 54

Figure 2.24 (a) Schematic of oxygen vacancy in HfO2 dielectric and (b)

calculated electron trap levels associated with the oxygen

vacancy states. ······················································ 56

Figure 2.25 ALD cycle sequence of the developed HfOxNy processes on

InGaAs substrates. ·················································· 58

Figure 2.26 Multi frequency C-V responses of (a) O3 and (b) IPA oxidant

based HfON/In0.53Ga0.47As MOS capacitors; insets are the

hysteresis at 1MHz. ················································ 60

Figure 2.27 Border trap estimation of HfON/InGaAs MOS capacitors by

using the distributed oxide bulk trap model (a) O3-HfON and (b)

IPA-HfON. ·························································· 61

Figure 2.28 Leakage plot of O3-HfO2 (open, black), O3-HfON (closed,

black), IPA-HfO2 (open, red), IPA-HfON (closed, red) on

InGaAs substrates. ·················································· 63

Figure 2.29 Conductance map of (a) O3-HfON and (b) IPA-HfON on

xi

InGaAs substrates. ·················································· 63

Figure 2.30 STEM images of (a) O3-HfON and (b) IPA-HfON on InGaAs

substrates. ···························································· 64

Figure 2.31 TOF-SIMS results of (a) O3 based HfON (b) IPA based HfON

and impurity results of (c) O3 based HfON (d) IPA based HfON

at InGaAs substrates. ··············································· 66

Figure 2.32 XPS results of (a) low power (50 W) cyclic N2 plasma and (b)

high power (100 W) cyclic N2 plasma of HfON at InGaAs

substrates. ···························································· 67

Figure 2.33 The Dit distribution of the fabricated III-V MOS-Capacitors

showing great reduction in the mid-gap Dit with the IPA-based

HfOxNy. ······························································ 69

Figure 2.34 Benchmarking the mid-gap Dit values of our work compared to

the best results in the field of III-V MOS. ······················ 69

Figure 2.35 C-V characteristics of IPA-based PA-ALD HfOxNy (left) and

O3-based HfO2 (right) on p-type In0.53Ga0.47As substrates. ··· 70

Figure 2.36 The total Dit distribution within the In0.53Ga0.47As bandgap

which is extracted from the n-and p-type MOS-Caps. ········ 71

Figure 2.37 C-V characteristics of IPA-based PA-ALD HfOxNy on n-type

InGaAs substrate measured at (a) 350 K (b) 400 K and (c) 450

K. ····································································· 73

Figure 2.38 The total Dit distribution within the In0.53Ga0.47As bandgap

which is extracted from the temp. dependent conductance

method. ······························································ 74

Figure 2.39 The conductance profiles for (a) sample A1 and (b) B2. ······ 76

Figure 2.40 –wdC/dw and Gm/w profiles of sample B2. ···················· 77

Figure 3.1 Schematic of (a) inversion mode and (b) accumulation mode

InGaAs MOSFETs. ················································· 90

xii

Figure 3.2 Schematic of the process flow of InGaAs QW MOSFETs

fabrication. ·························································· 92

Figure 3.3 SiNx capping technology to protect the InGaAs surface (a) HSQ

capped and (b) SiNx capped. ····································· 94

Figure 3.4 Schematic diagram of the fabricated InGaAs MOSFETs. ······ 98

Figure 3.5 The ID-VG transfer characteristics with gate length (LG) = 5, 10,

20 μm of sample (a) ref. (b) A (c) B and (d) C measured at VD =

0.5 and 0.05 V; Insets represent the linear-scale ID-VG curve of

LG = 5 μm measured at VD = 0.5 V. schematic diagram of the

fabricated InGaAs MOSFETs. ·································· 102

Figure 3.6 On/off ratio comparison of varied gate stacks measured at VD =

0.5 V. ································································ 103

Figure 3.7 Vth roll off effect of varied gate stacks measured at VD = 0.05 V.

······································································· 103

Figure 3.8 Minimum SS for varied gate stacks in terms of gate length

measured at (a) VD = 0.5 V (b) VD = 0.05 V. ·················· 104

Figure 3.9 The multi-frequency C-VG characteristics of sample (a) ref. (b) A

(c) B and (d) C. ··················································· 107

Figure 3.10 Dit distribution of varied gate stacks extracted by conductance

method. ···························································· 108

Figure 3.11 Stress time evolution of threshold voltage shift under varied

PBTI stress for sample B and C. ································ 109

Figure 3.12 The lifetime extrapolation with varied gate stress for sample B

and C. ······························································· 110

Figure 3.13 Trapped charge density as a function of Eox for sample B and C.

······································································· 111

Figure 3.14 Pulse time configuration of FTCE. ····························· 112

xiii

Figure 3.15 FTCE characteristics of (a) Sample B and (b) C with varied gate

biases. ······························································ 113

Figure 3.16 Hysteresis of (a) Sample B and (b) C with varied gate biases.

······································································· 114

Figure 3.17 Achieved dopant concentration in terms of the dopant flow rate.

······································································· 119

Figure 3.18 TLM results in terms of growth temperature and dopant type.

······································································· 120

Figure 3.19 Ron extracted from the fabricated transistors in terms of gate

length and RSD extracted from the Ron-LG plot. ··············· 121

Figure 3.20 The transfer curve of the fabricated short channel III-V

MOSFET with highly Te-doped capping layers (a) log-scale

and (b) linear-scale. ··············································· 121

Figure 3.21 Capping layer resistance extraction varied with doping

concentration. ······················································ 123

Figure 3.22 Capping layer effect on MOSFET performance (a) SS (b) on

current (c) Rcap vs top doping concen. and (d) Rcap vs effective

doping concen.. ··················································· 124

Figure 3.23 Effect of bi-layer capping layer design on Ron and RSD. ····· 125

Figure 3.24 Buffer leakage in terms of buffer growth temperature. ······ 127

Figure 3.25 Lattice matched InGaAs epitaxial layer grown by MOCVD.

······································································· 128

Figure 3.26 Log-scale transfer characteristics of the fabricated InGaAs

MOSFETs with varied gate length. ···························· 128

Figure 3.27 The subthreshold slope characteristics of the fabricated InGaAs

MOSFETs with varied gate length and drain bias. ··········· 129

Figure 3.28 Device On-performance comparison to the MBE-grown InGaAs

xiv

MOSFET with similar material. ································ 130

Figure 3.29 Benchmarking of the fabricated planar type InGaAs MOSFET.

······································································· 130

Figure 3.30 Impact of channel band-gap on BTBT current. ··············· 132

Figure 3.31 Thin body Multi-gate FET as a solution for SCE suppression.

······································································· 133

Figure 3.32 Schematic of QW III-V Tri-gate FET. ························· 134

Figure 3.33 Process flow of QW III-V Tri-gate FET. ······················· 134

Figure 3.34 Schematic of the channel of the fabricated MOSFET. ········135

Figure 3.35 Schematic of the channel of the fabricated MOSFET. ········135

Figure 3.36 Transfer curves of the fabricated QW-MOSFETs (planar vs Tri-

gate). ·································································137

Figure 3.37 Family curves of the fabricated QW-MOSFETs (planar vs Tri-

gate). ·································································138

Figure 3.38 Benchmarking of our fabricated III-V MOSFET results to

advanced Si MOS technologies. ·································138

Figure 3.39 Process flow of ART III-V fin growth. ··························139

Figure 3.36 TEM result of the ART III-V fin. ································140

Figure 3.37 (a) Schematic and (b) transfer results of the fabricated InGaAs

ART FinFET. ······················································141

Figure 4.1 Energy landscape of a general ferroelectric material and its

polarization-electric field dependence derived from the free

energy. ·······························································151

Figure 4.2 Combining FE and DE materials with capacitance matching.

······································································· 153

xv

Figure 4.3 Polarization of HfO2 with varied dopants and concent. ········155

Figure 4.4 Approach to achieve hysteric PE curve of FE-HfO2. ···········156

Figure 4.5 Schematic and process flow of FE-HfO2 MIM capacitor. ·····157

Figure 4.6 Butterfly CV curve and PE curve of low temp. FE-HfO2 MIM

capacitor. ··························································· 158

Figure 4.7 Butterfly CV curve of low temp. FE-HfO2 MIM capacitor in

varied thickness. ··················································· 159

Figure 4.8 Permittivity of low temp. FE-HfO2 MIM capacitor in varied

thickness. ··························································· 160

Figure 4.9 XRD analysis of sputtered TiN with varied process conditions.

······································································· 161

Figure 4.10 Butterfly C-V characteristics of optimized TiN capped FE-HfO2

MIM capacitors. ·················································· 161

Figure 4.11 XRD analysis of FE-HfO2 with and without annealing. ····· 162

Figure 4.12 Thermal stability of IPA-based HfOxNy dielectric. ··········· 163

Figure 4.13 Butterfly C-V curve of FE-HfO2 MIM capacitors with different

annealing conditions. ···························································· 165

Figure 4.14 CV curves of the fabricated III-V MFIS capaictors (a) sample 1

(b) sample 2 (c) sample 3 and (d) sample 4. ·················· 167

Figure 4.15 CV curves of the fabricated III-V MFIS capacitors (a) sample 1

(b) sample 2 and (c) sample 3. ·································· 170

Figure 4.16 Amount of hysteresis estimated in the CV curves of the

fabricated III-V MFIS capacitors. ······························ 171

Figure 4.17 Comparison of transfer curves of InGaAs MISFET and

MFMIS-FET. ······················································ 174

1

Chapter 1. Introduction

1.1. Backgrounds

The silicon (Si) based metal-oxide-semiconductor field effect

transistors (MOSFET) has been the main stream technology of modern

micro-electronics for many decades [1-4], and semiconductor industry has

undergone one of the most remarkable market growth of any product in

history. Achievement of greater mobility and computing capability while

lowering standby power dissipation simultaneously has been the key goal

throughout the history of MOSFET and in order to accomplish this goal,

physical gate length scaling has been the most simple and effective method

leading to the birth of scaling trend so-called Moore’s law (Fig. 1.1) [2, 5-8].

Figure 1.1 Intel’s scaling trend for logic technologies .

2

The semiconductor foundry business has gone through a dynamic

transformation over the last 30 years. Today the foundries are leading the

process development race at 10 nm [9, 10] and even to 7 nm [11, 12], and

will continue to do so. However, traditional physical scaling of advanced

MOSFETs in conjunction with Dennard’s scaling rules has become

challenging as to increase the drive currents for faster switching speeds at

lower supply voltages is largely at the expense of large leakage current in

extremely scaled device [8]. These leakage currents arise from the quantum

tunneling and the thermal excitations resulting in a large static power

dissipation. Fig 1.2 shows that the current 14 nm and 10 nm technologies

lack the dynamic capacitance and power performance of the requirement in

the technology nodes [8].

Figure 1.2 Power dissipation issue of physical gate length scaling, trends

for improving transistor performance and reducing active power in the

aspect of dynamic capacitance (left) and performance per watt (right).

3

As a result, even with huge R&D investments, the semiconductor firms

gradually lagged the advertised on-chip feature sizes demonstrated in the

roadmap and finally the end of Moore’s law has been declared with the end

of 2016 International Technology Roadmap of Semiconductors (ITRS) [8,

13]. Moreover, over the past decades, personal computers, smartphones and

data centers have been the main application for semiconductor industry

growth. However, as we look into the future, smartphone industry seems to

be red hot and the future growth will not be driven by smartphones anymore.

Emergence of internet-of-things (IoT) [14] and big data applications [15]

has driven a necessity of abundant computing and memory resources that

requires always-on and high performance ultra-low-power devices to

generate data instantly (Fig. 1.3) [16]. Not only the technology but also the

market need is pushing the physical, electrical, and reliability requirement of

the device to the edge.

Figure 1.3 Big data and instant data presented at the international roadmap

for devices and systems (IRDS) 2017.

4

Innovative device technologies were required to enable the pursuit of

the scaling road map and over the past decades, outstanding developments

have been proposed to mitigate the stringent parasitic constrains regarding

small dimension device design (Fig. 1.4) [3, 17-19]. For 45nm node, high-

k/metal gate MOS technology replaced the silicon-dioxide (SiO2) /poly-Si

gate stack [3]. It is safe to say that the gate dielectric engineering has always

been the most important feature of a MOS transistor. It has significant

impact on the device performance with the most fabrication challenges in

nanometer scale dimension. The SiO2 gate dielectric is universally

considered a near-perfect dielectric with excellent nature to Si and obviously

the industry was very reluctant to part with the SiO2 gate dielectric [20].

Physical scaling under 1.3 nm of silicon-oxynitride gate oxide thickness

reached its limit due to severe tunneling current and extensive research of

high permittivity dielectric such as Hafnium-oxide (HfO2) is making

progress [21-23]. For 22nm node, short-channel effects limited planar gate’s

electrostatic control for further scaling and multi-gate transistors has been

introduced as the future generation MOSFET [18, 24]. This three-

dimensional gate geometry allows better gate controllability and reduces the

leakage path by thinning the fin width which enables excellent

subthreshold-slope device characteristics. While high permittivity gate

stacks and multi-gate transistor technologies have been successfully adopted

along the scaling roadmap, strained-Si is currently the dominant technology

for high mobility channel research which was introduced for 90nm node

[17]. However, it fails to satisfy the requirements of sub-7nm nodes with

particular emphasis on increasing low-field mobility and reduced doping.

Therefore, seeking novel channel material with high mobility continues to

be important.

5

Figure 1.4 Innovative device technologies for MOSFET scaling

roadmap (IMEC’s perspective).

6

1.2. III-V for Low Power Electronics

In order to overcome the scaling challenge, several device architectures

and materials based on both analytical and experimental academic research

were proposed and III-V compound semiconductor transistors due to their

significant carrier transport characteristics stand out as promising n-type

channel candidates for future highly scaled CMOS application [25-27].

The material properties of III-V compound semiconductor are

exhibited in Table. 1.1 with other semiconductors for low-power

applications. Light effective mass of III-V materials compared to Si even in

the highly strained case lead to higher electron mobility and higher injection

velocity, which should translate into great on-performance even at lower

VDD of 0.5V. Moreover, there is already a mature industry that uses III-V

high-electron-mobility-transistors (HEMTs) for high frequency application

[28-30] and it provides excellent techniques such as InGaAs and InAs

quantum-well (QW) FETs [31-33] or large band-gap buffer layer research

[34, 35]. However, most of these III-V compound semiconductors have

smaller bandgaps, which have great impact on the band-to-band tunneling

leakage currents. In addition, according to the Yan’s model [6], the higher

permittivity of these materials may worsen the short channel effects (SCE).

In spite of the demerits that may limit the scalability, the benefits are much

more attractive which makes the III-V channel technology a powerful

beyond CMOS solution.

7

Table 1.1 Physical properties of semiconductor materials.

Si Ge GaAs In0.53Ga0.47As InAs Impact

Electron

effective

mass (/m0)

mT/m

L

:

0.19/

0.16

mT/m

L

:

0.082/1

.467

0.067 0.041 0.026 Ion

Bandgap

(Eg) [eV] 1.12 0.66 1.42 0.75 0.36 BTBT

Mobility

[cm2/V-s] 1600 3900 9200 14000 40000 Ion

Hole

effective

mass (/m0)

mHH

/m

LH

: 0.49/

0.16

mHH

/m

LH

: 0.28/

0.044

mHH

/m

LH

: 0.45/

0.082

mHH

/mLH

:

0.46/0.051

mHH

/

mLH

: 0.57/

0.35

Ion

Permittivity 11.8 16 13.2 13.9 14.6 DIBL

/SS

8

Figure 1.5 Comparison of III-V and Si transistor (a) Electron mobility of

group III-V compound semiconductors. (b) Superior on-current boosting of

III-V transistors.

The general process of III-V compound semiconductor has some

differences compared to the typical Si process. Ion implantation, which is

normally used in Si process, is difficult to use in III-V substrates. Implant

activation requires high temperature annealing (around 750 to 800 oC)

which is critical to low thermal budget of III-V MOS [36-38]. In addition,

large energy ion implantation leaves structural implantation damages that

have not been annealed out in the range of activation annealing [36]. As a

result, S/D define method using highly doped III-V capping layer growth is

widely adopted [39-41] and as III-V materials are difficult to realize

inversion operation, depletion mode III-V HEMT with complex material

structure is the typical transistor structure [39, 42]. To define the gate region,

as highly doped capping layer is initially grown, capping layer of the gate

area should be removed through wet etching (gate recess) however short

gate length cannot be achieved. On the other hand, through dummy gate

9

process, first defining the gate area and then growing S/D area (regrowth) is

possible. In order to enable high performance transistor operation, defect

free and complex material structure is extremely important and III-V

material growth is the key challenge.

Figure 1.6 (a) HSQ dummy gate (b) S/D regrowth.

For III-V epitaxy, two technologies are competing that are utilized in

high volume, molecular beam epitaxy (MBE) and metalorganic chemical

vapor deposition (MOCVD) [43]. MBE is growth on a heated substrate in

ultra-high vacuum environment (base pressure of 10-9 Torr) typically using

elemental sources. The MBE is performed on an ultra-high-vacuum

environment which ensures great material purity.

MOCVD also grows on a heated substrate but in much lower vacuum

level and rather than using the elemental sources, metal-organic sources are

used with other gas sources. Although, technical advantage of superior

interface characteristics of MBE grown III-V is favorable and lots of III-V

wafer are supplied in MBE, commercial advantage of CMOS compatible

large size MOCVD grown wafer is important to meet the industry III-V

channel roadmap requirements.

10

Table 1.2 Comparison of III-V material growth method.

MOCVD MBE

Technical

High growth rate Fast switching for superior

interfaces

Growth near

thermodynamic

equilibrium

Able to grow

thermodynamically

forbidden materials

Excellent quality /

crystallinity Uniformity easier to tune

Commercial

CMOS compatible for

large size wafer Lower material cost / wafer

Overhead cost scales with

run rate

Overhead doesn’t scale

with run rate

11

1.3. Feasible Strategies for III-V Channel

The use of III-V compound semiconductors has been reluctant to the

industry because of its high cost manufacturing process and CMOS

incompatible process. Naturally, it brought out a strong motivation of

research of III-V hetero-integration on a Si platform. The main obstacle of

III-V on Si integration research is that as huge lattice constant mismatch

exists between those two materials growing epitaxial films directly on Si

without defect is difficult [44]. Accordingly, different approaches have been

developed, and among them, direct wafer bonding [45, 46] and aspect-ratio-

trapping (ART) [47, 48] technologies have projected the most promising

results.

Figure 1.7 CMOS compatible III-V channel strategies.

12

Direct wafer bonding technique is developed to transfer thin layers of

III–V channel onto silicon substrates similar to the process of silicon-on-

insulator (SOI) substrate manufacture [45, 46]. This technique allows us to

integrate high quality III–V channels on Si wafers under a large lattice

mismatch between III–V semiconductors and Si. Having a very thin III–V

channel on an insulator is the ideal structure to maintain good electrostatic

control of the gate over the channel at short gate lengths. The fabrication

flow of direct wafer bonding is that first the thin III-V channel layer is

initially grown on a donor substrate, which is then bonded via an oxide to a

target silicon substrate. After that, the thin III–V layer is then released from

the donor wafer, yielding a III–V-on-insulator structure on Si. The donor

wafer can be recycled in order to maintain the cost efficiency of this process.

This technique is also able to integrate large lattice mismatch materials such

as InAs or GaSb on Si for further development of low-power logic circuits.

IBM and Tokyo University are the main leading research groups for direct

wafer bonding technique.

Another approach is to use the aspect-ratio-trapping (ART) technique.

While direct wafer bonding requires 300mm or 450mm donor III-V wafers

thereby increasing the cost of the starting material and process complexity,

III-V ART grown FinFET, in contrast, offers a cost effective solution to

integrate III-V materials on the Si wafer. The fabrication flow of ART

FinFET is that first shallow trench isolation (STI) template is initially

prepared, and the Si fin is then recessed and is replaced with a III-V fin [47,

48]. By altering the trench width narrower, the dislocations, which result

from the lattice mismatch, are trapped at the sidewall and allowing defect

free III-V channel for the active region. IMEC is the main leading research

group for the ART technique.

13

Figure 1.8 Integration of III-V on Si platform (a) Direct wafer bonding of

III-V channel (b) III-V ART fin growth FET.

14

1.4. Research Aims

In this research, advanced process development and detailed

characterization of high-k/III-V MOS devices is investigated for low power

electronics. In order to fabricate high quality III-V MOS device, there are

several technical challenges regarding high-k/III-V interface, high-k

dielectric, III-V epitaxial growth quality and the FET architecture. The final

goal of this work is to demonstrate advanced III-V channel transistor for low

power application and innovative methods are proposed toward this goal in

the following chapters. The detailed outline of this dissertation is described

below.

Chapter 2 proposes highly advanced ALD gate stack technology for

delicate III-V substrate. At first, PEALD SiNx and AlN is reported for

interfacial layer on InGaAs substrate. The CV frequency dispersion was

successfully decreased however, leaving some issues of further EOT scaling

and Dit suppression. Then, in order to achieve enhanced interface

characteristics, high quality plasma-assisted atomic-layer-deposited (PA-

ALD) HfOxNy by using isopropyl alcohol (IPA) oxidant and cyclic N2

plasma treatment was demonstrated on N-type In0.53Ga0.47As. Remarkable

mid-gap Dit levels with strong inversion characteristics were achieved which

usually cannot be observed at defective HfO2/InGaAs interface. Also, we

report detailed study of the interface improvement mechanism and

characterization study of the advanced gate stack results. This outstanding

achievement surpassed any other reported high-k/III-V MOS results in EOT

scaling ability, Dit suppression and voltage stress reliability.

Chapter 3 discusses the fabrication and characterization of high quality

InGaAs MOSFET. Using the PA-ALD HfOxNy proposed in chapter 2 with

15

optimized fabrication flow, excellent subthreshold characteristics and on-

performance were achieved in the fabricated InGaAs MOSFETs. Moreover,

superior reliability on positive voltage stress was achieved compared to the

controlled samples. Furthermore, MOCVD-grown InGaAs MOSFETs were

fabricated and by optimizing both capping layer and buffer layer quality,

comparable transistor performance was achieved. And following the current

trend, three-dimensional fin-type InGaAs transistors are demonstrated.

60nm gate length of dry etched fin-type InGaAs quantum well MOSFET

resulted in improved subthreshold characteristics compared to the planar-

type. Moreover, bottom-up ART-type InGaAs MOSFET is demonstrated for

future CMOS integration.

Chapter 4 demonstrates a feasibility of our work to highly advanced

negative capacitance FET (NC-FET) applications by employing

ferroelectric HfO2 on InGaAs substrate. NCFET is known to be the next

generation technology that can achieve extremely low SS under 60 mV/dec.

First, the ferroelectric HfO2 formation process was optimized. Clear

ferroelectric characteristics were observed at low temperature deposited un-

doped ALD HfO2 process and the ferroelectric parameters were evaluated.

In addition, in order to adopt the FE-HfO2 technology on low thermal

budget III-V materials, several technologies were studied to improve the

thermal stability. Systematic study of the hysteresis behavior was further

conducted in the fabricated III-V MFIS capacitors in order to analyze the

polarization amplitude. Based on the experimental results, successful

demonstration of InGaAs MFMIS-FET was achieved and it exhibited the

characteristics of NC-FET.

16

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21

Chapter 2. Development and

Characterization of High-quality

High-k/InGaAs Interface

2.1. Introduction

As briefly discussed in the former section, the defective interface

quality has been the one of the major bottleneck toward the practical

realization of III-V compound semiconductors in logic semiconductor

industry [1-5]. The poor native oxide quality compared with SiO2 is

challenging even more with III-V materials than with Ge. III-V compound

semiconductors are typically composed of binary, ternary, or even

quaternary material covalent bonding and the more complex elements mean

a much richer population of possible oxides for III-V materials (Table 2.1)

[6]. These native oxides are not thermodynamically stable and very leaky

that rise serious issues of creation of significant surface states on the oxide-

semiconductor interface and huge trap assisted gate leakage current [1, 3, 7].

From an historical point of view, concerning the III–V channels, GaAs

MOSFET was early recognized as next generation transistor and the first

GaAs MOSFET was reported using SiO2 as gate dielectric [8]. At the early

stage of research, GaAs MOSFET suffered from high density of interface

states (over 3-order compared to Si) hindering inversion-mode operation.

22

Table 2.1 List of stable III-V oxides and their bulk oxide Gibbs free

energies.

Oxide Gibbs free energy, ΔG

(kcal/mol)

XPS core-level binding

energy (eV)

Ga2O -75.3 1117.3 (2p3/2), 19.6 (3d)

Ga2O3 -238.6 1117.9 (2p3/2), 20.2 (3d)

GaAsO4 -212.8 1118.8 (2p3/2), 21.1 (3d)

In2O3 -198.6 444.7 (3d)

InAsO4 -209.4 445.3 (3d)

As2O3 -137.7 1325.4 (2p3/2), 43.7 (3d)

As2O5 -187 1326.7 (2p3/2), 45.0 (3d)

Furthermore, to overcome the defective interface problem, many

research groups conducted extensive research effort with a search for a

perfect gate dielectric match for III-V substrate [9-11]. The discovery of

sulfide passivation (Li2S, (NH4)2S, Na2S) was first made which provided

excellent electronic properties to GaAs surfaces and sulfur passivation is

still an effective method in recent research [12, 13]. Another approach is to

employ a thin amorphous or crystalline Si layer as an interfacial control

layer between the III-V substrate and gate dielectrics such as SiO2 or Si3N4

[11, 14]. It was heavily researched in the early work of III-V MOS device

study and resulted in great achievements however, the electrical

performance was not enough and lacked in insight of future scaling. On the

other hand, still III-V channel MOSFETs suffered from high interface traps

hindering inversion-mode operation, and a series of accumulation-type

architecture devices that employs high work-function metal gates were also

reported [15, 16]. Moreover, study of ALD high-k dielectric led to

23

successful integration of high-k gate dielectrics on III-V substrate and recent

research is mainly focused on development and interface characterization of

ALD high-k and III–V compound semiconductors [17, 18].

Figure 2.1 Typical frequency dispersion phenomenon in C-V characteristic

of In0.53Ga0.47As MOSCAP.

To evaluate the objective III-V MOS characteristics, it is important to

understand the trapping mechanism and know what kind of measurement is

required. For Si, the primary defects are the well-known Pb centers, which

are dangling bonds at the immediate interface with the dielectric [19].

However, for III-V material, the anti-sites and interstitials are the critical

defect centers [1] and small DOS of III-V is also a weak point [20]. These

24

differences lead to different trapping mechanism and unlike Si MOS, III-V

MOS gate stack often exhibits a particular C-V phenomenon typically

known as the frequency dispersion effect as shown in Fig. 2.1 [21-23]. The

features of the frequency dispersion effect are threefold. First, large

inversion-like hump occurs even at high measurement frequency, which

could not be an actual inversion characteristic theoretically. Secondly, the C-

V curve horizontally shifts to the negative direction as the measurement

frequency decreases. Finally, the accumulation capacitance increases as the

measurement frequency decreases.

The large interfacial trap densities (Dit) that reside within high-k

dielectric and III-V substrate are mostly responsible for the explained

features (Fig. 2.2) [22, 23]. The high Dit especially the near mid-gap states

act as generation-recombination centers that attribute to the inversion hump

phenomenon in weak inversion regime. In addition, the large donor-like Dit

near the conductance band (for n-type substrate) induce substantial surface

charge that needs to be compensated by larger gate biases resulting in a

horizontal shift in the C-V curve. Detailed discussions are well explained

through both theoretical and experimental research [22, 23]. The

accumulation capacitance increase, however, is quite difficult to be

explained only by the interface traps. There have been numerous

publications on this particular accumulation dispersion behavior and

discussion led to an explanation of a carrier transport model from the

crystalline semiconductor into the border traps, which are defects within the

bulk of the dielectric [24]. The capture and emission process occur at border

traps with the interaction of conduction band electrons resulting in

discrepancy of accumulation capacitance and the thermal barrier in capture

process is responsible to the strong temperature dependency.

25

Figure 2.2 (a) Schematic of trap response in energy bands of n-type

MOSCAP (b) Band valley structure of In0.53Ga0.47As (c) Interface trap

distribution of In0.53Ga0.47As MOS.

26

2.2. Individual Process Optimization

Over the past decades, extensive studies of GaAs surface chemistries,

defect models have been conducted, and since elements of a chemical group

tend to share many similar properties, the acquired concepts are essential to

understanding the behavior of other III-V semiconductors [25, 26]. Due to

the superior transport characteristics, InGaAs research has thrived over

GaAs as a potential channel for future MOSFET applications. InGaAs exists

in a variety of indium concentrations and regardless of the indium

concentrations, the InGaAs alloy exhibits similar surface reconstruction

behavior to GaAs. The difference is shown in the temperature dependency

that since the In-As bond is weaker than Ga-As bond, free indium and

arsenic interstitials are easily formed on the surface at high temperature [26].

To explain in detail, at temperatures higher than 500 oC, preferential

desorption of As2 occurs leading to the (2 × 4) reconstruction changing to a

(4 × 2) indium rich surface (Fig. 2.3) [26]. This surface thermal instability of

InGaAs inhibits further dielectric annealing treatment difficult and

optimization of process flow is critical in III-V device engineering.

Figure 2.3 The (2 × 4) surface reconstruction models of GaAs. Opened

circles indicate Ga and filled circles indicate As atoms.

27

In order to achieve excellent MOS characteristics, fabrication and

precise measurement of MOS capacitor is critical, and based on the

capacitor results, many research groups report both quantitative, and

qualitative analysis results of III-V interface [1, 17, 22-24, 27-29]. The

typical process flow of capacitor fabrication is shown in Fig. 2.4.

Figure 2.4 Process flow of InGaAs MOSCAPs.

Epitaxial structure of the wafer for MOS capacitors is composed of Si

doped n-type In0.53Ga0.47As channel layer with a doping concentration of

1.0E+17 /cm3 which is grown on InP substrate.

The first key fabrication process is pretreatment before insulator

deposition. The main purpose of pretreatment is to remove native oxides and

depending on whether the treatment is done outside or inside the ALD

chamber, the treatments are classified as ex-situ or in-situ pretreatment. Ex-

situ pretreatment includes (1:3) HCl, 29% NH4OH, and 10% (NH4)2S

solutions to remove native oxides on the surface [2, 30, 31] and we used

these pretreatments for all studies in this order. Especially the sulfur

treatment performed lastly as previously discussed is known as very

powerful passivation method that protects the cleaned III-V surface from

28

oxidation [2]. In our study, we explored all the mentioned ex-situ

pretreatments and concluded that all of these methods are effective only to

some extent. On the other hand, in-situ pretreatment includes

trimethylaluminum (TMA) pulse and nitridation treatments. Short time

pulsing of the metal precursor using TMA is effective to remove native

oxides of III-V substrate which is known as the self-cleaning mechanism

[32]. Most research employ this simple method and have demonstrated

promising results. We used 5 times of 0.2sec TMA pulsing in our

experiments. Also, surface nitridation studies in various ways were proven

to be significantly effective for improving MOS qualities [33-36]. Studies

on the chemical reaction for III-V surface nitridation have already been

reported and reduction in native oxides by formation of thin III-N layers

was observed. In our ALD system, N2 plasma treatment was available and it

showed improvement also only to some extent. In conclusion, it is believed

that subcutaneous oxidation of the substrate during premature oxide

deposition [37] and plasma induced damage during pre-ALD surface cleans

can also generate Dit [38]. Therefore, optimization of pretreatments was

done and has been the foundation for excellent MOS results.

Secondly, high-k ALD deposition study is the most focused field of III-

V MOS research and is also the key subject of the thesis. The ALD

equipment used in the following experiments is shown in Fig 2.5 (a). It is a

shower head type chamber with direct plasma process mode available

facility equipped. 13.56 MHz RF generator is used for the plasma source.

For our study, HfO2, Al2O3 and AlN ALD deposited dielectrics were

investigated and optimized. The metal precursors of each dielectric were

tetrakis ethylmethylamino hafnium (TEMAHf) and trimethyl aluminium

(TMA). The C-V curves of optimized high-k/n-Si MOS are shown in Fig.

29

2.5 (b). Detailed challenges and dielectric material will be discussed in the

following sections.

Figure 2.5 (a) Configuration of ISRC MEMS ALD (b) C-V characteristics

of atomic-layer-deposited dielectrics on Si substrate.

30

After high-k dielectric layer deposition, gate metallization is one of the

remaining issues. Normally, in III-V studies, lift-off process is quite

common unlike in CMOS process. We have investigated this difference by

fabricating MOS capacitors in Fig. 2.6 and have found out when using E-

beam evaporator for metal deposition, there is no visible difference between

etch- back and lift-off processes. However, when using sputter for metal

deposition, as the sputter deposition is rather multi-directional compared to

e-beam evaporator, the accurate length define was more difficult and

especially it left photoresist leftovers which affect the device uniformity and

leakage drastically. In conclusion, sputtered metal such as TiN in this study

should be performed in etch-back process.

Figure 2.6 Leakage plot of InGaAs MOSCAP fabricated in lift-off process

and etch-back process.

31

In addition, gate metal type has constantly been investigated for III-V

MOS studies [39]. We have experimented different type of metals used for

general gate stacks in Fig. 2.7 and have concluded that using Pt as the metal

gate, the most improved electrical characteristics could be achieved. The

biggest advantage using Pt gate is that Pt has the biggest work function

value around 6.35 eV among other metal candidates and it affects the

threshold voltage (Vth) shifting toward the positive direction. While we will

discuss the details in the following sections, the Dit distribution of general

III-V MOS is shaped as highest Dit peak in the mid-gap level and lowering

toward the conduction band level. Thus, moving the Vth toward the positive

direction means that the Fermi-level movement to operate the transistor

would be shifted to the conduction band level and the Dit levels contributed

to the device operation would be lesser [40].

Figure 2.7 CV plot of HfO2/InGaAs MOSCAPs with varioius metal gates.

-2 -1 0 1 20.0

0.5

1.0

1.5

2.0

2.5 Ni/Au (by E-beam evaporation)

Pt/Au (by E-beam evaporation)

TiN (by high-power sputtering)

Cap

acit

an

ce [F

/cm

2]

Voltage [V]

32

Moreover, the hydrogen catalytic effect of Pt is also helpful in the annealing

process [41]. Without special comments, most of our experiments were done

with Pt gate.

Furthermore, with regard to improve the metallization process, ALD

deposited TiN was investigated. Precursor type, reactant type and deposition

temperature were TiCl4, NH3 and 350 oC respectively. Definite improvement

in electrical characteristics was observed due to elimination of deposition

damage of PVD process. ALD TiN was employed for the most advanced

transistor processes, which require the best step-coverage profile.

The final key fabrication process is the annealing step. Many groups

have different annealing conditions in ambient, time, temperature and

process step [41-43]. We have investigated all annealing conditions for the

advanced MOS results. In our experiments, it showed that forming gas

ambient consisted of 5% hydrogen and 95% nitrogen is the most effective

ambient to reduce interface traps. Meaningful impact on interface traps,

oxide charges, and border traps after forming gas annealing was observed

due to hydrogen incorporation as reported in former studies. Most research

groups tend to employ forming gas annealing in the similar condition and

for the following experiments, forming gas ambient consisted of 5%

hydrogen is employed.

Also, the effect of annealing significantly changes as the annealing step

locates in the process flow. It is classified as post deposition annealing

(PDA) or post metallization annealing (PMA) whether it is before or after

gate metallization step. In our experiments, PDA is only effective to some

extent and the annealing effect saturates in some point. Especially the CV

hysteresis does not decrease in the PDA condition, while PMA CV

characteristics report better results. We believe that the saturation point is

33

Figure 2.8 (a) CV hysteresis comparison of PDA and PMA effect (b) 1

MHz CV curves of InGaAs MOS capacitors.

34

the limit of PDA, which represents the damage occurred in the gate

metallization process (Fig. 2.8). Only PMA can further improve the MOS

performance in same annealing conditions with PDA and curing the

metallization damage. PMA was employed for all our studies.

Moreover, annealing temperature and time has been investigated

systematically. In 5 torr pressure condition using RTA, low temperature and

long time annealing resulted in the most improved CV results. The

annealing temperature below 300 oC had no effect on the CV results and

over 400 oC showed degraded maximum capacitance results due to gate

metal oxidation or indium out-diffusion probably [44]. In ATM pressure

condition using furnace, 30min of 400 oC annealing showed the most

promising result compared to other results (Fig. 2.9). It is perhaps that large

pressure of hydrogen is more effective in curing the dielectric or large

pressure annealing prevents the indium out-diffusion or annealing in broader

temperature might benefit from advantages of both high temperature and

long time annealing.

35

Figure 2.9 HfON/InGaAs MOS capacitors in the annealing conditions of

(a) RTA, 5torr, 5% FG, 400 oC, 10min (b) RTA, 5torr, FG, 350 oC, 60min (c)

Furnace, ATM, 5% FG, 400 oC, 30min and (d) Schematic of annealing

mechanism.

36

2.3. Impact of Oxidant in HfO2/InGaAs MOS-

Capacitors

For comprehensive summary of the issues in ALD HfO2, brief

introductory remarks of hafnium based dielectric development will be

discussed. Since the high-k materials was proposed to be the future

dielectric for EOT scaling, hafnium-oxide high-k dielectrics have been

regarded as the most promising gate insulator candidate due to its large

bandgap (~ 5.5 eV), high dielectric constant (k ~ 25), and high breakdown

field (5 to 6 MV/cm) [45]. In addition, hafnium-based dielectric has been

first introduced to the manufacture industry of 45 nm node LSI which was

the start for serious high-k/metal gate studies [46]. The key requirements for

high-k dielectric are high-k value for EOT scaling with sustainable leakage

property, robust against high thermal budget, good process controllability

and capability of thin film thickness. Hafnium-based oxides such as HfO2

and HfSiOx seem to meet these requirements well and have been studied

intensively (Fig. 2.10) [45].

Figure 2.10 Intel 45 nm high-k+metal gate strain enhanced transistors.

37

In typical formation of HfO2 deposition, the precursors are TEMAHf

and H2O and deposited around 300 oC. Above this temperature, it is known

that decomposition of the metal precursor occurs leading to CVD type

growth and leaving carbon contamination in the ALD dielectric [47].

Therefore, the first key issue is to obtain high quality film with low

dielectric deposition temperature. One method is to change the metal

precursors and Tetrakis-dimethylamido hafnium (TDMAHf) [48] and

hafnium chloride (HfCl4) [49] are the alternatives, which has been normally

studied. It was reported that the decomposition growth rate changes for

various metal precursors and especially decomposition of TDMAHf is only

half of that of TEMAHf at 300°C [48]. Also, TDMAHf precursor based

ALD HfO2 exhibited stable deposition rate even up to 350 oC.

Figure 2.11 TEMAHf and TDMAHf metal precursors for HfO2 ALD.

38

Also, as shown in Fig. 2.11, the low vapor pressure of TEMAHf

requires longer exposure time and it makes it more susceptible to the

decomposition reaction while TDMAHf has higher vapor pressure. So it is

considered that the thermal behavior of TDMAHf precursor seems to be

more suitable than TEMAHf for higher temperature processing, and as its

higher vapor pressure characteristics will bring advantage in the delivery

system, allowing higher concentration dosage.

Figure 2.12 HfCl4 and Hf(EtCp)2Cl2 metal precursors for HfO2 ALD.

HfCl4 precursor on the other hand has a different approach to solve this

decomposition issue [49]. As HfCl4 does not contain any carbon molecules,

the thermal decomposition issue may be easily prevented and therefore,

using chloride precursors has great advantage over any other carbon

containing precursors. Previous research of ALD HfO2 using HfCl4 already

reported high dielectric constants (k ~ 19 when using O3 and k ~ 21 when

using H2O) and low leakage current densities [49]. However, using chloride

precursors have raised new issues that Cl byproduct molecules such as HCl

are segregated at the ground boundaries of HfO2, which led to void

39

formation and high leakage currents. In order to reduce Cl residue in ALD

HfO2, several approaches were suggested such as employing less Cl atom

containing Hf precursors or even replacing the Cl ligand into

cyclopentadienyl (Cp) rings which is normally known to prevent the

formation of Cl ligand at Hf presursors (Fig. 2.12) [50].

Second method to improve the film quality is by employing PEALD

technique (Fig. 2.13) [51]. Stoichiometric HfO2 films with fairly low

impurity concentrations of C, H, and N (below 0.1 at.%) is important in

ALD film quality and by employing O2 plasma based PEALD process in

HfO2 deposition it can result in better film qualities with less O–H bonding

in the films which is usually the case for HfO2 deposited in thermal ALD

process [51]. Uncleaved ligands of metal precursor or high hydrogen

impurities are known to be the main leakage path which weakens the film

quality most. However, the presence of plasma normally limits the MOS

interface quality due to plasma damage and high reactivity of oxidant.

Another method to improve the film quality is to laminate other

dielectric films into HfO2. It is argued that the simplest solution would be

the introduction of an interfacial layer [45], such as SiO2, however this

approach suffers a tradeoff issue of gate capacitance and interface density.

Also, ordinary HfO2 layer crystallizes at relatively low PDA temperatures

leading to severe degradation of Dit and leakage [52]. Therefore, in order to

overcome these issues, a single hafnium based laminate oxide, which has

the desired characteristics of both dielectrics, has been explored. Hafnium

silicate (HfSixOy) and hafnium aluminate (HfAlxOy) has been investigated

as a promising material due to high dielectric constant, large band-gap, low

interface state density, and high thermo-chemical stability up to 700 oC.

Therefore, these materials have attracted many attentions in CMOS

40

application, which requires high thermal budget. In conclusion, while the

discussed high-k studies are mostly based on Si substrate, high-k MOS

study on III-V substrate is more difficult as discussed in the previous

sections, however, all methods have some insight on the direction of high-k

study in III-V MOS and will be discussed in the next section.

Figure 2.13 Thermal and plasma enhanced ALD of HfO2 on Si.

41

2.3.1. Issues of Direct HfO2 Deposition

Among the reported high quality insulator/InGaAs interface studies,

Al2O3 [32, 36, 53], AlOxNy [54], La2O3 [55], AlN [56] and Y2O3 [57]

demonstrated the most promising results while the direct deposition of HfO2

on InGaAs substrate has generally led to poor electrical characteristics and

there are only few studies aimed at improving the intrinsic HfO2/InGaAs

interface quality [33, 58]. These studies also target only in pretreatments,

which is vulnerable during oxide deposition. Meanwhile, O3 and H2O are

the most common oxidants employed in HfO2 ALD. However, one of the

disadvantages of H2O-based ALD is the high concentration hydroxyl groups

in the films, which degrades the dielectric interface during the post-

deposition annealing process [59]. In addition, sufficiently long purge time

is needed due to H2O tends to physisorb on the surface strongly, especially

at low temperature. To solve this problem, O3 is used as one of the most

promising alternative oxidants in ALD process, due to its strong oxidization

and high volatility. However, O3 is known to affect the III-V surface during

initial deposition cycles neglecting prior surface treatments that easily cause

the formation of inferior native oxides [60]. The excess interfacial oxidation

of the InGaAs surface initiated by the use of ozone is widely reported in the

previous studies. H2O oxidant also is not totally free from surface oxidation

[37]. Therefore, research on alternative oxidation sources is necessary for

HfO2/InGaAs MOS studies.

42

2.3.2. IPA-based ALD HfO2

Looking into the oxidant candidates, isopropyl-alcohol (IPA) is known

to be irresponsive to the semiconductor surface during the initial ALD

cycles [61] and as most pretreatment studies are aimed at removing native

oxides of the III-V surface, the IPA oxidant will be able to efficiently

suppress surface oxidation. To our knowledge, it is the first successful

demonstration of HfO2 deposition using IPA at InGaAs substrate.

Figure 2.14 The vapor pressure of IPA in terms of temperature..

43

The basic cycle of the HfO2 deposition consisted of TEMAH precursor

pulse and oxidant (ozone or IPA) exposure. N2 purging process was

performed for between precursor injection and the oxidant process. The

temperature of IPA precursor maintained at 4 oC. The vapor pressure of IPA

at 4 oC is around 10 mmHg four-times smaller than at room temperature

(Fig. 2.14) [62]. It is important to control the excessive vapor pressure

because it leads to long purge time, which disables efficient ALD.

We compared the ALD characteristics of HfO2 using O3 and IPA

oxidants (Fig. 2.15). Oxidant pulse times were 1 sec and 3 sec for O3 and

IPA respectively which were chosen to meet the saturation requirement of

ALD. Both oxidant had similar saturated deposition rate of 0.1 nm/cycle.

Noticeable difference was observed in the temperature windows of oxidant

type. While stable deposition rate of O3 oxidant was maintained in large

temperature range, saturated deposition rate of IPA oxidant was only

observed in small temperature range around 320 oC. In low temperatures,

low deposition rate is due to insufficient reaction which is originated from

low reactivity of IPA. Also, in high temperatures above 320 oC, thermal

decomposition of Hf precursor occurs and it hinders self-limiting

characteristics of ALD. Therefore, the deposition temperatures of HfO2

ALD were chosen to be 230 oC and 320 oC for O3 and IPA respectively.

Moreover, film thickness per ALD cycles is presented. It is observed that

linear deposition rate per cycle is obtained for both oxidants and thicker

interface layer thickness appears to be existed for the O3 oxidant due to is

strong reactivity.

44

Figure 2.15 Comparison of the O3 and IPA based HfO2 ALD characteristics

(a) deposition rate vs oxidant time (b) deposition rate vs deposition temp.

and (c) growth per cycle rate. .

45

By using O3 and IPA oxidant, HfO2/Si MOS capacitors are fabricated

on Si substrate (Fig. 2.16). All samples undergone standard Si cleaning steps

consisted of SPM and HF based cleaning and 400 oC 10 min annealed after

dielectric deposition. The CV and forward gate leakage characteristics are

measured and discussed. First of all, CV hysteresis difference is notable. As

anticipated, CV hysteresis significantly decreases by employing IPA oxidant.

Powerful oxidation ability of ozone may induce undesired interfacial oxide

at Si forming defective hafnium silicate leading to large hysteresis while IPA

based HfO2 appears to be negligible on this effect [47]. The dielectric

constants of IPA based and O3 based HfO2 extracted by thickness series

method are 19.4 and 17.6, respectively [63]. While CV results report

promising potential of IPA oxidant in ALD HfO2, the leakage properties

suggest a different aspect. Leaky forward gate leakage especially in the

medium-VG range of the IPA based HfO2 is presented and compared to the

O3 based HfO2. It is well known that at this gate bias range, the dominant

leakage mechanism is by poole-frenkel tunneling, which is a conduction

method of electron tunneling from a metal electrode to traps in a nearby

insulator layer followed by detrapping of the electrons from the traps by

virtue of a lowered potential well due to an applied electric field [64]. It

usually implies the bulk quality of dielectric, in short, larger the leakage in

this E-field is inferior the gate insulator is. It is speculated that by using IPA

oxidant the bulk quality may be inferior than using O3 oxidant in ALD HfO2.

This might affect further scaling down potential and border trap density in

ALD HfO2 application on InGaAs substrate [65].

46

Figure 2.16 Comparison of O3 and IPA based HfO2/Si MOS capacitors (a)

C-V and (b) Leakage-E plot.

47

2.3.3. Electrical Characteristics

By using the developed O3 and IPA oxidant based HfO2 dielectrics,

HfO2/InGaAs MOS capacitors were fabricated and the samples undergone

the fabrication steps as discussed in section 2.2. The multi frequency (1 kHz

- 1 MHz) C-V characteristics of HfO2 (7nm)/ n-In0.53Ga0.47As MOSCAPs

using O3 and IPA oxidants, and referred to as sample A1 and A2 respectively,

as shown in Fig. 2.17. The C-V curves of sample A1 showed a large

inversion hump in the negative bias range, which is attributed to the large

density of interface defect states near the mid-gap [66]. In contrast, those of

sample A2 showed a notable suppression of the inversion hump behavior. In

addition, by employing the IPA oxidant, the EOT has decreased. We

hypothesize that the reduced inversion hump and decrease of the EOT

originate from the suppression of un-intentional interfacial oxides by the use

of the IPA oxidant. Despite the advantages of using the IPA oxidant,

frequency dispersion at the accumulation region of sample A2, in

comparison to sample A1, slightly increased from 3.3 % to 4.7 % per decade.

In Fig. 2.18, these values were used to estimate the border trap densities (Nbt)

by using a distributed bulk-oxide trap model [67] and increased Nbt of

1.1×1020 cm-3eV-1 was extracted in sample A2 compared to 6.7×1019 cm-3eV-

1 in sample A1. Also, larger C-V hysteresis and severely degraded leakage

currents at positive bias are shown in Fig. 2.19. An inferior quality of the

HfO2 film for sample A2 was predicted which should be resolved for reliable

use of the IPA oxidant. In Fig. 2.20, conductance maps of sample A1 and

sample A2 are also shown and efficient movement of the conductance peak

with the gate bias was observed in sample A2, which can be attributed to less

surface oxidation leading to effective Fermi-level un-pinning [68].

48

Figure 2.17 Multi frequency C-V responses of (a) O3 and (b) IPA oxidant

based HfO2/In0.53Ga0.47As MOS capacitors; insets are the hysteresis at 1

MHz.

49

Figure 2.18 Border trap estimation of HfO2/InGaAs MOS capacitors by

using the distributed oxide bulk trap model (a) O3-HfO2 and (b) IPA-HfO2.

50

Figure 2.19 Leakage plot of O3-HfO2 and IPA-HfO2 on InGaAs substrates.

Figure 2.20 Conductance map of (a) O3-HfO2 and (b) IPA-HfO2 on InGaAs

substrates.

51

2.3.4. Material Characteristics

Cross sectional STEM images of HfO2/InGaAs samples with different

oxidants are shown in Fig. 2.21. It was noted that smooth interface is

observed for using IPA oxidant while 1.2 nm of interfacial layer is detected

for using O3 oxidant. We believe that strong oxidation ability of ozone

results in severe surface oxidation at deposition cycles while use of IPA

oxidant drastically diminishes this effect. It is quite encouraging to achieve

this result without any in-situ pretreatments normally performed to remove

the defective native oxides.

Figure 2.21 STEM images of (a) O3-HfO2 and (b) IPA-HfO2 on InGaAs

substrates.

Moreover, in order to further analyze detailed information of the

interface between HfO2/In0.53Ga0.47As, XPS spectra of As 3d5/2, In 3d5/2, Ga

2p3/2 with different oxidants are presented in Fig. 2.22. In order to analyze

clear interfacial oxide composition, 10 cycles of thin HfO2 were deposited to

allow photoelectrons ejected from InGaAs substrate escape through the film.

It was noted that when using O3 oxidant, large amount of In, Ga, As-related

oxide signals were present on the surface while significantly reduced oxide

52

Figure 2.22 XPS spectra of (c) As 3d5/2 (d) In 3d5/2 (e) Ga 2p3/2 core level

from HfO2/In0.53Ga0.47As with O3 oxidant (top) and IPA oxidant.

53

signals were observed for IPA oxidant. The higher Ga binding energy of O3

based HfO2 is attributed to the more fully oxidized Ga and AsOx signal

present in O3 based HfO2 is effectively removed below detection limit by

change of oxidant to IPA. These Ga and As related oxides are known to be

the unstable species responsible of severe fermi level pinning and large mid-

gap interface states. Also, InOx signal decreased in the IPA sample and even

the small detected signal may also be originated from the asymmetry

characteristics of indium peak not an oxide related signal. These results

confirm that definite HfO2/In0.53Ga0.47As interface quality improvement is

achieved by utilizing IPA oxidant which is consistent with improved

interface quality observed in C-V results.

Furthermore, TOF-SIMS analysis of HfO2/In0.53Ga0.47As with different

oxidants are presented in Fig. 2.23. By comparing the interface chemistry,

the most distinct change is observed for the oxygen species. For ozone

oxidant, broad and huge oxygen intensity peak is observed at the

HfO2/InGaAs interface, while, narrow and small oxygen intensity peak is

noticed for the IPA oxidant sample. Also, decline of the substrate atoms

including In, Ga, and As is steeper for the IPA based HfO2 compared to the

ozone based HfO2. These result supports our hypothesis that using IPA

oxidant has advantage over the O3 oxidant at the III-V interface by tight

protection of undesired surface oxidation. Meanwhile, in the aspect of

atomic concentration of the bulk HfO2, when using IPA oxidant, higher ratio

of Hf:O ratio and larger nitrogen impurities within HfO2 are observed

compared to the ozone oxidant [69]. This result implies that inferior bulk

characteristics of the IPA-HfO2 is responsible from the weak IPA oxidant

reactivity leading to insufficient oxidation in the ALD process which

generates high defect density originated from oxygen vacancies [70-74].

54

Figure 2.23 TOF-SIMS results of (a) O3 based HfO2 (b) IPA based HfO2

and impurity results of (c) O3 based HfO2 (d) IPA based HfO2 at InGaAs

substrates.

55

2.4. Development of Nitrogen Incorporation

Technique in III-V MOS-Capacitors

2.4.1. Oxygen Vacancy in HfO2

In order to improve the weak IPA based HfO2 bulk quality, study of

origin in HfO2 defect is necessary. One of the main concern in the

replacement of SiO2 to HfO2 is that compared to SiO2, HfO2 generally

suffers from high defect densities leading to several issues such as large

carrier trapping, mobility degradation due to coulombic scattering in the

channel surface, and threshold voltage shifts in gate stress conditions [70-

74]. To be specific, the threshold voltage shift issue was not a new

phenomenon that suddenly happened with use of HfO2. In immature SiO2

MOSFETs, it is widely known that the extrinsic contaminations in SiO2 with

alkali ions induce this similar phenomenon [75]. However, with HfO2, it

appeared to be caused by the high defect concentrations, which originated

from a more fundamental problem not an extrinsic defect. Consequently,

many research were devoted to HfO2 physical model simulation in order to

identify the type of defects and their energy levels, and by these physical

study, researchers hoped to learn how the deposition and processing

conditions can be optimized to minimize these defect origins [70, 71, 73,

76].

Based on computational calculations, it is identified that oxygen

vacancies in HfO2 are both the principle trap and main cause of the

discussed issues and its formation energy and energy levels were also

calculated [71] as shown in Fig. 2.24. Hence, in order to reduce the defect

56

densities, experiments regarding deposition and post processing conditions

were aimed to remove or passivate these defects, with an oxygen rich

ambient. However, in many cases, it only worked to some extent and led to

new issues of excessive oxidation leaving oxygen interstitials and oxygen

diffusion to the interface [77].

Figure 2.24 (a) Schematic of oxygen vacancy in HfO2 dielectric and (b)

calculated electron trap levels associated with the oxygen vacancy states.

Additionally, due to the low density of states of III-V semiconductors,

III-V substrates are heavily influenced to border traps that could severely

worsen the device performance resulting in poor reliability properties.

Therefore, not only the interface but also the bulk characteristics of HfO2

should be considered in III-V MOS studies and improvement in both

qualities is definitely important.

57

2.4.2. Nitrogen Incorporation in ALD HfO2

One of the most effective method to improve the inherent properties of

HfO2 is the incorporation of nitrogen to passivate oxygen vacancies and it

has been extensively utilized in many recent studies [74, 78-81]. Significant

improvement in the electrical characteristics of various high-k gate

dielectrics by nitrogen incorporation has been demonstrated and it is found

that interfacial layer growth is effectively suppressed [80] and lower boron

penetration with nitrogen incorporation [82]. Also, lower leakage current

density in HfOxNy is widely reported due to suppression of oxygen vacancy

traps [80]. It has been reported that nitrogen incorporation in HfO2 can be

achieved by several methods mostly by nitrogen ambient plasma based

nitridation [78, 80] or ammonia (NH3) ambient high temperature annealing

treatment [83, 84]. For Si based MOS studies, the later approach is known

to be very powerful achieving good uniformity of nitrogen incorporation

and excellent interface quality due to the absence of plasma damage.

However, in order to successfully apply nitrogen incorporation technology

on III-V substrate, the low thermal budget of III-V compound

semiconductor always has to be considered and high temperature annealing

treatment should be ruled out for nitrogen incorporation study in III-V MOS.

In the other hand, although plasma based nitridation technology offers low

thermal budget capacity, most studies generally suffers from several issues

such as non-uniform nitrogen distribution throughout dielectric [85], plasma

induced damage due to high power plasma for dielectric penetration and

high energy potential nitrogen species substituting well combined Hf-O

bonds [86]. Post deposition plasma treatments have recently been suggested

for InGaAs MOS devices [87] however, no effort was made to improve the

58

nitridation technology regarding the discussed issues.

In this thesis, in order to improve the film quality of HfO2, a cyclic

nitrogen low power plasma step was added within the ALD cycles to

passivate oxygen vacancies uniformly without causing damage or surface

degradation. Through this technology with a combination of IPA oxidant,

achievement of improvement in both interface and bulk quality of high-

k/InGaAs MOS properties is expected. The detailed information of the ALD

sequence is depicted in Fig. 2.25. Every cycle is consisted of sequential

precursor pulse steps and a gas stabilization step followed by 5 sec of 50 W

N2 plasma step with purge steps between pulse steps. It is discovered that

there is a trade-off relationship of plasma condition. The plasma power

should be enough for effective passivation while it may degrade the

substrate by radiation damage. Through the developed ALD sequence, with

adequate plasma condition, the HfO2 layer is improved without having

influence in the substrate.

Figure 2.25 ALD cycle sequence of the developed HfOxNy processes on

InGaAs substrates.

59

2.4.3. Electrical Characteristics

By using the proposed nitrdiation technology, HfOxNy/InGaAs MOS

capacitors are fabricated and the samples undergone optimized fabrication

steps as discussed in section 2.2. The multi frequency C-V characteristics of

PA-ALD HfOxNy (7 nm) / n-In0.53Ga0.47As MOSCAPs using O3 and IPA

oxidants, will be referred to as sample B1 and B2 respectively, are presented

in Fig. 2.26. An outstanding inversion behavior of sample B2 is observed

which has not been reported in numerous studies on HfO2/InGaAs without

interfacial layers [88]. Moreover, a significant suppression of the frequency

dispersion was observed upon nitrogen incorporation in every gate bias

range. The inversion humps and flat-band voltage shift were effectively

reduced for all samples, which imply that the defective interface states near

the mid-gap level can be treated with nitrogen incorporation. It is

hypothesized that oxygen diffusion through the oxygen vacancies of HfO2,

which results in the formation of AsGa anti-sites was greatly reduced, as

oxygen vacancies were effectively passivated with nitrogen [1]. Therefore,

nitrogen may block further oxygen diffusion, thereby preventing surface

oxidation, which could occur not only during but also after dielectric

deposition. Furthermore, frequency dispersion in the accumulation region

greatly reduced to 2.1% and 3.2% per decade for sample B1 and B2,

respectively. Also, decreased Nbt of 7.0×1019 cm-3eV-1 and 5.8×1019 cm-3eV-

1 were extracted in sample B1 and B2, respectively in Fig. 2. 27. These

values are comparable to suppressed dispersion values in low EOT gate

stacks, which imply excellent reliability quality of dielectric stacks on III-V

substrate [89, 90]. As the proposed nitridation technology is aimed to treat

inferior bulk qualities of HfO2, it showed greater impact on IPA based HfO2.

60

Figure 2.26 Multi frequency C-V responses of (a) O3 and (b) IPA oxidant

based HfON/In0.53Ga0.47As MOS capacitors; insets are the hysteresis at

1MHz.

61

Figure 2.27 Border trap estimation of HfON/InGaAs MOS capacitors by

using the distributed oxide bulk trap model (a) O3-HfON and (b) IPA-HfON.

62

Significant improvement of leakage currents at positive bias with

nitrogen incorporation is shown in Fig. 2.28. Moreover, efficient movement

of the conductance peak with gate bias indicates free Fermi-level movement

around the mid-gap level in HfOxNy samples, shown in Fig. 2.29. In

summary, although slightly better bulk quality of O3 based HfOxNy is

estimated, we believe that the significant improvement in interface trap

density makes IPA based HfOxNy more favorable in overall gate stack

quality.

63

Figure 2.28 Leakage plot of O3-HfO2 (open, black), O3-HfON (closed,

black), IPA-HfO2 (open, red), IPA-HfON (closed, red)on InGaAs substrates.

Figure 2.29 Conductance map of (a) O3-HfON and (b) IPA-HfON on

InGaAs substrates.

64

2.4.4. Material Characteristics

Cross sectional STEM images of HfOxNy/InGaAs samples with

different oxidants are shown in Fig. 2.30. Significant improvements in all

samples were observed by employing the developed cyclic nitrogen plasma

treatment. The interfacial layer has shrunk by nitrogen treatment even in the

case of ozone oxidant based oxide deposition and it was noted that smooth

interface with clear atomic-resolution crystal structure is observed for using

IPA oxidant HfOxNy. The absolute surface protection is successfully

achieved by employing the developed oxide deposition technology and it

supports the excellent electrical characteristic of InGaAs MOS observed

from the experiment.

Figure 2.30 STEM images of (a) O3-HfON and (b) IPA-HfON on InGaAs

substrates.

65

Film compositions of all samples were analyzed by TOF-SIMS showed

in Fig. 2.31. Narrower and smaller oxygen signal peaks on HfOxNy/InGaAs

interfaces are observed and steeper III-V substrate related signals including

In, Ga and As signals are observed compared to the HfO2 samples. It all

supports the superior interface characteristics of HfOxNy/InGaAs MOS

capacitors. The signals of nitrogen impurities in the HfOxNy samples were

larger than that of HfO2 oxidant sample indicating successful nitrogen

incorporation. It was also, found to be that the nitrogen profile slightly

piling up at the high-k/InGaAs interface. Enhanced nitrogen amounts at the

interface might have a surface nitridation effect resulting in Dit reduction.

Carbon impurities seems to be the same whether nitrogen plasma is treated

and it implies that radiation effect through plasma treatment is not the main

cause of interface enhancement mechanism.

The bonding configurations of IPA based HfOxNy are observed for low

and high power nitrogen plasma treatment in Fig. 2.32. When high plasma

power is applied, high increase of N-Hf bond is observed while N-Ga bond

maintains similar. This result indicates that the cyclic nitrogen plasma

treatment is well targeted to the bulk layer of HfO2 and only minor direct

impact of nitrogen plasma was made on the III-V surface. Therefore, the

interface enhancement mechanism should be explained through the bulk

enhancement approach.

66

Figure 2.31 TOF-SIMS results of (a) O3 based HfON (b) IPA based HfON

and impurity results of (c) O3 based HfON (d) IPA based HfON at InGaAs

substrates.

67

Figure 2.32 XPS results of (a) low power (50 W) cyclic N2 plasma and (b)

high power (100 W) cyclic N2 plasma of HfON at InGaAs substrates.

68

2.4.5. Dit-distribution Analysis

Based on the multi-frequency C-V measurements, the Dit distributions

were extracted with using the conductance method and are shown in Fig.

2.33. The combination of IPA oxidant and PA-ALD HfOxNy with standard

interface treatments resulted in a reduced Dit level of 4.5×1011 eV-1cm-2 at Ec

- Et = 0.3 eV. This result is comparable with previously reported excellent

values for high-k/InGaAs studies even without special in-situ pretreatments

or particular interfacial layers [91, 92]. Based on the Dit distribution, it is

evident that the inversion behavior observed in the C-V curves of sample B2

is due to the significant mid-gap Dit decrease, which is consistent with

previously reported studies. As the mid-gap Dit is known to correlate to the

AsGa anti-site defect and the ozone based HfOxNy lacked inversion

characteristics with high mid-gap Dit, these defects might be the reason why

the inversion behavior is difficult to be achieved in most studies. Also, these

defects might be formed in the initial ALD steps through the oxidant

exposure.

Also, in Fig. 2.34, we have benchmarked our results comparing to the

best results ever reported in the field of III-V MOS-device studies.

Extraordinary mid-gap Dit values are achieved with low CET values with

our work. Especially, while other studies mostly suffer from insufficient

dielectric constant of the IL, our work employs HfO2 as an IL which have

merit in terms of the EOT scaling.

69

Figure 2.33 The Dit distribution of the fabricated III-V MOS-Capacitors

showing great reduction in the mid-gap Dit with the IPA-based HfOxNy.

Figure 2.34 Benchmarking the mid-gap Dit values of our work compared to

the best results in the field of III-V MOS.

70

In addition, with conductance method in the measurement frequency

range of 1 kHz to 1 MHz, the n-type MOS-Cap results can only provide

information of Dit distribution near the conduction band. In order to estimate

the total Dit distribution throughout the bandgap in InGaAs, p-type InGaAs

MOS was fabricated and analyzed. The p-type InGaAs MOS-Caps are

fabricated in the same process flow of n-type MOS-Caps. The multi

frequency C-V measurements of IPA-based PA-ALD HfOxNy (7 nm) / n-

In0.53Ga0.47As MOS-Cap compared to the HfO2 (O3) sample is presented in

Fig. 2.35. Compared to the reference, the optimized HfON process we

developed exhibits significant frequency dispersion suppression with steeper

CV slope. This result is comparable to the previously reported high-quality

p-type InGaAs MOS results. It is assumed that the interface improvement

mechanism is similar to the previous n-type MOS analysis.

Figure 2.35 C-V characteristics of IPA-based PA-ALD HfOxNy (left) and

O3-based HfO2 (right) on p-type In0.53Ga0.47As substrates.

71

Based on the results, the Dit distribution within the InGaAs band-gap is

extracted with the conductance method shown in Fig. 2.36. The Dit level at

the exact mid-gap energy level (Eg/2 = 0.375 eV) is around 8 x 1011 eV-1cm-

2. This value is still low for reported III-V MOS interface and it is suggested

that based on the Dit distribution, the accumulation mode n-channel III-V

devices are favorable than the inversion mode p-substrate III-V devices

because the overall Dit levels are much lower at the conduction band area.

Figure 2.36 The total Dit distribution within the In0.53Ga0.47As bandgap

which is extracted from the n-and p-type MOS-Caps.

Moreover, temperature dependent conductance method was performed

in order to analyze the mid-gap Dit level thoroughly. High temperature (350

K, 400 K and 450 K) multi-frequency CV analysis was conducted on

72

HfON/InGaAs MOS Capacitors. The CV results of each measurement

temperature are shown in Fig. 2.37. As the measurement temperature

increases, the inversion response gets stronger at higher frequencies

compared to the room temp. measured results. Also, while the dispersion at

the accumulation region seems to be similar there was significant impact on

the inversion hump phenomenon which is the interface trap characteristic.

The measurement noise at higher temperature and lower frequencies was

also noted. When the measurement temperature reaches around 450 K, the

strong inversion response occurs even at 1 MHz and it interferes with the

interface trap related conductance peak making the deconvolution process

impossible.

The Dit distribution was estimated from the temperature dependent

conductance technique. As the measurement temperature increases, the

deeper energy range could be measured. Similar Dit profile was observed

showing a peak energy level around the exact mid-gap level (~ 0.375 eV).

The peak Dit value is slightly higher than the previously estimated value

which would be the effect of enhanced thermal broadening of trap response

in higher temperatures. The differences between the Dit profile estimation

method are while using p-MOS capacitors, a larger energy level range is

observable with no thermal broadening of the trap response due to the fixed

measurement temperature on the other hand, using temp. dependent method

has a thermal broadening issue but only requires one sample for

characterization.

73

Figure 2.37 C-V characteristics of IPA-based PA-ALD HfOxNy on n-type

InGaAs substrate measured at (a) 350 K (b) 400 K and (c) 450 K.

74

Figure 2.38 The total Dit distribution within the In0.53Ga0.47As bandgap

which is extracted from the temp. dependent conductance method.

0.0 0.2 0.4 0.6 0.810

10

1011

1012

1013

1014

300 K

350 K

400 K

Dit [

eV

-1c

m-2]

Et [eV]

75

2.4.6. Inversion Characteristics Analysis

It was noted that in sample B2, inversion behavior is attributed to the

mid-gap Dit level decrease. However, in order to verify true inversion

characteristics, more analyze must be investigated. In Fig. 2.38, the

conductance profile of sample A1 and B2 are depicted. Both CV profile have

shown inversion like behavior in the negative bias region. However, clear

difference is observed between the conductance profiles. While huge and

gaussian conductance profiles in the negative bias regions are observed for

sample A1, smaller gaussian conductance peaks are observed in depletion

region and distinct from these peaks saturated conductance profiles are

observed for sample B2. Therefore, it is concluded that the inversion-like

behavior in sample A1 is attributed from the huge and broad conductance

peaks that reflects high midgap Dit levels, while inversion behavior in

sample B2 might be attributed from real true minority carrier inversion.

In Fig. 2.39, to verify true inversion characteristics of sample B2 , the

minority carrier response was investigated based on the extraction of the

transition frequency, ωm , which is known to be a characteristic of a strong

inverted surface for III-V MOS capacitors [93, 94]. It is known that at the

transition frequency the–ωdC/dω and Gm/ω shares a same peak magnitude

in the strong inversion gate bias. Notably, –ωdC/dω and Gm/ω share the

same peak magnitude at same transition frequency of 4 kHz which suggests

that sample B2 exhibits true inversion behavior. The true inversion behavior

of hafnium-oxide based dielectrics on InGaAs substrate has not been

reported yet which implies significant potential of our work.

76

Figure 2.38 The conductance profiles for (a) sample A1 and (b) B2.

77

Figure 2.39 –wdC/dw and Gm/w profiles of sample B2.

104

105

106

0.0

20.0p

40.0p

60.0p

80.0p

100.0p

-dC/d

Gm/

[rad/s]

78

2.5. Conclusion

In this chapter, various ALD high-k layers were investigated for the

InGaAs substrate. Nitride based dielectrics such as SiNx and AlN were first

studied to prevent the formation of defective native oxide interfacial layers.

Significant interface qualities were achieved by using the nitride layers

however, due to the smaller dielectric constant, further EOT scaling has

been difficult. In order to achieve both low EOT and low Dit, a highly

advanced gate stack, prepared by using an IPA oxidant in the PA-ALD of

HfOxNy on N type In0.53Ga0.47As substrates were proposed and showed the

most outstanding results.. A cyclic nitrogen low power plasma step was

added within the ALD cycles to passivate oxygen vacancies uniformly

without causing damage or surface degradation in comparison to post

deposition nitridation technology. Remarkable mid-gap Dit levels with

strong inversion characteristics were achieved which has not been reported

in the previous HfO2/InGaAs interface studies. The improved interface

characteristics can be attributed to both low surface oxidation ability of IPA

and suppression of oxygen diffusion by effective nitrogen passivation to

oxygen vacancies in HfO2. It is suggested that, not only surface treatments,

but also the development of an advanced HfO2 ALD process, has a great

impact on the quality of the III-V MOS interface and the IPA-based HfON

interfacial layer might have great potential in future technology node.

79

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8, pp. 974-977, 2016.

[93] É. O’Connor, K. Cherkaoui, S. Monaghan, B. Sheehan, I. Povey, and

P. Hurley, “Effect of forming gas annealing on the inversion

response and minority carrier generation lifetime of n and p-In0.

53Ga0. 47As MOS capacitors,” Microelectronic Engineering, vol. 147,

pp. 325-329, 2015.

[94] É. O’Connor, S. Monaghan, K. Cherkaoui, I. M. Povey, and P. K.

Hurley, “Analysis of the minority carrier response of n-type and p-

type Au/Ni/Al2O3/In0.53Ga0.47As/InP capacitors following an

optimized (NH4)2S treatment,” Applied Physics Letters, vol. 99, no.

21, pp. 212901, 2011.

89

Chapter 3. Fabrication and

Characterization of InGaAs

MOS-FETs

3.1. Introduction

It is clear that study of III-V MOS interface is the most fundamental

and important task in realization of high performance III-V MOSFET and

great effort to achieve high quality high-k/InGaAs MOS interface has been

dedicated in the previous chapter. However, study of basic MOSCAP

structure only provides limited information of the actual MOSFET therefore;

design and optimization in actual III-V MOSFET device must be

demonstrated as well.

As briefly discussed, several planar device architectures for III-V

MOSFET have been studied (Fig. 3.1). The simplest architecture is the

inversion-mode device, which is an equivalent of a traditional bulk Si

MOSFET. It is consisted of inversion channel formed under MOS interface

and Si donor implanted S/D contacts. However, III-V interface generally

suffers from high defect densities hindering inversion characteristics [1].

Also, S/D implantation in III-V substrate raises problems such as increased

access resistance, implant damage defect, and thermal budget issues [2, 3].

In order to avoid the related issues, undoped n-InGaAs channel with

regrown highly-doped S/D technology is introduced [4]. This architecture

90

can mitigate the access resistance and easier carrier control is available by

carrier confinement with wide bandgap material underneath the channel.

Also, in device characterization point of view, this accumulation-mode

structure is preferable for evaluation, because it is difficult to achieve the

intrinsic carrier mobility in inversion-mode III-V MOSFETs [5, 6]. This

architecture is usually demonstrated in HEMT technologies and the specific

material structure and material growth technique will be further discussed

throughout this chapter.

Figure 3.1 Schematic of (a) inversion mode and (b) accumulation mode

InGaAs MOSFETs.

Furthermore, with the continuation of gate length scaling, it is well

known that the conventional planar structure MOSFETs have limitations

such as increase in short channel effect (SCE) and leakage current [7]. In the

case of III-V channel MOSFETs, these limitations in short gate length

transpire more seriously. Therefore, recently in order to overcome these

issues, three-dimensional structure MOSFETs especially FinFET was

proposed [8]. The research and development of high performance FinFETs

have cleared a path to the III-V FinFET study with specific issues related to

the material properties, which would be further discussed.

91

3.2. Process Flow

The typical epitaxial structure of the recessed-type wafer is composed

of a semi-Insulating InP substrate, a thick In0.52Al0.48As wide-gap buffer

layer for off-leakage reduction, a thin 10 ~ 15 nm InxGa1-xAs (x : 0.53 ~ 0.7)

channel for efficient gate control, a thin InP etch stop and a highly-doped

N+ InGaAs capping for low resistance.

There are 2-types of fabrication method of InGaAs MOSFETs studied

on this thesis. First, recessed-type structure InGaAs MOSFETs were

fabricated by performing a gate recess step that etches the highly doped

capping layer on the gate area [9]. Due to the isotropic wet etching

characteristics used to avoid etching damage during the gate recess process,

the recessed type MOSFETs were designed for long gate length devices in

order to evaluate the fundamental properties of InGaAs MOSFETs such as

the gate stack quality, the III-V wafer quality and the fabrication technology.

The detailed fabrication process is as the following. First, mesa isolation

was performed using H3PO4 based wet etching deep enough to isolate the

active region. Then, selective gate recess step was performed by citric acid

based solution using a SiNx mask. It is worth to mention that the dielectric

mask is preferred to avoid the carbon contamination issue, which occurs in

the case of ordinary PR mask. To further etch the InP etch stop layer and

clean the surface, HCl based digital etching were performed. The digital

etching step is composed of oxidation step in 20W O2 plasma on the

microwave asher and etching step in diluted HCl (1:3) 1 min. The etch-rate

is about 0.9 nm/cycle and 3 cycles were performed. Then for the pre-

treatment step before dielectric deposition, 3 min of NH4OH (29 %) and 20

min of (NH4)2S (10 %) was performed as optimized in the MOS-Cap

92

experiments. The HfOxNy gate insulator was deposited with the optimized

condition described in the previous chapter. Then after Pt/Au gate

deposition by lift-off process, PMA was carried out at 400 ºC for 30 min in

forming gas ambient (N2 95%, H2 5%). Finally, low contact resistance

Pd/Ti/Pt/Au ohmic metal stack was deposited after dielectric opening.

Figure 3.2 Schematic of the process flow of InGaAs QW MOSFETs

fabrication.

93

On the other hand, regrown-type structure InGaAs MOSFETs were

fabricated by performing a S/D regrowth step that grows the capping layer

without the dummy gate patterned area [9]. The regrown-type MOSFETs

were developed to improve the gate recess process without isotropic features

for short gate length devices. To define the short gate length region, first the

gate area is patterned by e-beam lithography with hydrogen silsesquioxane

(HSQ) and then S/D region is regrown in a MOCVD chamber on this thesis.

The regrowth process is used to evaluate the short gate length device

characteristics, the capping layer optimization. The detailed fabrication

process of regrown-type devices is similar to that of recessed-type devices,

and the single difference is that the gate recess process is substituted to the

S/D regrowth process. However, as the regrowth process is exposed to a

high-temperature ambient in the MOCVD chamber, the dummy gate process

creates some contamination issues and affects the gate stack quality [10]. In

order to solve this problem, before HSQ coating, 10 nm of thin SiNx layer is

deposited at the ICP-CVD chamber and after HSQ patterning the SiNx is

opened by low power SF6 plasma. By the developed process, as

SiNx/InGaAs has higher thermal stability than HSQ/InGaAs and the HSQ

contamination is effectively stripped on the underlying SiNx stripping

process, the InGaAs channel surface was well protected until the gate

dielectric deposition process.

94

Figure 3.3 SiNx capping technology to protect the InGaAs surface (a) HSQ

capped and (b) SiNx capped.

95

3.3. Characterization of HfOxNy/InGaAs MOS-

FET

In the previous chapter, successful development and characterization

of high-quality high-k dielectric deposition process was demonstrated for

III-V substrate. The focus of gate stack study was mainly oriented to the

interface quality improvement; however, a reliable gate stack along with

excellent interface properties is also a major issue for logic devices [11, 12].

Not only the defect that resides in the interface but also the high-k dielectric

bulk quality itself has great impact on both the device performance and

operating lifetime [12, 13]. In order to analyze the reliability characteristics

of the device, BTI (Bias Temperature Instability) measurement is generally

performed to observe the Vth shift in MOSFETs [11, 14]. The basic

mechanism of BTI measurement is that the positive Vth shift is due to

positive gate stress induced by high electrical field leading to oxide charge

trapping and even generation of new trap states. Although full

comprehensive understanding of BTI related trap characteristics in III-V

gate stack such as non-Arrhenius trapping features [15] is still on

investigation, it provides sufficient amount of analytical information on the

gate stack reliability in the aspect of operation life time and failure.

Direct deposition of HfO2 on InGaAs substrate has been difficult with

large density electron traps and the approach to employ bi-layer high-k

schemes with the optimized interface layer (IL) has become the common

strategy to address the goal of thin effective-oxide-thickness (EOT) and

good interface quality simultaneously [16-19]. Among several IL candidates,

Al2O3 has been the dominant high-k IL in III-V MOS research due to its

strong advantage of ‘self-cleaning effect’ [16, 20]. Despite employing Al2O3

96

has accomplished the excellent interface passivation results in wide

literatures, the issues concerning the oxide reliability are still unresolved

[21]. Recently, it was reported that the polycrystalline AlN is effective to

passivate the III-V surface dangling bonds in conjunction with a substantial

improvement in the gate stack reliability [22]. Also, the most advanced

results were recently reported by using the combination of unknown ALD IL

material which has been developed at ASM referred to as ASM-IL (κ-value

~ 6) and LaSiOx on the InGaAs substrate [19]. It was suggested that the

developed IL forms a more favorable defect band distribution and a further

reduction on the oxide defects. In this work, a bi-layer ALD high-k gate

stack scheme that is consisted of an IPA-based HfOxNy IL and an O3-based

HfOxNy bulk layer is proposed and characterization of the gate stack was

performed to optimize the bi-layer gate stack.

97

3.3.1. Bi-layer HfOxNy Gate Stack

Even though HfO2 has been regarded as the most promising high-k

candidate to replace SiO2 in various electronic devices, a large density of

intrinsic electron traps mainly generated from the oxygen vacancies within

HfO2 have severely degraded the oxide reliability. In our previous work, the

excellent interface characteristics could be achieved with the optimized

plasma-assisted atomic-layer-deposition (PA-ALD) HfOxNy process [23].

Noticeable trade-off relationships in terms of the bulk and interface quality

between the O3 and Isopropyl-alcohol (IPA) based HfOxNy exists

respectively. In order to achieve a reliable gate stack, the trade-off

relationship in the HfOxNy processes should be optimized. In this work, a

bi-layer ALD high-k gate stack scheme that is consisted of an IPA-based

HfOxNy IL and an O3-based HfOxNy bulk layer is proposed. The proposed

gate stack might have strong potential in achieving not only an excellent

interface quality but also an improvement in reliability performance. Also,

as most IL candidates have lower dielectric constant compared to HfO2, our

work might have better EOT scalability compared to the previous III-V

MOS research.

Table 3.1 Description of III-V MOS Gate stacks.

Sample Bi-layer high-k design

(IL) IPA-based HfOxNy (Bulk) O3-based HfOxNy

Ref. 0 cycle 30cycle

A 5 cycle 25 cycle

B 10 cycle 20 cycle

C 30 cycle 0 cycle

98

The gate stacks studied in this work are described in Table I. Details

of the pretreatment and high-k deposition processes are described in our

previous work [23]. The total ALD deposition cycles were maintained to 30

cycles targeting a 3 nm oxide thickness for all samples. The bi-layer gate

stack is consisted of IPA-based PA-ALD HfOxNy for the interface and O3-

based PA-ALD HfOxNy for the bulk. The IPA-based HfOxNy IL is expected

to exhibit the most improved interface characteristics attributed to both the

low surface oxidation ability of IPA and the suppression of oxygen diffusion

by effective nitrogen passivation at oxygen vacancies in HfO2. On the other

hand, O3-based PA-ALD HfOxNy has better bulk characteristics due to the

stronger oxidation ability of O3 oxidant. Therefore, the optimum point

would be the thickness that is thick enough to fully protect the InGaAs

surface and thin as possible for the reliability improvement.

Figure 3.4 Schematic diagram of the fabricated InGaAs MOSFETs.

99

Quantum-well InGaAs MOSFETs were fabricated and the

schematic of the designed device is shown in Fig.1. The epitaxial III-V

MOSFET material structure is composed of a semi-insulating InP substrate,

a thick In0.52Al0.48As buffer, a Si-delta doping layer under the channel, a 10

nm In0.7Ga0.3As channel,, a 3 nm InP etch stop layer, and a highly doped

capping layer. The capping layer is consisted of a 20 nm n+ In0.52Al0.48As

(Si-doped, 2x1019 cm-3), a 15 nm n+ In0.53Ga0.47As layer (Si-doped, 3x1019

cm-3), and a 10 nm n+ In0.7Ga0.3As layer (Si-doped, 3x1019 cm-3).

The process flow of MOSFET fabrication is as following. The mesa

isolation was first performed with phosphoric acid wet etching. Then

selective gate recess was done with citric acid using a SiNx dielectric mask.

Then after removing the SiNx mask, 4 cycles of digital etching based on

sequential O2 plasma and HCl etching were performed to etch the InP etch

stop layer. After high-k deposition, Pt/Au gate metal contact was deposited

by lift-off process and post metallization annealing was carried out at 400 ºC

for 30 min in forming gas ambient (N2 95%, H2 5%). Finally, Pd/Ti/Pt/Au

ohmic metal stack was deposited after the high-k dielectric opening.

100

3.3.2. Device Results

The ID-VG transfer characteristics of InGaAs QW MOSFETs are shown

in Fig. 3.5 for all samples. Excellent device characteristics were achieved

for IPA-HfOxNy IL employed samples compared to the reference sample as

expected. In Fig. 3.6, it was noted that improvement in the aspect of on/off

ratio was achieved by on-current improvement through the IL insertion

reaching ~ 106 at VD = 0.5 V (A and B). However, slight off-current

degradation occurred for the single-layer IPA-based HfOxNy gate stack (C)

due to the gate leakage increase. Moreover, the threshold voltage (Vth)

negative shift phenomenon as gate length decreases which is often referred

as the Vth roll-off is effectively suppressed through the IL insertion as shown

in Fig. 3.7. The Vth is extracted using the linear extrapolation method at

maximum Gm bias. The amount of negative Vth shift decreases as the IL

thickness increases and it saturates at the IL thickness of 1 nm. The Vth roll

off effect is almost negligible in sample B and C. Also, it was observed that

remarkable subthreshold-slope (SS) improvement is achieved by employing

our developed IPA-based HfOxNy layer (Fig. 3.8). The extracted SS values

at the gate length of 20 μm on VD = 0.5 V are 77, 76, and 72 mV/dec and on

VD = 0.05 V are 72, 70, 68 mV/dec for sample A, B and C respectively. This

result represents that the developed IL technology achieves extraordinary

interface quality comparable to the best results reported [19]. Also, as it is

shown in the insets of Fig. 3.5, the Gm,max increases as the IL thickness

increases and saturates at the IL thickness of 1 nm. These results suggest

that at least 1 nm IL deposition shows similar interface results to the single-

layer IPA-based HfOxNy result indicating that 1 nm IL deposition is the

optimum point for the InGaAs surface passivation.

101

102

Figure 3.5 The ID-VG transfer characteristics with gate length (LG) = 5, 10,

20 μm of (a) ref. (b) A (c) B and (d) C measured at VD = 0.5 and 0.05 V;

Insets represent the linear ID-VG of LG = 5 μm measured at VD = 0.5 V.

103

Figure 3.6 On/off ratio comparison of varied gate stacks measured at VD =

0.5 V.

Figure 3.7 Vth roll off effect of varied gate stacks measured at VD = 0.05 V.

Ref. A B C0.00

0.05

0.10

V

th,l

in (

@ V

D =

0.0

5 V

) [V

]

LG = 5 m

LG = 10 m

relative to LG = 20 m

104

Figure 3.8 Minimum SS for varied gate stacks in terms of gate length

measured at (a) VD = 0.5 V (b) VD = 0.05 V.

105

These results suggest that 0.5 nm IL deposition is not enough and at

least 1 nm IL deposition shows similar interface results to the single-layer

IPA-based HfOxNy result indicating that 1 nm IL deposition is the optimum

point for the InGaAs surface passivation.

For detailed interface analysis, the multi-frequency (1 kHz – 1 MHz)

C-VG measurement is performed at ring shape device and the results are

shown in Fig. 3.9. The capacitance-equivalent thickness (CET) is extracted

considering the semiconductor capacitance of the III-V substrate [24].

Significant improvements in both CET and frequency dispersion are

achieved through the IL insertion. As the IL thickness gets thicker, the CET

decreases up to 1.04 nm (B) and this value is identical to sample C. This

CET improvement has definite impact on the electrical characteristics

regarding the Vth roll off and Gm,max results and a pattern is noted that with

IL insertion, definite improvement in electrical characteristics are observed

and it saturates at 1 nm IL deposition. Furthermore, distinct frequency

dispersion suppression is observed through IL deposition and the

accumulation dispersion value, in particular, shows that most improved

result is obtained at sample B. It implies that the proposed bi-layer approach

successfully benefits from both bulk and interface quality of O3 and IPA

based HfOxNy. In Fig. 3.10, the Dit distribution extracted by the conductance

method is compared for all samples. Higher mid-gap Dit value over 1012 eV-

1cm-2 is observed for the reference sample, and by IL insertion, remarkable

mid-gap Dit decrease occurs reaching 3 x 1011 eV-1cm-2 which is consistent

with the SS values. In conclusion, in terms of device performance, the

optimum IL thickness appears to be 1 nm similar to the single-layer IPA-

based HfOxNy results.

106

107

Figure 3.9 The multi-frequency C-VG characteristics of sample (a) ref. (b) A

(c) B and (d) C.

108

Figure 3.10 Dit distribution of varied gate stacks extracted by conductance

method.

In addition, positive bias temperature instability (PBTI) measurements

are further investigated for sample B and C in order to explore the

advantage of using bi-layer gate stack scheme. PBTI stress measurements

were performed using the measure-stress-measure technique under various

positive gate stress voltages. The amount of threshold voltage shift under

high gate stress bias represents the electron trapping rate in defects located

at the interfacial layer and the bulk high-k dielectric. Fig. 3.11 shows the

ΔVth of InGaAs QW-MOSFETs as a function of stress time with varied gate

stress voltages. The bi-layer gate stack approach (B) exhibits much lower

threshold voltage shift under similar VG - Vth stress. Also, the power law

time exponent (n) which represent the trap generation rate and electron

trapping rate significantly reduces from 0.18 to 0.11 on high gate stress bias

0.15 0.20 0.25 0.30 0.3510

11

1012

Ref.

A

B

C

Dit [

eV-1cm

-2]

Ec - E

t [eV]

109

as the IL layer is inserted.

Moreover, based on the PBTI measurements, the 10 year lifetime

reliability is extrapolated from the time to ΔVth = 30 mV shift at various

gate stress conditions (Fig. 3.12). The maximum operating voltages (VOV)

that ensure 10 year reliability are 0.49 V and 0.32 V for sample B and C,

respectively. It is worth mentioning that the max. VOV targets of VDD = 0.5

V and 0.75 V are 0.33 V and 0.5 V, respectively [24] and the proposed bi-

layer gate stack achieves these values successfully even on such low CET.

Figure 3.11 Stress time evolution of threshold voltage shift under varied

PBTI stress for sample B and C.

100

101

102

10310

-3

10-2

10-1

n ~ 0.18

n ~ 0.18

n ~ 0.24n ~ 0.11

n ~ 0.12

Vth s

hif

t [V

]

Stress time [sec]

VG - V

th = 0.6 V

VG - V

th = 0.8 V

VG - V

th = 1.0 V

n ~ 0.14

Blue : Sample B

Black : Sample C

110

Figure 3.12 The lifetime extrapolation with varied gate stress for sample B

and C.

In addition, the trapped charge density (ΔNeff, ΔNeff = ΔVth x Cox/q) is

evaluated on the stress time of 1 sec (Fig.10) as a function of effective oxide

field (Eox, Eox = (VG - Vth) / CET). In order to ensure reliable device

operation, the maximum ΔNeff should be less than 3 x 1010 cm-2 at the

operating field (Eox = 3.5 MV/cm) for an EOT 1nm gate stack [24]. For

sample B, great reduction of ΔNeff to 1.3 x 1010 cm-2 at Eox = 3.5 MV/cm is

achieved by the bi-layer gate stack approach. Also, the electric field

acceleration exponent (γ), which represents the oxide defect level

distribution [24], increased from 1.45 to 2.0 suggesting that the defect bands

improved.

111

Figure 3.13 Trapped charge density as a function of Eox for sample B and C.

In addition, in order to study the fast transient traps within the high-k

dielectric, fast transient charging effect (FTCE) [25] was further

investigated for sample B and C. This effect is known to be caused by the

shallow traps below the HfO2 conduction band in very fast charging times.

The pulse signal is designed as shown in Fig. 3.14. A fast transient bias

increase is given as a gate bias from the off-state bias to the on-state bias

and a certain amount of time of constant gate stress bias is applied. Then, a

fast transient bias decrease from the on-state bias to the off-state bias. The

pulse time configuration is rising time (tr) = falling time (tf) = 2 μs, and

pulse width time (tpw) = 100 μs.

112

Figure 3.14 Pulse time configuration of FTCE.

As the PBTI measurement can not estimate the shallow traps which

only reacts at fast charging times [25]. The fast transient charging

measurements were performed, and only the shallow traps are able to

response and the amount of the traps are estimated through the Vth

hysteresis. The transfer curves of the FTCE measurements of InGaAs QW

MOSFETs are shown in Fig. 3.15 with varied max. gate biases. It clearly

shows that hysteresis of the bi-layer gate stack is much smaller than the

single layer HfON layer in same gate stress bias. For detailed analysis, the

amount of hysteresis is calculated and shown at Fig. 3.16. While sample B

exhibited small hysteresis even in high gate biases, sample C resulted in

large hysteresis which implies that the IPA-HfOxNy single gate dielectric

suffers from the shallow traps.

0.0 10.0µ0.00

0.05

0.10

100.0µ 110.0µ

tf

tr

I D [

mA

/m

]

time [sec]

tr = t

f = 2s

tpw

= 100 s

tpw

113

Figure 3.15 FTCE characteristics of (a) Sample B and (b) C with varied

gate biases.

114

Figure 3.16 Hysteresis of (a) Sample B and (b) C with varied gate biases.

In Table II, the device properties of various III-V MOS gate stacks are

benchmarked [19, 21, 22]. In the early stage of research, although Al2O3

reported great interface characteristic, it certainly lacked the reliability

performance [21]. Among the proposed technologies, the bi-layer high-k

design developed in this work demonstrates the most outstanding

performance in all aspects. It is believed that the proposed IPA-HfON IL bi-

layer gate stack could suggest a path to establish high performance III–V

MOSFETs with reliable gate stacks to fulfill the stringent requirement for

energy-efficient nanoscale MOSFETs.

In this work, we have proposed a high quality IPA-based PA-ALD

HfOxNy IL technology and presented excellent device performance along

with great reliability improvement. By IL insertion, low SS is achieved with

0.8 1.0 1.2 1.40.00

0.05

0.10 Sample B

Sample C

Vth

[V

]

VG,max

- VT [V]

115

reduced Vth roll-off, Gm improvement and low CET. Also, significant mid-

gap Dit reduction was observed which attributed to the excellent sub-

threshold performance. In addition, through PBTI measurements, the

proposed gate stack achieved stringent BTI reliability targets and clear

advantage of using bi-layer gate stack scheme is reported. In summary, we

believe that the developed HfOxNy IL has great potential over the low-k IL

materials and it could contribute to the most advanced III-V MOSFETs for

future technology node.

Table 3.2 Benchmarking of III-V MOS Gate stacks

Research

Device properties

LG

[μm] Dielectric

CET

[nm]

SSmin

(@ VD = 50 mV)

[mV/dec]

Max.

VOV

[V]

IMEC (2014) 20 Al2O3 5.3 77 0.23

IMEC (2018) 50 ASM-IL /

LaSiOx / HfO2 1.46 68 0.43

NCTU (2016) 6 AlN / HfO2 1.4 120 0.41

Sample B

(This work) 20

HfON (IPA) /

HfON (O3) 1.04 70 0.49

Sample C

(This work) 20 HfON (IPA) 1.04 68 0.32

116

3.4. MOCVD-grown InGaAs MOS-FET

Another important aspect of achieving the feasibility of III-V channel

on logic technology node is to develop an appropriate growth method of III-

V compound semiconductor with a desirable quality [26]. As previously

discussed, MBE is the typical growth method in the III-V technology,

however it is not suitable for large size (above 200 mm) wafer growth which

is necessary for mass production in low cost [27]. Therefore, MOCVD

growth method is studied in this work as compared to MBE for practical use

of III-V channel technology in the industry.

In order to achieve sufficient quality MOSFETs, maximizing the

device on-performance and minimizing the leakage-performance would be

the fundamental task. In the aspect of III-V material structure, the capping

layer would be the key process for the on-current boosting while the buffer

layer would be the key process for the off-current suppression. In this work,

we report optimization of material quality by controlling various growth

process conditions. All MOCVD growth studies were collaborated with

KANC.

117

3.4.1. Capping Layer Optimization

It is very important to stress that achievement of lower contact

resistance gets highly challenging with continued device dimension scaling

and since its relative contribution to the source and drain resistivity (RSD)

increases, the difficulty of achieving the ITRS requirement gets higher [28,

29]. Also, in order to attain ultra-low contact resistance in the metal/n-type

III-V contact, using low work function metal contact usually does not help

due to the Fermi-level pinning issue [30], which frequently occurs in

defective III-V surface. Therefore, maximizing the doping concentration and

activation of those dopants is the major challenge in III-V ohmic contact

study [31].

There are several techniques to control the doping concentrations in

III–V materials. Ion implantation is the most common method however has

issues of requirement of high temperature annealing which is critical to low

thermal budget of III-V MOS and structural implantation damages induced

by large energy ion implantation that have not been annealed out in the

range of activation annealing [32, 33]. On the other hand, there are some

difficulties such as chemical solubility limited activation, co-implantation,

amphoteric limited compensation, point defect limited activation in epitaxial

doping growth method, it generally results in the highest n-type doping

concentrations in InGaAs even without specific activation annealing [31, 34,

35]. In MBE growth, the doping simultaneously in the growth process can

be easily accomplished due to the ability to perform the III-V capping layer

growth at low temperatures which are normally non-equilibrium doping

conditions. Many studies report low growth temperature highly doped

InGaAs growth which generally results in higher n-type dopant activation

118

above 1.0E+19 cm-3 while the high growth temperature results in

deactivation phenomenon in heavily doped substrates [31, 34, 36]. This is

likely to occur due to the dopant-vacancy complex and dopant-dopant

complex formation.

The MOCVD growth, on the other hand, is often not available to

change the growth temperature freely than the MBE growth method. It is

due to the growth mechanism of MOCVD occurs near thermodynamic

equilibrium while MBE does not and therefore, smaller growth temperature

window is opened for the MOCVD growth making the optimization of

process condition more difficult. Low temperature MOCVD epitaxial

doping approach is studied in this research with adequate material quality.

Moreover, in most research of III–V semiconductor systems, Si was

used as the most common n-type dopant [37-39]. It is known that the group

IV semiconductors such as C and Si act as amphoteric dopants that replace

either a group III or group V sublattice site and generally the amphoteric

dopants suffer from significant amphoteric limited compensation [39]. The

reported carrier concentration values of Si doping is only around mid-1018

cm-3, and some report that reach high carrier concentrations beyond 1.0 x

1019 cm-3 also suffer severe diffusion issues. In order to overcome the

amphoteric doping limitation issue, Group VI dopants such as S, Se, and Te

have been studied for n-type dopant candidates in InGaAs [31]. However,

diffusivity of S is very high and it raises issue of junction steepness on III-V

material system that might affect the subthreshold characteristics of device

while Se and Te have exhibited limited diffusivity [40]. Te dopant is studied

with comparison of Si dopant in this research and the goal is to achieve both

high doping concentration with steep junction interface.

In order to optimize the capping layer design, a regrowth type III-V

119

MOSFET is fabricated. In the early work of capping layer growth, severe

degradation of device on-resistance (Ron) was observed. It was found that

the high Ron is due to the SD resistance degradation which led to detailed

investigation of capping layer growth.

Figure 3.17 Achieved dopant concentration in terms of the dopant flow rate.

First of all, the effect of Si and Te dopant in N+ InGaAs growth was

compared in Fig. 3.17. It was observed that Si doping is not effective to

achieve high doping levels and it only reached the doping levels of late 1018

cm-3, while high doping levels of late 1019 cm-3 with Te doping. Therefore,

using Te dopant in the following experiments was certain, however, there

were some reports regarding the Te dopant related issues such as the growth

temp. [35, 41] and the over-saturated doping levels [35].

The growth temperature plays a significant role in the SD resistance as

expected. In order to evaluate the capping layer quality, the contact

resistance was extracted by a TLM method in Fig. 3.18. The best contact

0 20 40 60 80 1001E17

1E18

1E19

1E20

Te-Hall

Si-Hall

Do

pa

nt

Co

nce

tra

tio

n (

/cm

3)

Normalized Dopant flow rate (sccm)

120

resistance value is estimated of 0.05 ohm∙mm in the case of using Te dopant

at low growth temperature. While, better III-V material quality was easily

achieved in higher growth temperatures, a trade-off relationship was shown

for the contact resistance. It is concluded that the contact resistance has clear

correlation to the growth temperature. Moreover, the RSD that was extracted

from a linear extrapolation from the transistor Ron-LG plot (Fig. 3.19), and

by further decreasing the growth temperature the RSD significantly decreases

reaching almost 278 ohm∙μm. It is assumed that in high temperatures, the Te

dopant forms a Te-Te complex which acts as a point defect that deactivates

the dopant as previously discussed [42]. Therefore, the highly doped

InGaAs growth recipe was optimized on 500 oC.

Figure 3.18 TLM results in terms of growth temperature and dopant type.

121

Figure 3.19 Ron extracted from the fabricated transistors in terms of gate

length and RSD extracted from the Ron-LG plot.

Figure 3.20 The transfer curve of the fabricated short channel III-V

MOSFET with highly Te-doped capping layers (a) log-scale and (b) linear-

scale.

122

When adopting high doping levels of Te dopant in the capping layer,

significant increase in drain current and transconductance can be achieved

as shown in Fig. 3.20. However, the issue of over-saturated doping levels is

known to impact severe dopant diffusion which rise difficulties such as SS

degradation in III-V devices. Therefore, we have studied different types of

capping layer design altering the dopant type and doping concentration. In

the TLM results, there were strong correlation of current level and capping

layer resistance to the doping concentration. Also, analysis of SS, On-

current, Rcap in terms of doping concentration is performed in the MOSFET

results (Fig. 3.22). The table 3.3 shows the sample split in order to find out

the effect of doping layer concentration. In Fig. 3.22, the SS value, which is

directly affected on the dopant diffusion effect, shows positive correlation to

the bottom layer doping concentration. It is assumed to be that as lowering

the bottom layer doping concentration, the dopant diffusion effect is clearly

improved. However, SS is not only affected by the off- current decrease but

also affected by the on-current difference. So, the 2-step doping results show

better SS. In terms of the on-current characteristics, there is strong tendency

to the inverse of Rcap as estimated. In addition, the Rcap is strongly

dependent to the total effective doping concentration of the capping layer. In

conclusion, in order to prohibit the dopant diffusion effect the doping

concentration has to be maintained under the oversaturated doping level.

123

Figure 3.21 Capping layer resistance extraction varied with doping

concentration.

Table 3.3 Varied capping layer design effect on current and Rcap.

124

Figure 3.22 Capping layer effect on MOSFET performance (a) SS (b) on

current (c) Rcap vs top doping concen. and (d) Rcap vs effective doping

conen..

125

We have found out that mid 1019 cm-3 level of Te doped InGaAs

growth is sufficient for minimum dopant diffusion and due to lowering the

doping level, there could be a slight degradation in the contact resistance. So,

we have designed the capping layer to avoid this issue by engineering the

III-V band-gap. With higher In contents, the band-gap of InGaAs decreases

and at the channel/cap interface, it may degrade the on/off performance by

lowering the barrier [43] however, at the cap/ohmic-metal interface, it

improves the contact resistance [44]. Therefore, a bi-layer capping layer that

is composed of highly-doped InGaAs (In : 53%) and highly doped InGaAs

(In : 70%) surface is designed. In Fig. 3.23, compared to the single layer

capping layer without the band gap engineering, the RSD decreased to 249

ohm∙μm successfully.

Figure 3.23 Effect of bi-layer capping layer design on Ron and RSD.

126

3.4.2. Buffer Optimization

In III-V epitaxial growth, different III-V material growth with lattice

matching is available by engineering the elements. While InGaAs channel

exhibits high carrier mobility, its low band-gap property raises issue of off-

leakage increase and to avoid this issue, In0.52Al0.48As, which lattice

constant is matched to In0.53Ga0.47As, is often employed right underneath the

thin channel layer [45, 46].

The growth temperature also plays a significant role in the resistivity

of InAlAs growth [47, 48]. In general, high temperature growth improves

the InAlAs quality by reducing the impurities and making Al atoms move to

the desired site due to higher mobility. However, the InAlAs layer in this

study has to serve as a buffer layer and its resistivity has to be high enough

in order to reduce the leakage path. In the process of InAlAs growth, it is

reported that C, an amphoteric dopant, is unintentionally incorporated into

InAlAs and act as a p-type dopant. These C impurities reduce in high

temperature, however, decreases the resistivity as InAlAs is normally grown

n-type because the carbon compensates the n-type background impurities in

InAlAs buffer [48]. Therefore, low temperature (LT) InAlAs buffer layers

grown lattice matched to InP substrates tends to have high resistivity suited

for our study.

The growth temperature is split for the InAlAs buffer growth in Fig.

3.24. In high temperatures, high buffer leakage current of 10-6 A/μm at 1 V

is observed which is reflected to high off-currents in the device. Great

reduction over 4 decades is achieved with 500 oC buffer growth temperature.

127

Figure 3.24 Buffer leakage in terms of buffer growth temperature.

We have fabricated a MOCVD-grown InGaAs MOSFET by using all

the optimized growth process. The InAlAs buffer and the n+ InGaAs

capping layer were grown on 500 oC. The channel thickness is 15 nm with a

In percentage of 53% and the grown epitaxial layer is shown in Fig. 3.25.

By using this material, the III-V MOSFET was successfully demonstrated

and the transfer characteristics of MOCVD-grown InGaAs MOSFETs are

shown in Fig. 3.26. The optimized MOSFETs exhibited the on/off ratio over

106 for all gate length that implies great material quality. Also, the

subthreshold slope characteristics are shown in Fig. 3.27. The device

exhibited a minimum SS of 70 mV/dec at VDS = 50mV which is comparable

to any III-V MOSFET result ever reported. Also, in comparison to the

similar material structure grown by MBE, the device on-performance of the

128

Figure 3.25 Lattice matched InGaAs epitaxial layer grown by MOCVD.

Figure 3.26 Log-scale transfer characteristics of the fabricated InGaAs

MOSFETs with varied gate length.

-0.2 0.0 0.2 0.4 0.6 0.8 1.010

-11

10-9

10-7

10-5

10-3

I D [

A/

m]

VG [V]

500 nm

1 m

2 m

5 m

10 m

20 m

Filled : VD = 500 mV

Open : VD = 50 mV

LG

129

Figure 3.27 The subthreshold slope characteristics of the fabricated InGaAs

MOSFETs with varied gate length and drain bias.

MOCVD grown III-V MOSFET is comparable to the MBE-grown InGaAs

MOSFET results and it is shown in Fig. 3.28. The transconductance and the

drain current of the MOCVD grown device is similar to those of the MBE

grown device results. Also, by benchmarking the device results to the best

device performance reported in the field (Fig. 3.29), we believe that the

reported MOSFET results show great potential of MOCVD grown III-V

technology that would be helpful to the field of CMOS integration.

0 5 10 15 20 25

60

70

80

90

MOCVD, VD = 0.5V

MOCVD, VD = 0.05V

MBE, VD = 0.5V

MBE, VD = 0.05V

SS

[m

V/d

ec]

LG [m]

130

Figure 3.28 Device On-performance comparison to the MBE-grown

InGaAs MOSFET with similar material.

Figure 3.29 Benchmarking of the fabricated planar type InGaAs MOSFET.

-0.2 0.0 0.2 0.4 0.6 0.8 1.00.00

0.04

0.08

0.12

I D [

mA

/m

]

VG [V]

Both no delta doping

MOCVD (In 53%, 15nm)

MBE (In 70%, 10nm)

60 70 80 90 100 110

104

105

106 This work

[5] LG = 1 m

LG = 0.5 m

[4] LG = 300 m

[3] LG = 0.25 m

[2] LG = 0.2 m

<MBE>

[1] IMEC (IEDM 2013)

[2] Intel (IEDM 2009)

[3] IBM (IEDM 2012)

[4] MIT (Thesis of J.Lin 2015)

<MOCVD>

[5] TSMC (VLSI 2015)

This work

On

/off

ra

tio

at

VD =

0.5

V

SS at VD = 0.5 V [mV/dec]

[1] LG = 10 m

131

3.5. Three-dimensional InGaAs MOS-FET

As severe degradation of electrostatic performance in short gate length

is observed for the developed III-V MOSFETs compared to the Si

MOSFETs at the same transistor dimension [49-52], it is important to

explore the feasibility of III-V channel transistors for the extremely scaled

gate dimension node. There are multiple explanations regarding this matter,

and first, the design of S/D capping layer in the fabricated device should be

improved. The highly-doped InGaAs cap used in the thesis is rather a simple

structure designed for large gate length III-V devices for demonstration.

However, the highly doped small band-gap InGaAs layer without a spacer

layer is very susceptible to the gate field applied at the drain-side gate edge

[53]. In order to mitigate this issue, one approach is to insert adequately

doped InAlAs or InP layer that could disperse the gate field with negligible

resistance increase or another approach is to apply a spacer between gate

and capping layer [54]. These approaches are fully demonstrated in other

studies and successful reports of improvement in SCE (Short Channel Effect)

characteristics of III-V MOSFETs are reported.

Other explanations are related to the intrinsic III-V material properties.

It is speculated that due to larger permittivity of III-V channels, effective

gate field applied to the channel decreases leading to poor gate control and

III-V MOSFETs intrinsically suffer from severe short channel effect [55].

Also, for devices with extremely short gate lengths, the direct source-drain

tunneling leakage might occur and could be more serious for III-V

MOSFETs due to smaller tunneling effective mass. Since high mobility

channels tend to have smaller band-gap energy compared to Si, off-state

leakage currents related to band-to-band tunneling are dominant for III-V

132

channel MOSFETs [56, 57]. Especially for the case of back-barrier material

system (Fig. 3.30), it is known that hole confinement from the

semiconductor back barriers prevent the hole extraction to the substrates,

leading to a large amount of holes which stay in the quantum wells and

reducing the channel potential. The decrease on channel potential acts as a

forward-bias on the source-channel junction, thus reducing the source-to-

channel barrier and increasing the leakage current and it is known as bipolar

effect. As these issues come from its material properties, it seems to be

difficult to use III-V channel in short gate length devices.

Figure 3.30 Impact of channel band-gap on BTBT current.

The effective solution for this issue is to fabricate ultra-thin body 3-

dimensional MOSFETs [58]. With the continuation of CMOS scaling, multi-

gate structure MOSFETs generally known as FinFETs were successfully

introduced to the logic technology node replacing the conventional planar

MOSFET’s to overcome SCEs and leakage current. Low cost process steps

and compatibility with CMOS are the main advantages of FinFETs which

133

attracted the semiconductor society and it became the key technology.

Beside of the obvious advantage of employing FinFET technology in III-V

technology, it has a specific advantage regarding the mentioned issue above.

First, thin body of III-V FinFET can easily mitigate the permittivity issue as

the channel thickness to control is small enough. Also, the thin body has a

larger effective band-gap and smaller DOS than the bulk due to the strong

quantization (Fig. 3.31) [56, 57, 59]. Continuous development and research

in the areas of devices and materials have lastly conveyed the III-V FinFETs

with an agreement of higher device performances.

Figure 3.31 Thin body Multi-gate FET as a solution for SCE suppression.

134

3.5.1. QW III-V Tri-gate FET

We have fabricated a QW III-V tri-gate FET as a solution for SCE

improvement as shown in Fig. 3.32.

Figure 3.32 Schematic of QW III-V Tri-gate FET.

The fin structure was fabricated with a process of dry etching (Fig.

3.33). The other process flow is identical to the recessed type MOSFETs.

The dry etching process is developed in an ICP-etcher system. The etching

recipe is consisted of a BCl3/Ar gas ambient, a pressure of 5 mtorr, an ICP

power of 400 W, and a RF power of 10 W at zig temperature of 100 oC. It is

Figure 3.33 Process flow of QW III-V Tri-gate FET.

135

known that the substrate species related chloride by-products are easily

removed in high temperatures that enhances the etch rate [60]. 5 cycles of

digital etching are followed after the dry etching in order to remove possible

dry etching damage and narrow the fin [60]. Also, ALD TiN was adopted for

the gate step coverage.

The channel layer is composed as 3 nm of In0.7Ga0.3As / 2 nm of InAs /

5 nm of In0.7Ga0.3As in order for on current boosting with channel

confinement as shown in Fig. 3.34 [53].

Figure 3.34 Schematic of the channel of the fabricated MOSFET.

Figure 3.35 Schematic of the channel of the fabricated MOSFET.

136

The fin configuration is fin width = 30 nm, fin height = 10 nm, fin

number =2 and the total width = 100 nm as shown in Fig. 3.35.

The transfer curves of LG = 60 nm InGaAs QW planar FET and Tri-

gate FET are shown in Fig. 3.36. Significant impact on the sub-threshold

characteristics are observed with the Tri-gate FET. Compared to the planar

device, successful improvement in SCE values of SS = 115 mV/dec (at VDS

= 0.05 V) and a DIBL = 240 mV/V is achieved.

In addition, the family curves of LG = 60 nm InGaAs QW planar FET

and Tri-gate FET are shown in Fig. 3.37. Significant output resistance

improvement is observed with the Tri-gate FET. This effect is due to the

DIBL effect that as drain bias increases, the threshold voltage decreases and

then increases the output current. Therefore, by employing multi-gate

structure thin body FET, improved output characteristics of III-V MOSFET

can be achieved. Although some degradation in the on-performance is

observed due to the dry etching damage, the excellent sub-threshold

performance improvement suggests great potential of III-V channel FinFET

devices.

In comparison to the Si MOSFET results as shown in Fig. 3.38 [64],

our result surpass the best on-performance of Si channel based MOSFETs

even with high strain stressor technologies at long gate length. Especially

the transconductance is much higher in the non-planar devices. However,

the severe short channel effect deteriorates the device performance of our

III-V channel based MOSFETs which remains an important issue to resolve.

137

Figure 3.36 Transfer curves of the fabricated QW-MOSFETs (planar vs Tri-

gate).

138

Figure 3.37 Family curves of the fabricated QW-MOSFETs (planar vs Tri-

gate).

Figure 3.38 Benchmarking of our fabricated III-V MOSFET results to

advanced Si MOS technologies.

139

3.5.2. ART III-V Fin-FET Demonstration

As previously discussed, many III-V production processes are

incompatible with the CMOS process and in order to enable large-scale and

cost-effective integration, CMOS compatible III-V MOSFET is inevitable.

Among the different strategies, selective epitaxial techniques have strong

potential integrating high quality III-V crystals at the desired areas [61, 62].

Aspect-ratio trapping (ART) technique is designed for narrow III-V fin

growth on the Si substrate with defect confinement along the trench

direction [63]. In this research, ART grown III-V FinFET is studied and was

collaborated with the following institutes of KANC, Yonsei Univ.,

Kyungpook National Univ., Sungkyunkwan Univ., Chonbuk National Univ.,

and Univ. of Texas Dallas.

Figure 3.39 Process flow of ART III-V fin growth.

The process flow of ART III-V FinFET is as shown in Fig. 3.39. After

a typical STI Si trench pattern is formed, a InP buffer is grown on a GaP

seed layer. Then, InP was CMP and recessed. Finally the InGaAs channel

140

layer is grown and the rest of the process flow is identical to the typical

MOSFET process. By controlling the aspect ratio, the defect dislocation can

successfully be trapped under the InP buffer. The defect trapping and defect

free InP is observed in Fig. 3.40.

Figure 3.40 TEM result of the ART III-V fin.

With the ART III-V fin growth template, demonstration of III-V ART

FinFET is performed and the device structure and the results are shown at

Fig. 3.41. Due to the small bandgap of InP buffer, the transistor suffers from

severe off-leakage which suggests that the developed ART technique is yet

immature to adopt and suppression of large buffer leakage is the critical

issue in III-V FinFET. Alternative approach such as selective etching of the

buffer and making a nanowire structure MOSFETs would be a solution.

141

Figure 3.41 (a) Schematic and (b) transfer results of the fabricated InGaAs

ART FinFET.

142

3.6. Conclusion

In this chapter, development and integration of advanced processes in

InGaAs MOSFETs were addressed. We have proposed a high quality IPA-

based PA-ALD HfOxNy IL technology and by the IL insertion, low SS is

achieved with Gm improvement and low CET. In addition, through the PBTI

measurements, clear advantage of using a bi-layer gate stack scheme is

reported achieving the stringent BTI reliability targets. The developed

HfOxNy IL has great potential over the low-k IL materials and it could

contribute to the most advanced III-V MOSFETs for future technology node.

Moreover, for CMOS integration of III-V channel, we have optimized

the MOCVD III-V growth process and fabricated a MOCVD-grown InGaAs

MOSFET by using all the optimized growth process. The optimized

MOSFETs exhibited excellent subthreshold characteristics comparable to

any MOCVD result reported. Also, the device on-performance is out-

standing even compared to the MBE-grown InGaAs MOSFET results.

Furthermore, to explore the feasibility of III-V channel transistors for

the extremely scaled gate dimension node, three-dimensional multi-gate

structure MOSFETs were fabricated. A QW III-V tri-gate FET was

fabricated and a significant SCE improvement was observed by using a high

temp. III-V fin dry etching process. Also, an ART III-V FinFET was

demonstrated in a CMOS compatible process, however, large buffer leakage

should be resolved.

143

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150

Chapter 4. Demonstration of

InGaAs NCFET by using

Ferroelectric HfO2

4.1. Introduction

As steep scaling continues, the power constraint is estimated to be

severe and the roadmap predicts that the fundamental limitation will be

reached in classical MOSFETs [1]. In Boltzmann FET theory, the

subthreshold slope has a thermal limit at room temperature, which is 60

mV/dec, and in order to pursue the scaling of supply voltage, smaller SS

should be obtained. Among different type of operation methods, a sub-

thermal subthreshold swing under 60mV /dec at room temp. can be achieved

by decreasing the device body factor (m = 1+Cs/Cox) smaller than 1 (Cs :

semiconductor capacitance and Cox : gate oxide capacitance) [2, 3].

To obtain this operation method, recently, negative capacitance (NC)

FETs using the ferroelectric (FE) materials to the gate stack have been

studied [2, 3]. It has been reported that by employing ferroelectric material

based gate stacks, the device operates in a manner of exploiting the negative

capacitance region of ferroelectric material, to get voltage step-up action of

the gate voltage. In order to full understand the nature of ferroelectric

material, the energy landscape of polarization density should be considered.

A ferroelectric is defined as a material which exhibits a spontaneous

151

polarization that can be reversed with an applied electric field [4]. It means

that as certain voltage is applied the spontaneous polarization is minimized

and the typical energy landscape is shown in Fig. 4.1 [5]. Between these two

minimum points there is a region where the capacitance becomes negative

and in other words, if the ferroelectric material can be brought near the P = 0

state, its capacitance will be negative theoretically.

Figure 4.1 Energy landscape of a general ferroelectric material and its

polarization-electric field dependence derived from the free energy.

However, employing single ferroelectric gate stack generates issue of

severe hysteresis in transfer characteristics [6] and for logic transistors to

have the identical threshold voltage for both turn-on and turn-of operation is

very important. In order to avoid this issue, a combination of a dielectric

(DE) and ferroelectric capacitor (as shown in Fig. 4.2) which is composed as

the series connection of the ferroelectric and dielectric capacitor in circuit

model is studied as a solution [7]. By matching these capacitances, the

energy landscape changes and the negative capacitance region disappears

(which is the main cause of large hysteresis) and the amplification

152

(calculated as Abs(CFE)/(Abs(CFE)-CDE)) occurs without exhibiting any

hysteresis resulting in reduced SS. In order to achieve a stable operation of

NCFET by capacitance-matching, it is known that controlling the

ferroelectricity and thickness of the FE and DE materials is important [7].

Therefore, the goal of this work is to employ ferroelectric materials to

the gate stack with the optimized IPA-based HfOxNy IL at the InGaAs

substrate proposed in the previous chapter. There are only few reports of

ferroelectric material combined InGaAs MOSFETs and they usually lack in

the interface quality. Therefore, maximizing the ferroelectricity of the FE

while maintaining the IL quality would be the main issue throughout this

chapter.

153

Figure 4.2 Combining FE and DE materials with capacitance matching.

154

4.2. Development of Ferroelectric HfO2

In order to compare the ferroelectric material candidates, several

parameters are shown in Table 4.1. The coercive field (Ec) and the remanent

polarization (Pr) are the key parameters that represent the hysteretic

behavior and functionality of a ferroelectric material [8]. Also, additional

parameters such as the scalability, the thermal budget, and the CMOS-

compatibility should be compared for actual realization of the technology

[9]. It is shown that the properties of FE-HfO2 is the most feasible material

candidate in all aspects compared to the common perovskite based

ferroelectrics. FE-HfO2 have strong advantage of scalability (FE

characteristics in few nm thickness) and CMOS compatible ALD process,

sufficient Pr, and large Ec [9]. The material properties of reported FE-HfO2

however seem to be more broad indicating that the process optimization

would be important. In specific, to integrate with III-V MOSFETs,

annealing temperature will be the most critical factor due to the low thermal

stability of III-V substrate [10] and FE-HfO2 appears to be the most

available candidate for InGaAs substrate.

Table 4.1 Properties of ferroelectric material candidates.

155

In order to achieve better ferroelectric characteristics in FE-HfO2,

doping is known to be the most common approach to stabilize t- or o- phase

HfO2 which are responsible to the ferroelectric behavior in HfO2 [11]. The

common dopants used are Zr, Al, Si, Y, Gd and La in FE-HfO2 (Fig. 4.3).

By the doping method, boosting of Pr and annealing condition is

reported however, it is not used in this work due to issue of dopant memory

effect in the ALD chamber. The use of multiple dopants in the same

chamber might degrade the IL dielectric quality therefore, it was not

available for our research.

Figure 4.3 Polarization of HfO2 with varied dopants and concentration [].

On the other hand, engineering of the FE-HfO2 capacitor fabrication

process also has a significant impact on the ferroelectricity of HfO2 (Fig. 4.4)

[9]. The key approach of making stable FE-HfO2 is to form stable t-phase

(or o-phase) HfO2 by engineering the grain size or encapsulation. Making

156

tensile stress, formation of oxygen vacancies, changing growth temperature

and capping layer effect are the well-known methods [9, 12-14] to achieve

this and these approaches are covered in this study.

Figure 4.4 Approach to achieve hysteric PE curve of FE-HfO2.

157

4.2.1. Process Optimization

In order to study the ferroelectric characteristics of HfO2, MIM

capacitors were fabricated as shown in Fig. 4.5. Sputtered TiN was chosen

for the metal encapsulation. In various reports, FE-HfO2 is achieved by

using well optimized TiN [15-17]. The effect of TiN sputtering process

condition will be discussed further. After the bottom TiN electrode

sputtering deposition, 100 cycle (10 nm) of low temperature (220 oC) ALD

HfO2 was deposited. Then, the top TiN electrode was sputtered and after

defining the gate area, fluorine based etching was performed. Finally, post

metallization annealing was done in 600 oC for 1 min.

Figure 4.5 Schematic and process flow of FE-HfO2 MIM capacitor.

It was reported that without the intentional doping of metallic elements

other than Hf, the appearance of the ferroelectricity in HfO2 thin films

through deposition temperature control can be achieved during the atomic

layer deposition [13]. In the low temperature deposition conditions, carbon

impurity concentration in HfO2 increases, and the involvement of these

impurities suppressed the lateral grain growth during the crystallization

158

thermal treatment [13]. The grain size reduction could stabilize the

metastable orthorhombic phase, whose surface and grain boundary energies

are lower than those of the room-temperature-stable monoclinic phase, by

increasing the grain boundary areas. We also adopted this approach and

have achieved FE characteristics of HfO2 on low temperature deposition as

shown in Fig. 4.6. Successful butterfly shape C-V curve was obtained which

is a unique feature of a metal-ferroelectric-metal (MFM) capacitor [18]. In

the P-E curve, the key parameters are estimated to be Ec ~ 0.85 MV/cm and

Pr ~ 4.5 μC/cm2. The carbon doping effect and the oxygen vacancy

formation may be the main mechanism enhancing the ferroelectricity of

HfO2 [13].

Figure 4.6 Butterfly CV curve and PE curve of low temp. FE-HfO2 MIM

capacitor.

Further optimization was done to characterize the ferroelectric

properties of the low temp. FE-HfO2 dielectric. As previously discussed, in

order to achieve a stable operation of NCFET by capacitance-matching, and

159

the FE dielectric thickness control is essential [7]. The properties of FE-

HfO2 MIM capacitors were investigated by varying the thickness as shown

in Fig. 4.7. As the thickness of FE layer decreases, the distance between the

maximum capacitance decreases which represents the coercive voltage [17].

Also, as the thickness of FE layer decreases, the maximum capacitance

difference which represents the polarization strength [17] increases only

until 10 nm. In Fig. 4.8, the permittivity of the FE-HfO2 was calculated

which reflects the ratio of crystallinity of HfO2. It is observed that the

maximum ferroelectricity is estimated to be achieved at the 10 nm FE-HfO2

and the same thickness is used for further study.

Figure 4.7 Butterfly CV curve of low temp. FE-HfO2 MIM capacitor in

varied thickness.

160

Figure 4.8 Permittivity of low temp. FE-HfO2 MIM capacitor in varied

thickness.

Furthermore, it has been reported that by controlling the process

conditions of the TiN sputtering, (200) phase TiN can be obtained which

affects the HfO2 phase [19] as shown in Fig. 4.9. As the N2/Ar ratio and the

deposition temperature increases, higher (200) phase TiN peak is observed

in the XRD results. Also as (111) TiN peak decreases and (200) TiN peak

increases, the resistivity of the TiN film is improved from 280 μΩ∙cm to

93.7 μΩ∙cm.

Finally, by using the optimized TiN process, the C-V characteristics are

compared in the Fig. 4.10. Enhanced ferroelectricity (~ 60 % increase) is

observed with using high quality TiN film as expected. It is clear that the

crystallinity of TiN affects the ferroelectricity of HfO2 however, detailed

analysis should be further investigated in order to identify which process

step is affected.

-3 -2 -1 0 1 2 3

16

18

20

22

24

26

28

30

Perm

itti

vit

y

Voltage [V]

7nm

10nm

13nm

15nm

161

Figure 4.9 XRD analysis of sputtered TiN with varied process conditions.

Figure 4.10 Butterfly C-V characteristics of optimized TiN capped FE-HfO2

MIM capacitors.

162

XRD characteristics of TiN capped HfO2 with and without annealing

are shown in Fig. 4.11. Before annealing, the t- or o- phase HfO2 peak was

not observed which reflects the ferroelectricity of HfO2 while, emergence of

strong t- or o-phase HfO2 peak and suppression of m-phase HfO2 were

observed after high temperature annealing. It is clear that the formation of

FE-HfO2 occurs at the annealing step and the PMA is the key process of FE-

HfO2 formation [20, 21].

Figure 4.11 XRD analysis of FE-HfO2 with and without annealing.

163

4.2.2. Thermal Stability in III-V substrate

One of the issue to achieve ferroelectricity in HfO2 especially in III-V

substrate is that low thermal budget of III-V material limits the annealing

process [22, 23]. Generally, above 400 oC, InGaAs surface are fragile and

out diffusion of In, Ga, and As occurs resulting in severe interface quality

degradation. On the other hand, in order to achieve reliable ferroelectric

HfO2, high temperature annealing is required [24]. Therefore, the optimum

annealing point should be investigated to apply at the III-V substrate. As

shown in Fig. 4.12, the thermal stability of IPA-based HfOxNy dielectric is

experimented at various high temperatures. It is clearly shown that at 600 oC,

which is the temperature we used to realize the FE-HfO2, severe stretch-out

occurs and Dit increases 6.7 times. Until 550 oC annealing, stable C-V

curves are extracted without thermal degradation. Therefore, in order to

apply at III-V substrates, increasing the thermal budget of IL or decreasing

the annealing temperature of FE-HfO2 realization is definitely required.

Figure 4.12 Thermal stability of IPA-based HfOxNy dielectric.

164

One method is to decrease the annealing temperature of FE-HfO2

formation. Optimization of FE-HfO2 at different annealing conditions are

studied in Fig. 4.13. It is noted that the ferroelectricity of HfO2 is strongly

dependent at the annealing temperature, while it is independent of the

annealing time. At low temperature of 500 oC, only small ferroelectricity is

observed and at above 550 oC annealing, definite ferroelectricity is achieved.

Therefore, it is speculated that at 550 oC annealing the ferroelectricity of

HfO2 and IL thermal stability could be achieved simultaneously. The

mechanism of FE-HfO2 formation by annealing was studied in Fig. 4.14.

The stress measurement of TiN film using a laser scanner to measure the

curvature of the wafer is performed. In the initial status (TiN capping

without annealing), a huge compressive stress (-2.5 GPa) was strained on

the HfO2 film. Then, when the annealing step was performed, substantial

stress relaxation to the tensile direction occurred. The difference of stress

(ΔStress= Stressanneal – Stressas dep) was calculated for each annealing

temperature and was 1.3, 1.8, and 2.2 GPa for 500, 550, and 600 oC

annealing.

Even in the case of 600 oC annealing, the static stress is in the direction

of compressive direction. Therefore, it is not accurate to define that the

stress itself has impact on the crystallization process and the stress change

during annealing or cooling would be the main mechanism to form

ferroelectric HfO2. Based on our results, the critical temperature (or ΔStress)

would be 550 oC (or 1.8 GPa) to obtain stable ferro-characteristics in the un-

doped low temp. ALD HfO2 process.

165

Figure 4.13 Butterfly C-V curve of FE-HfO2 MIM capacitors with different

annealing conditions.

The other method is to achieve higher thermal stability of the IL by

laminating other films such as AlN. AlN is considered to be very stable in

high temperatures compared to Al2O3 or HfO2 [25, 26] and several

AlN/InGaAs MOS research report better thermal stability [27-29]. Also, not

only the surface species out diffusion but also the film crystallization might

be the reason of the thermal instability effect [30] and the laminated AlN

could work as a disruption layer in HfO2 dielectric [31]. The IL stacks for

InGaAs MFIS capacitors are designed as shown in table. 4.2. The process

flow of the MFIS capacitors were consisted of IL deposition which is

described in chap.2 and FE-HfO2 formation. The thicknesses of IPA-based

HfON and AlN were optimized for various thick- nesses and the C-V results

are shown in Fig. 4.14. The total IL thickness were maintained at 6 nm. In a

-4 -3 -2 -1 0 1 2 3 41.5

2.0

2.5

3.0

3.5

4.0

600 oC 60sec

500 oC 30sec

500 oC 60sec

Cap

acit

an

ce [F

/cm

2]

Voltage [V]

550 oC 30sec

550 oC 60sec

166

MFIS capacitor, the capacitance amplification value is calculated as

Abs(CFE)/(Abs(CFE)-CDE) and the hysteric behavior occurs when the

denominator of the fraction becomes below zero [32]. In order to achieve a

non-hysteric behavior, the magnitude of Cox should be less than that of CFE

and they were optimized by decreasing the Cox to the accepted value (2.05

μF/cm2 when TFE = 10 nm). As a result, the samples showed no hysteresis

successfully. By a single HfON IL deposition (sample 1), severe degradation

of interface quality was observed with severe stretch-out and not able to

reach minimum capacitance. The interface quality degradation was

consistent as expected. Also, a 1 nm of AlN was laminated above 5 nm of

HfON (sample 2), and slight improvement was achieved however seem to

be not enough. It might be the IL HfON thickness is too thick yet. With 1

nm of AlN for every 2 nm HfON (Sample 3) showed the most improved

interface results which reflects great potential of AlN lamination layer. Also,

0.5 nm of AlN in sample 4 suggests that the AlN layer should be at least 1

nm.

Table 4.2 IL gate stacks for InGaAs MFIS capacitors.

167

Figure 4.14 CV curves of the fabricated III-V MFIS capaictors (a) sample 1

(b) sample 2 (c) sample 3 and (d) sample 4.

168

4.2.3. Analysis of Hysteric Behavior in III-V

MFIS-Capacitors

Although many literatures report experimental results of high

performance NCFETs [33-37], the operation is still controversial and

systematic study of these devices is required [38]. As previously discussed,

the hysteric behavior in MFIS capacitors is a typical characteristic and we

have investigated this hysteresis effect in various MFIS capacitors in order

to explore further insight in capacitance matching. The fabricated capacitors

are shown in Table. 4.3 adopting both lower annealing temperature 550 oC 1

min and AlN thin film lamination to prohibit interface degradation.

Table 4.3 Gate stacks for InGaAs MFIS capacitors.

In order to evaluate the hysteresis behavior, the applied gate voltages

were varied and it is shown in Fig. 4.15. The estimated parameter values of

the MFIS capacitors are CMIS,1 = 1.55 μF/cm2 CMIS,2 = 1.3 μF/cm2, CMIS,3 =

1.1 μF/cm2 with consideration of the semiconductor capacitance of InGaAs.

It is observed that as the Cox of IL decreases, the maximum capacitance

169

decreases from 1.3 μF/cm2 to 0.8 μF/cm2 and all values lack to achieve the

estimated MOS capacitance which may be due to insufficient ferroelectricity.

Also, as the CMIS decreases, the amount of the CV hysteresis increases

reaching almost 1.3 V. It is noted that the ΔVFB – V curve seems similar to

the P–E curve and we assume that the hysteresis value is closely related to

the polarization value. It is known that the hysteresis value is calculated

from the Pr value and the increase indicates the polarization increase [39]

However, the IL thickness increase normally means more voltage drop

across the MIS layer [40] and therefore, lower Pr is estimated for an ideal

case. In this case, as shown in Fig. 4.16, as the EOT of the IL increases, the

hysteresis increases. It is assumed that the interface effect is more critical in

this study and further investigation is required in order to understand correct

capacitance matching.

170

Figure 4.15 CV curves of the fabricated III-V MFIS capacitors (a) sample 1

171

(b) sample 2 and (c) sample 3.

Figure 4.16 Amount of hysteresis estimated in the CV curves of the

fabricated III-V MFIS capacitors.

0 5 10 15-1.5

-1.0

-0.5

0.0

EOTIL = 1.5 nm

EOTIL = 2 nm

EOTIL = 2.36 nm

V

FB [

V]

Vmax

-Vmin

[V]

172

4.3. Demonstration of FE-HfO2/III-V MFMIS-

FET

Based on the previous results, we have fabricated a FE-HfO2/InGaAs

MFMIS-FET and demonstrated a NCFET characteristics. The description of

the fabricated devices are as following. The MFM FE-HfO2 capacitor was

fabricated in the process described in Fig. 4.5. The FE thickness is 10 nm.

The MISFET was fabricated in the process described in chap. 3 and the

channel is In0.7Ga0.3As 10 nm without Si delta-doping. The oxide is

consisted of optimized IPA-based HfOxNy described in chap. 2. The MFM

FE-HfO2 capacitor and the In0.7Ga0.3As MISFET are serial connected

externally. The transfer curve of LG = 2 μm, InGaAs MIS-FET and MFMIS-

FET at VDS = 0.5 V are shown in Fig.4.17. The filled points refer to the

measurement points of the forward direction and the opened points refer to

the measurement points of the reverse direction. First, it is observed that the

hysteresis loop of the MISFET was a clock-wise direction while the

hysteresis of MFMIS-FET exhibited almost no hysteresis and a twist

hysteresis loop at VG = -50 mV. Secondly, the calculated subthreshold-slope

was SSforward / SSreverse = 90 / 75 mV/dec and 83 / 73 mV/dec for MISFET

and MFMIS-FET, respectively. The improved subthreshold swings were

experimentally achieved in both direction. In addition, the on-current of

MFMIS-FET slightly increases compared to the MISFET result. These are

all definite reflection of negative capacitance effect using ferroelectric

characteristics. It suggests that our work successfully demonstrates the

characteristics of NC-FET.

173

The benchmarking of the reported III-V NCFETs are shown in Table

4.4. The research reported in VLSI 2018 [36] exhibited extremely low SS of

28 mV/dec by employing 8 nm of HZO ferroelectric layer and 1 nm of

Al2O3 interfacial layer in a MFIS structure. However, a huge counter-

clockwise hysteresis of 700 mV was observed which indicates a huge FE

and IL capacitance mismatch (the IL thickness may be too thin). If the

matching is well obtained, the SS value may be much bigger. Also, the

research reported in IEDM 2018 [35] exhibited low SS of 40 mV/dec with

very low hysteresis. The lower SS is attributed to the device operation

method (a tunneling mechanism) with negative capacitance effect. However,

the tunneling device usually lack the on-current performance therefore, the

on/off ratio is about 2E+4 at VD = 0.4 V. Also, the ferroelectric material used

in this research was PZT which fails CMOS compatibility. In conclusion,

our work has achieved both low subthreshold slope, low hysteresis and high

on/off ratio with a CMOS compatible process.

174

Figure 4.17 Comparison of transfer curves of InGaAs MISFET and

MFMIS-FET.

Table 4.4 Benchmarking of reported III-V NCFETs.

175

4.4. Conclusion

In this chapter, development of ferroelectric ALD HfO2 and integration

of advanced processes in InGaAs MOSFETs were addressed. A CMOS

compatible low temperature un-doped ALD HfO2 process was developed

and it successfully exhibited ferroelectric characteristics. In addition, in

order to adopt the FE-HfO2 technology on low thermal budget III-V

materials, several technologies such as annealing temperature optimization

and AlN lamination were studied to improve the thermal stability.

Systematic stress measurement study identified that the ferroelectric

characteristics of HfO2 are formed at the process stage of annealing and the

main mechanism is speculated to be the effect of stress relaxation toward the

tensile stress.

By integrating the developed processes, successful demonstration of

InGaAs MFMIS-FET was observed with the characteristics of NC-FET. The

subthreshold characteristic was improved with no hysteresis. It is expected

that with further investigation, our work might contribute to the most

advanced III-V MOSFETs for future technology node.

176

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181

Chapter 5. Conclusions and

Outlook

5.1. Conclusions

The main goal throughout this thesis was to develop a high quality gate

stack that can be exploited at different types of III-V MOS device

technologies. Even though, a substantial academic interest has been

developed for several decades in III-V compound semiconductors, the major

bottleneck for commercialization has always been the deficient gate stack

issue. Also, the III-V MOS gate stack studies in other research institutes

often failed to suggest the complete capability to achieve excellent gate

stack properties of a low interface trap and border trap, a great EOT

scalability and a stable reliability, all simultaneously. In this thesis, we

proposed a high quality PA-ALD HfOxNy dielectric which utilized a

sequential N2 plasma step in every ALD cycle and an IPA oxidant for the IL.

Improved gate stack characteristics were observed comparable to any other

result reported in the III-V MOS gate stack research. The gate stack

improvement mechanism was speculated to be the effect of the low surface

oxidation ability of IPA oxidant and the effective nitrogen passivation at the

oxygen vacancies in HfO2. The systematic studies of electrical and material

analysis supported our hypothesis. We believed that the proposed gate stack

has a competitive advantage over the other high-k dielectrics which will

result in excellent performance when adopted to the III-V MOS devices.

182

Then, the proposed III-V MOS gate stack was adopted to the III-V

MOSFETs to find out the actual feasibility of our work, and high quality

InGaAs MOSFETs were achieved that satisfy stringent DC and BTI

reliability targets for the VDD = 0.75 V technology node. The key technology

in this work was to compromise the trade-off relationships in terms of the

bulk and interface quality between the O3 and IPA-based HfOxNy by

utilizing a bi-layer ALD high-k gate stack scheme. Excellent subthreshold

characteristics and on-performance with superior PBTI reliability

characteristics showed comparable results compared to the previous III-V

MOSFET research. It suggests that the developed PA-ALD HfOxNy on our

work has actually demonstrated the great potential toward the III-V

technology. Furthermore, MOCVD-grown InGaAs MOSFETs were studied

as a cost effective solution to the industry and by optimizing both capping

layer and buffer layer quality, comparable transistor performance was

achieved. Also, three-dimensional fin-type InGaAs transistors were

demonstrated to overcome the short channel effect. High temperature dry

etching was adopted to define the III-V fin and the InGaAs quantum well

MOSFET has resulted in improved subthreshold characteristics compared to

the short channel planar-type. Also, a bottom-up aspect-ratio-trapping

(ART)-type InGaAs MOSFET was demonstrated for future CMOS

integration. These results prove that the developed gate stack scheme has

great potential on the advanced III-V MOSFETs.

Based on the achievements, the gate stack process was also adopted to

III-V NCFETs known to be the next generation transistors. Among several

ferroelectric dielectric candidates, CMOS compatible FE-HfO2 technology

was developed for this study. The FE-HfO2 technology was engineered to

adopt at low thermal budget III-V materials, and several technologies were

183

suggested for integration. As a result, by integrating the developed processes,

successful demonstration of III-V MFMIS-FETs was shown with the

characteristics of NC-FET.

5.2. Outlook

We believe that the developed bilayer PA-ALD HfOxNy gate stack has

great potential for the MOS interface related technologies. The obvious

application may be to employ the proposed gate stack to the other III-V

materials beside the studied n-type InGaAs. We already showed a successful

demonstration on p-type InGaAs substrate which might lead to a high

quality inversion mode MOSFET. As the most Si-based CMOS technology

operates in the inversion-mode, the inversion type III-V MOSFET has to be

studied. Also, while we only focused on NMOS technology, PMOS must

definitely has to be integrated for CMOS circuits. The Sb-based III-V

compounds such as GaSb are one of the strong PMOS candidates due to

their high hole mobility. The proposed gate stack can be studied on the Sb-

based substrates as well since they suffer from similar interface issues to the

InGaAs MOS research. Moreover, the PA-ALD HfOxNy can be employed

on the GaN HEMT studies. We already have reported several GaN MOS-

HEMT studies for a different type of applications including the

enhancement-mode high-power devices and the radio-frequency monolithic

microwave integrated circuits.

The successful gate stack results of III-V MOS devices in this thesis

were mainly demonstrated on the large-scale III-V MOS devices and only

the feasibility was shown for the scaled device structures. In order to

explore the actual prospect of the proposed gate stack to the required

184

technology node, it has to be tested at the more advanced device

architectures such as the extremely scaled FinFETs or Nano-Wire FETs with

the proper device fabrication processes. The source and drain capping layer

regrowth process that we studied could be the key technology for the

extremely scaled device architecture, since tight gate area define is available.

The regrowth process has to be further optimized by considering not only

decreasing the resistance but also reducing the gate-drain capacitance, which

has significant impact on the short channel effect. It can be achieved by

burying the capping layer and growing graded n-type doped InP spacers.

Also, although the ART FinFET might be the ultimate solution for III-V

channel on Si substrate, yet immature results were reported due to the large

buffer leakage. The ART III-V fin growth in this work was conducted on the

InP buffer, and the large buffer leakage is due to the very small conduction

band discontinuity between the InP and InGaAs layers. Selective InAlAs

buffer ART growth has to be researched and if it is not available, Nano-Wire

FET should be considered by selectively etching the buffer.

Furthermore, we demonstrated proto-type III-V MFMIS-FETs that

shown NC-FET characteristics. Although there are still some controversial

discussions about the credibility of the negative capacitance operating

model, various experimental results show promising results. We believe that

the proposed technologies in this thesis can provide some insight for the

ferroelectric and III-V integration and more studies should be continued.

Also, in the aspect of memory device applications, the MFIS FeFET suffers

from the large voltage drop issue at the interface layer. The HfOxNy IL

might be an effective solution that can achieve large memory window

without retention penalty.

185

Appendix

A. PEALD SiNx for Interface Layer

The results were reported at SSDM 2015.

Table A.1 PEALD SiNx configuration for III-V substrate.

SiH4 adsorption N2 Plasma

ICP power (W) 0 600 (300*)

Pressure (mtorr) 70 60

Gas Flow (sccm) SiH4 / N2 =25 /75 N2 / Ar = 50 /10

Dep. Rate (A/cycle) 0.53 (0.25*)

Figure A.1 (a) Schematic of PEALD SiNx deposition sequence (b)

Configuration of the ICP-CVD chamber (c) Final deposited PEALD SiNx

atomic structure.

186

Figure A.2 CV frequency dispersion characteristics of (a) 250 oC (b) 350 oC

(c) 400 oC deposition temperature SiNx IL InGaAs capacitors.

Figure A.3 TEM image of Pt/SiNx/InGaAs MOS interface.

187

Figure A.4 CV frequency dispersion characteristics of (a) SiNx only (b)

Al2O3/SiNx and (c) HfO2/SiNx InGaAs MOS capacitors.

188

Figure A.5 CV frequency dispersion characteristics of (a) No IL (b) 0.1 nm

SiNx IL (c) 0.2 nm SiNx IL and (d) 0.5 nm SiNx IL HfO2/InGaAs MOS

capacitors.

189

Figure A.6 (a) CV frequency dispersion characteristics of HfO2 (3 nm)/SiNx

(0.2 nm)/InGaAs MOS capacitor and (b) Dit distribution with and without

0.2 nm SiNx IL.

190

B. PEALD AlN for Interface Layer

The results were reported for KCS 2019.

Figure B.1 ALD window of PEALD AlN (a) N2/H2 ratio and (b) plasma

time.

191

Figure B.2 CV frequency dispersion characteristics of (a) low temp. (140 oC)

(b) medium temp. (230 oC) (c) high temp. (320 oC) and (d) low temp. (140

oC, 1 nm) + high temp. (320 oC, 6 nm) AlN/InGaAs MOS capacitors.

192

Figure B.3 CV frequency dispersion characteristics of (a) high temp. AlN 2

cycle and (b) low temp. AlN 2 cycle IL HfO2/InGaAs MOS capacitors and

(c) its Dit distributions.

193

Figure B.4 (a) XPS atomic concentration of AlN before and after etching (b)

CD-30 developer chemical resistance of AlN.

Issue of AlN surface oxidation still remains.

194

C. Pretreatment study for III-V substrate

Figure C.1 Effect of in-situ treatments at O3 based HfO2 at InGaAs

substrate.

The well-known treatments were experimented on the O3 based

HfO2/InGaAs interface, however, showed no significant treatment effect. It

might be the effect of an excessive oxidation issue of ozone.

195

Figure C.2 Dit comparison of the fabricated MOSCaps with various

treatments extracted by conductance method.

As expected, the treatments were ineffective and only the HfON MOS

results showed the improvements even without the treatments. It was

concluded that the in-situ treatments are only effective when the high-k

deposition process is optimized. Also, the improvement mechanism of

HfON would be an indirect mechanism not a nitrogen passivation effect as

the nitrogen plasma treatment showed only limited effect. It was concluded

that in order to optimize the pretreatment process, the surface oxidation

issue of O3 oxidant should be first solved

196

Figure C.3 Effect of in-situ treatments at IPA based HfO2 at InGaAs

substrate.

Unlike the O3 based HfO2/InGaAs MOS results, the TMA treatment

showed meaningful effect on IPA based HfO2/InGaAs interface. The TMA

treatment showed increase of maximum capacitance and decrease of

inversion hump. It is believed that the pretreatment effect is starting to be

observed by replacing to a less reactive oxidant.

197

Figure C.4 Dit comparison of the fabricated MOSCaps with various

treatments.

The Dit values of IPA based hafnium oxides were much lower than

those of the O3 based hafnium oxides. Also, with optimized in-situ

treatments the interface trap values were decreased effectively. The Dit

values of IPA-based HfON were much lower first to observe below the

order of twelve and with proper ex-situ treatments and annealing process,

very low interface trap densities were finally achieved.

198

Abstract in Korean

오늘날 눈부신 발전을 이룬 모스펫 (MOSFET) 소자는 게이트

길이가 줄어 감에 따라 소자의 전력 소모를 줄이는 것이 가장 큰

관건으로 여겨지고 있다. 기존의 실리콘 (Si) 기반 모스펫

기술로는 이러한 급격한 전력 제한적 스케일링 요구사항을

달성하기가 굉장히 어려울 것으로 예상되고 있으며 이에 따라 7

nm 미만의 로직 트랜지스터 로드맵에서는 전자 이동성이 매우

높은 채널 재료인 III-V족 화합물 반도체를 차세대 반도체 기술로

제안하고 있다. 하지만 III-V족 화합물 반도체의 산화막 품질 결함

문제는 실제 반도체 산업에서의 실용적인 응용을 어렵게 하였고

이를 해결하기 위한 연구가 오랜 기간 수행되었지만 여전히

실리콘 산화막 연구와는 그 차이가 크게 존재하고 있다.

본 연구의 목표는 원자층증착 (ALD) 기술을 이용해 개선된

고유전율 (high-k) 박막 공정을 개발하여 III-V족 화합물

반도체에서도 우수한 계면 특성을 확보하는 것이다. 인듐갈륨비소

(InGaAs) 기판에 실리콘나이트라이드 (SiNx) 및 알루미늄-

나이트라이드와 (AlN) 같은 여러 high-k 박막을 적용시키는 연구를

하였고 개선된 계면 품질 결과를 보였으나 유전상수가 충분치

않아 더 이상 등가산화물 두께를 (EOT) 줄이는 것은 어려움이

있었다. 낮은 EOT와 동시에 우수한 인터페이스 특성을 달성하기

199

위해서는 고유전율을 가지는 하프늄옥사이드 (HfO2) 박막과

InGaAs 사이의 본질적인 계면 품질 향상이 불가피한것으로 보였다.

우리는 N형 InGaAs에서 이소프로필알코올 (IPA) 산화제 및 주기

질소 (N2) 플라즈마 처리된 고품질 플라즈마 보조 원자층증착 (PA-

ALD) 하프늄옥시나이트라이드 (HfOxNy) 박막종정을 제안하였고

이는 본 연구의 주요 성과였다. 이 박막 공정을 통해 일반적으로

결함이 많은 HfO2/InGaAs 계면에서는 관측할 수 없는 강력한 반전

(inversion) 특성을 관찰하였으며 매우 개선된 계면 준위 밀도가

(Dit) 달성되었다. 또한, 개발된 게이트 스택 결과의 계면 특성

개선 메커니즘 및 상세한 특성화 연구가 수행되었다. 본 연구의

뛰어난 성과는 보고된 다른 high-k/III-V MOS 결과를 능가하고

있으며 앞으로의 III-V족 화합물 반도체 연구에 크게 기여할

것으로 기대된다.

III-V MOSFET에서 앞선 MOS 연구 결과가 미치는 영향을

알아보기 위해 InGaAs MOSFET 제작 공정 프로세스를 개발 및

최적화하였다. 앞선 연구결과에서 관찰된 오존과 IPA 기반 HfOxNy

사이의 벌크 및 계면 품질 측면에서 서로 상쇄되는 관계는 게이트

스택의 관점에서 최적화하는 연구를 하였다. 본 논문에서는 IPA

기반 HfOxNy 계면층과 O3 기반 HfOxNy 벌크층으로 구성된 이중층

ALD high-k 게이트 스택 방식을 제안하였다. 최적화된 이중층

게이트 스택을 사용하여 제작된 InGaAs MOSFET에서 탁월한 문턱

200

전압이하 특성과 on-off 성능을 달성했다. 또한, III-V MOSFET

연구에서 보고된 최상의 결과와 뒤지지 않는 우수한 PBTI 신뢰성

특성이 달성되었다. 더 나아가 반도체 산업에 실제 응용되기 위해

비용 효율적인 솔루션으로서 MOCVD로 성장된 InGaAs MOSFETs

를 제작 하였으며 소스 드레인 층과 버퍼 층 품질의 개선을 통해

우수한 트랜지스터 성능을 달성했다. 그리고 현재의 반도체 기술

경향을 따르는 3차원 Fin 모양의 InGaAs를 제작하였다. 고온 건조

식각의 개발로 60 nm의 게이트 길이를 가지는 InGaAs quantum well

fin-type MOSFET을 개발하였으며 이는 같은 게이트 길이의 planar-

type소자보다 우수한 문턱 전압이하 특성을 보였다. 또한 bottom-up

aspect-ratio-trapping (ART)-type InGaAs MOSFET의 개발을 통해 실제

CMOS기술과의 융합 가능성을 제시하였다.

또한, 개발된 InGaAs MOSFET 기술에 강유전체 HfO2 기술을

접목하여 차세대 negative-capacitance FET(NC-FET) 응용의 실현

가능성을 보는 연구를 하였다. NC-FET는 매우 가파른 subthreshold

swing 특성을 달성할 수 있는 차세대 기술로 잘 알려져 있다.

CMOS기술과 호환이 가능한 저온 ALD HfO2 공정을 개발하여

강전 특성이 성공적으로 발휘하는 것을 관찰였다. 또한 III-V 족

반도체의 열적 불안정성을 극복하기 위해 FE-HfO2 기술의 열

안정성 확보 기술을 연구하였고, 강전 형성 메커니즘을 분석하기

위해 체계적인 연구를 추가로 수행하였다. 최종적으로 개발된

201

공정을 통합함으로써 NC-FET의 특성을 보이는 InGaAs MFMIS-

FET의 성공적인 연구 결과를 확보하였으며 본 연구에서 개발한

기술들의 차세대 소자 응용 가능성을 성공적으로 확보하였다.

202

Research Achievements

Journals

[1] S.-K. Eom, M.-W. Kong, M.-J. Kang, J.-G. Lee, H.-Y. Cha, and K.-

S. Seo, “Enhanced Interface Characteristics of PA-ALD

HfOxNy/InGaAs MOSCAPs Using IPA Oxygen Reactant and Cyclic

N2 Plasma,” IEEE Electron Device Letters, vol. 39, no. 11, pp. 1636,

2018.

[2] S.-K. Eom, M.-W. Kong, H.-Y. Cha, and K.-S. Seo, "

Characterization of High-Performance InGaAs QW-MOSFETs with

Reliable Bi-layer HfOxNy Gate Stack," Journal of the Electron

Devices Society, 2019 (Under Review)

[3] M.-J. Kang, S.-K. Eom, H.-S. Kim, C.-H. Lee, H.-Y. Cha, and K.-S.

Seo, “Normally-off recessed-gate AlGaN/GaN MOS-HFETs with

plasma enhanced atomic layer deposited AlOxNy gate insulator,”

Semiconductor Science and Technology, vol. 34, no. 5, pp. 055018,

Mar. 2019.

[4] H.-S. Kim, S.-K. Eom, K.-S. Seo, H. Kim, and H.-Y. Cha, “Time-

dependent dielectric breakdown of recessed AlGaN/GaN-on-Si

MOS-HFETs with PECVD SiO2 gate oxide,” Vacuum, vol. 155, pp.

428, Sep. 2018.

[5] I.-H. Hwang, S.-K. Eom, G.-H. Choi, M.-J. Kang, J.-G. Lee, H.-Y.

Cha, and K.-S. Seo, “High-Performance E-Mode AlGaN/GaN MIS-

HEMT with Dual Gate Insulator Employing SiON and HfON,”

physica status solidi (a), vol. 215, no. 10, pp. 1700650, 2018.

[6] D.-H. Kim, S.-K. Eom, J.-S. Jeong, J.-G. Lee, K.-S. Seo, and H.-Y.

Cha, “Thermal stability and small-signal characteristics of

AlGaN/GaN HEMTs with gate insertion metal layer for millimeter-

wave applications,” Journal of Vacuum Science & Technology B, vol.

35, no. 6, pp. 060601, 2017.

[7] S.-H. Roh, S.-K. Eom, G.-H. Choi, M.-J. Kang, D.-H. Kim, I.-H.

Hwang, K.-S. Seo, J.-G. Lee, Y.-C. Byun, and H.-Y. Cha,

“Normally-off AlGaN/GaN-on-Si metal-insulator-semiconductor

203

heterojunction field-effect transistor with nitrogen-incorporated

silicon oxide gate insulator,” Journal of the Korean Physical Society,

vol. 71, no. 4, pp. 185, Aug. 2017.

[8] D.-H. Kim, S.-K. Eom, M.-J. Kang, J.-S. Jeong, K.-S. Seo, and H.-Y.

Cha, “V-band monolithic microwave integrated circuit with

continuous wave output power of >23.5 dBm using conventional

AlGaN/GaN-on-Si structure,” Journal of Vacuum Science &

Technology B, vol. 34, no. 4, pp. 040602, 2016.

[9] D. Kim, H. Park, S. Eom, J. Jeong, H. Cha, and K. Seo, “Ka-Band

MMIC Using AlGaN/GaN-on-Si With Recessed High-k Dual MIS

Structure,” IEEE Electron Device Letters, vol. 39, no. 7, pp. 995,

2018.

[10] H.-S. Kim, W.-H. Jang, S.-K. Eom, S.-W. Han, H. Kim, K.-S. Seo,

C.-H. Cho, and H.-Y. Cha, “Effects of PECVD SiO2 Gate Dielectric

Thickness on Recessed AlGaN/GaN MOS-HFETs,” Journal of

Semiconductor Technology and Science, vol. 18, no. 2, pp. 187, 2018.

[11] J.-G. Lee, D.-H. Kim, S.-K. Eom, S.-H. Roh, K.-S. Seo, H.-S. Kim,

H. Kim, H.-Y. Cha, and Y.-C. Byun, “Improved interface

characteristics of Mo/SiO2/4H-SiC metal-oxide-semiconductor with

post-metallization annealing,” Journal of the Korean Physical

Society, vol. 72, no. 1, pp. 166, Jan. 2018.

[12] D.-H. Kim, J.-S. Jeong, S.-K. Eom, J.-G. Lee, K.-S. Seo, and H.-Y.

Cha, “Electrical degradation on DC and RF characteristics of short

channel AlGaN/GaN-on-Si hemt with highly doped carbon buffer,”

Journal of the Korean Physical Society, vol. 71, no. 10, pp. 711, Nov.

2017.

[13] M. Lee, D. Kim, S. Eom, H. Cha, and K. Seo, “A Compact 30-W

AlGaN/GaN HEMTs on Silicon Substrate With Output Power

Density of 8.1 W/mm at 8 GHz,” IEEE Electron Device Letters, vol.

35, no. 10, pp. 995-997, 2014.

International Conferences

[1] S.-K. Eom, S.-H. Roh, M.-J. Kang, D.-H. Kim, J.-G. Lee, H.-Y. Cha,

and K.-S. Seo, “Improvement of Interface Characteristics in

204

HfO2/InGaAs MOS Devices by Employing In-situ Nitrogen Plasma

Treatment within ALD Cycles,” Asia-Pacific Workshop on

Fundamentals and Applications of Advanced Semiconductor Devices

(AWAD), 2017. (Oral)

[2] S.-K. Eom, R.-S. Ki, D.-H. Kim, H.-Y. Cha, and K.-S. Seo,

“Improved interface of HfO2/InGaAs MOS by employing thin SiNx

interfacial layer using plasma enhanced atomic layer deposition,”

Solid State Devices and Materials (SSDM), 2015. (Poster)

[3] S.-K. Eom, M.-J. Kang, H.-Y. Cha, and K.-S. Seo, “1.3 nm Effective

Oxide Thickness Self-aligned InGaAs MOS-HEMT using

SiNx/HfO2 Bi-layer as Gate Insulator,” Asia-Pacific Workshop on

Fundamentals and Applications of Advanced Semiconductor Devices

(AWAD), 2015. (Poster)

[4] S.-W. Han, S.-K. Eom, H.-S. Kim, K.-S. Seo and H.-Y. Cha,

“Negative Capacitance AlGaN/GaN Heterojunction Field-Effect

Transistors Using Ferroelectric Phase ALD-HfO2 with 22 mV/dec

Subthreshold Slope,” International Workshop on Nitride

Semiconductor (IWN), 2018.

[5] I.-H. Hwang, S.-K. Eom, H.-Y. Cha, and K.-S. Seo, “High

performance Normally-off Tri-gate AlGaN/GaN MIS-HEMT with

Partially Recessed MIS Structure,” International Workshop on

Nitride Semiconductor (IWN), 2018.

[6] H.-S. Kim, S.-K. Eom, S.-W. Han, W.-H. Jang, K.-S. Seo, and H.-Y.

Cha, “Electrical Properties of Normally-off AlGaN/GaN-on-Si

Recessed MIS-FETs Using PECVD SiON as Gate Dielectric,”

International Workshop on Nitride Semiconductor (IWN), 2018.

[7] M.-W. Kong, S.-K. Eom, C.-H. Lee, H.-Y. Cha, and K.-S. Seo,

“Fabrication of In0.53Ga0.47As homo-junction TFET with optimized

gate stack by emplying surface treatment and post metallization

annealing,” Solid State Devices and Materials (SSDM), 2018.

[8] S.-W. Han, S.-K. Eom, K.-S. Seo, and H.-Y. Cha, “GaN based

Negative Capacitance Heterojunction Field-Effect Transistors for

Steep Switching Operation,” Asia-Pacific Workshop on

Fundamentals and Applications of Advanced Semiconductor Devices

(AWAD), 2018.

205

[9] M.-J. Kang, S.-K. Eom, C. Lee, I.-H. Hwang, J.-G. Lee, H.-Y. Cha,

and K.-S. Seo, “High quality nitrogen-incorporated aluminium oxide

(Al2O3) for normally-off AlGaN/GaN-on-Si metal-insulator-

semiconductor HEMTs (MIS-HFETs),” Asia-Pacific Workshop on

Fundamentals and Applications of Advanced Semiconductor Devices

(AWAD), 2017.

[10] D.-H. Kim, S.-K. Eom, H.-Y. Cha, and K.-S. Seo, “Effects of Gate

Recess Depth on 0.15 um AlGaN/GaN Normally-on MIS-HEMT on

Si Substrate,” Asia-Pacific Workshop on Fundamentals and

Applications of Advanced Semiconductor Devices (AWAD), 2015.

[11] D. Kim, S. Eom, S. Han, H.-Y. Cha, and K. S. Seo, “Suppress

Current Collapse Effect by Optimizing 0.12um Gate Structure of

AlGaN/GaN HEMTs on Si-substrate for Microwave Power

Applications,” Solid State Devices and Materials (SSDM), 2013.

[12] M.-J. Kang, C.-H. Lee, S.-K. Eom, H.-S. Kim, H.-Y. Cha, and K.-S.

Seo, “Normally-off Recessed-gate AlGaN/GaN MOS-HFETs with

Plasma Enhanced Atomic Layer Deposited AlOxNy Gate Insulator,”

International Workshop on Nitride Semiconductor (IWN), 2018.

[13] M.-J. Kang, C.-H. Lee, S.-K. Eom, H.-S. Kim, H.-Y. Cha, and K.-S.

Seo, “Improved Vth Stability of Recessed-Gate AlGaN/GaN-on-Si

MOS-HFETs Using Cyclic Nitrogen Incoporation into Al2O3 Gate

Insulator,” International Workshop on Nitride Semiconductor (IWN),

2018.

[14] I.-H. Hwang, G.-H. Choi, S.-K. Eom, M.-J. Kang, H.-Y. Cha, and

K.-S. Seo, “Gate Recessed E-mode AlGaN/GaN MIS-HEMT with

Dual Gate Insulator Employing PEALD SiON and HfON,”

International Conference on Nitride Semiconductors (ICNS), 2017.

[15] H.-S. Kim, W.-H. Jang, S.-K. Eom, S.-W. Han, H. Kim, K.-S. Seo,

C.-H. Cho, and H.-Y. Cha, “Effects of PECVD SiO2 Gate Dielectric

Thickness on Recessed AlGaN/GaN MOS-HFETs,” Asia-Pacific

Workshop on Fundamentals and Applications of Advanced

Semiconductor Devices (AWAD), 2017.

[16] D.-H. Kim, M.-J. Kang, S.-K. Eom, H.-Y. Cha, and K.-S. Seo, “Low

Current Collapsed AlGaN/GaN HEMT-on-Si Substrate with

SiNx/HfO2 Dual Passivation Layer,” Solid State Devices and

206

Materials (SSDM), 2015.

[17] D.-H. Kim, J.-H. Kim, S.-K. Eom, M.-S. Lee, and K.-S. Seo, "77

GHz Power Amplifier MMIC using 0.1 μm Double-Deck Shaped

(DDS) field-plate gate AlGaN/GaN HEMTs on Si Substrate,"

International Conference on Compound Semiconductor

Manufacturing Technology (CS MANTECH), 2014.

[18] M.-S. Kim, D.-H. Kim, S.-K. Eom, and K.-S. Seo, “Improvement of

interface quality in SiNx/InGaAs MISFET using two-step deposition

method,” European workshop on heterostructure technology

(HETECH), 2014.

-Domestic Conferences

[1] S.-K. Eom, M.-W. Kong, H.-Y. Cha, and K.-S. Seo, “Effect of

deposition temperature on plasma-enhanced atomic layer deposited

AlN/InGaAs MOS characteristics,” 한국반도체학술대회 (KCS),

2019. (Poster)

[2] S.-K. Eom, N.-H. Lee, and K.-S. Seo, “Suppression of current

collapse effect by insertion of Mo on Ni/Au based schottky contacts

in AlGaN/GaN HEMT,” 한국반도체학술대회 (KCS), 2014.

(Poster)

[3] M.-W. Kong, S.-K. Eom, G.-W. Park, C.-S. Shin, K.-S. Seo,

“Fabrication of MOCVD-grown InGaAs Tunnel Field Effect

Transistor,” 한국반도체학술대회 (KCS), 2019.

[4] D.-H. Kim, S.-K. Eom, H.-Y. Cha, and K.-S. Seo, “Improvement of

Thermal Reliability for GaN Microwave Device Using

Molybdenum Insertion Gate Metal,” 한국반도체학술대회 (KCS),

2017.

[5] S.-H. Roh, S.-K. Eom, and K.-S.Seo, “Comparison of post-

metallization annealing and post-deposition annealing and

investigation of PMA effect with different gate metal stacks,”

한국반도체학술대회 (KCS), 2017.

207

[6] M.-J. Kang, C.-H. Lee, S.-K. Eom, J.-G. Lee, H.-Y. Cha, and K.-S.

Seo, “Improvement of Bias-Induced Vth Stability in Recessed-Gate

AlGaNGaN MIS-HEMTs with Nitrogen-Incorporated Al2O3 gate

insulator,” 한국반도체학술대회 (KCS), 2018.

[7] M.-W. Kong, R.-S. Ki, S.-K. Eom, M.-J. Kang, H.-Y. Cha, and K.-S.

Seo, “Leakage current reduction of Gallium Nitride diode for high

frequency operation,” 한국 LED 광전자학회 창립학술대회,

2018.

[8] M.-J. Kang, G.-H. Choi, S.-K. Eom, H.-Y. Cha, and K.-S. Seo,

“Improvement in Transconductance and Hysteresis of E-mode

AlGaN GaN MIS-HEMTs with Cat-CVD SiNx as Gate Insulator,”

한국반도체학술대회 (KCS), 2016.

[9] M.-S. Lee, D.-H. Kim, S.-K. Eom, and K.-S. Seo, “Improved

current collapse phenomenon in AlGaN/GaN HEMTs on Si

substrate by using SiNx re-deposition process,” 한국반도체

학술대회 (KCS), 2014.

-Domestic Patents

[1] K.-S. Seo and S.-K. Eom, “Method for forming hafnium oxynitride

film and semiconductor device using the same,” (Application) 10-

2018-0057225, 2018

[2] H.-Y. Cha, S.-W. Han, H.-S. Kim, S.-K. Eom, “Heterostructure

Field Effect Transistor and production method thereof,”

(Application) 10-2018-0034610, 2018