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2002 Fairchild Semiconductor Corporation Application Note 7507 Rev. A1
SP600 and SP601 an HVIC MOSFET/IGT Driverfor Half-Bridge Topologies
The interfacing of low-level logic to power half-bridge config-
urations can be accomplished by an 500VDCintelligent IC,
the SP600 series driver, which is designed for up to 230VAC
line rectified operation. The primary function of the high volt-age integrated circuit (HVIC) is to drive n-channel MOS
gated power devices in totem pole configuration. Compatible
with current-sensing MOSFETs/IGTs, this HVIC provides
overcurrent shutdown, simultaneous conduction protection,
and undervoltage lockout. Logic level inputs provide noise
immune control of power element switching.
The SP600 has demonstrated high frequency (130kHz)
operation as well as the ability to withstand high dv/dt. Its
semicustom design flexibility makes it easily adaptable to a
wide range of single and multiple phase applications. Other
salient features of the device are described below.
Technology Overview
BiMOS structures are implemented in a junction-isolation
process, known as lateral charge control,1 that supports
high voltage laterally. By the use of this thin epi process, low
voltage analog and digital circuitry can be combined mono-
lithically with high voltage transistors. Low voltage circuits
can be constructed to float up to 500VDCwith respect to the
substrate. Additionally, 500VDCNMOS and n-p-n transistors
can also be fabricated.2 Since this process conforms to
mainstream low voltage IC manufacturing, it is cost effective.
Totem Pole Drivers
Historically, designers have been faced with awkward deci-
sions regarding the upper-rail drive of bridge topologies.
P-channel MOSFETs, while easy to drive, are more than
twice as expensive as equivalent n-channel devices having
the same rds(on). Economic barriers and product availability
generally prohibit design beyond 200VDC. On the other
hand, the driving of upper rail n-channel MOS gated devices
requires a floating gate supply that must be 5 to 20VDCgreater than the upper rail link. While several discrete
approaches for implementing this floating supply are known,
the designer is burdened with additional components and
potential dv/dt problems associated with voltage translation.
The SP600 series driver provides the economical solution as
an intelligent totem pole n-channel driver. With the addition
of as few as five, user defined, external, passive components
(three if current detection isnt employed) a functional half-bridge driver can be built that has the following features:
Creation and management of a 15VDCupper-rail power
supply
Ability to interface and drive standard and current sensing
n-channel MOSFETs/IGTs
Shoot-through protection
Overcurrent protection
Undervoltage lockout
CMOS logic-level input compatibility
Semicustom flexibility through metal-mask changes
Standard 22-pin DIP packaging
Theory of Operation
Figure 1 is the basic block diagram of the SP600. CMOS
logic compatible input signals are filtered to ensure reliable
operation when the device is subjected to noisy industrial
environments. Digital commands at TOP and BOTTOM
inputs cause the upper or lower drivers, respectively, to turn
on or off. The ITRIP SELECT input provides a higher than
nominal current limit on a pulse-by-pulse basis. The input
signals are decoded to drive the appropriate output device.High voltage translation is provided by current mirror pulses
used to communicate upward to the top gate driver to initiate
turn on or off (ION/IOFF pulses). These momentary pulses
are captured by local latches to maintain the desired state.
This feature minimizes power dissipation in the level shifter
and provides added noise immunity as well. The bottom gate
driver circuitry is similar. The floating bootstrap power supply
is provided by low voltage capacitor CF and high voltage
diode DF. Each time the VOUTnode goes low, CFcharges to
roughly a diode drop less than VDD(15VDC). This situation
prevails each time the lower output device is activated or, in
the case of an inductive load, whenever the upper device is
switched off and freewheeling load current forces the output
node to a diode drop below ground. In either case, DFis for-ward biased, allowing CFto charge through the current limit-
ing resistor RBS to approximately VDD. Noise dropping
resistor RND, along with capacitor CDD, provides localized
filtering of the bias supply and bypasses bias supply series
inductance facilitating fast and complete bootstrap refresh.
Each output device is protected on a pulse-by-pulse basis
from overcurrent (OC) by sense resistor RS, which is con-
nected to 100mV comparators. This arrangement permits
the designer to take advantage of nearly lossless current-
sensing MOSFETs or IGTs.
Upon detection of any OC, the output is immediately dis-
abled. In the case of the lower switch, a FAULT is directly
detected and reported. Upper rail OC FAULTs are indirectly
reported via the output voltage monitor when it detects an
output state not in agreement with the commanded TOP
input signal. With local OC detection and shutdown of the
upper device, an inductive load will force VOUT low due to
freewheeling. This out of status detector recognizes a fault
when VOUTis typically less than 5.5VDC.
Application Note Apri l 1997 AN-7507
Author: Dean F. Henderson
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2002 Fairchild Semiconductor Corporation Application Note 7507 Rev. A1
FIGURE 1. BLOCK DIAGRAM OF THE HVIC
FIGURE 2. FUNCTIONAL DIAGRAM OF THE HVIC
Logic and Timing
Figure 2 is a detailed functional circuit of the SP600. The fil-
tered inputs, TOP, BOTTOM, and ITRIP SELECT, ignore pulse
widths less than typically 400ns to prevent false triggering.
During the generation of ION and IOFF pulses, the control
logic ignores further changes in the input signal. For each
IONpulse, an IOFFpulse is simultaneously sent to the oppo-
site driver, thus eliminating the possibility of spurious shoot
through caused by high voltage, high-speed switching.
These features aid in providing predictable operation of the
floating upper rail driver section, which is capable of slewing
over 10,000 volts per s.
+15VBIAS
VDD
CDD
TOP
BOTTOM
I TRIP SELECT
FAULTHVIC
FILTER
RND RBS
ION IOFF
F
CF
RS
+VDC
VOUT
RS
FILTER
CMOS TIMINGCONTROL LOGIC& PHASE STATUS
BOTTOMGATE
DRIVER
TOPGATE
DRIVER
OUTPUT VOLTAGEDETECTOR
CMOSTIMING
ANDCONTROL
VOUTSENSE &FILTER UV
LOCK-OUT
FILTER
QR
S
VBIAS
VDD
VDF
RND
RBS
TOP
BOTTOM
FAULT
ITRIPSEL
1
2
3
4
11
22
21
10
3.5
750
RF
ITRIPSEL
FAULT
ITRIPSEL
ION B
IOFF B
UVLOCK-OUT
LEVELSHIFT
QR
S
QR
S
QR
S
QR
S
+
-
+
-
12
19
18
17
15
16
14
13
10
9
8
6
7
5
VBS
D1U
G1U
G2U
UPPER
TRIPU
CL2
PHASE
VOUT
D1L
G1L
G2L
LOWER
TRIPL
CL1
VSS
RO
3.5
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2002 Fairchild Semiconductor Corporation Application Note 7507 Rev. A1
PHASE serves as a common reference for the floating boot-
strap supply (VBS) and all upper rail logic. VOUT, for all prac-
tical purposes, is at the same potential as PHASE, being
separated from it electrically by only a few (RO). This addi-
tional series output resistance helps to limit the peak current
being drawn from the HVIC when an external lower flyback
diode, undergoing forward recovery, forces VOUTnegative.
An automatic refresh algorithm is generated by the CMOS
timing and control block to ensure that the bootstrap capaci-
tor remains charged. As mentioned above, CF is refreshed
each time the VOUTnode swings to common. At power up,
with zero voltage on CF, there are two ways to refresh the
bootstrap capacitor. The first is by initially commanding the
bottom device to turn on, forcing VOUT low. The second
occurs when an automatic refresh is invoked if the TOP has
been commanded on for longer than 200s to 500s. The
logic momentarily ignores the inputs, and turns on the lower
output (subsequent to an IOFF TOP) for typically 2.0s,
charges CF and finally restores control to the input com-
mands. Automatic refresh is overridden at switching rates
greater than 5kHz, the minimum refresh timer period.
A dual level current limit provision allows for a 30% highercurrent trip point (above nominal) on a pulse-by-pulse basis.
A logic level 1 applied to ITRIP SELECTprovides a boosted
current limit suited for applications like uninterruptable power
supplies (UPS), which may have occasional shifted peak
power requirements. This feature may allow for a more opti-
mally selected output device. Benefits of current boost have
been demonstrated in an off-line PWM motor controller
where ITRIP SELECTis momentarily applied to overcome the
inertia associated with rotor start-up.3
Both outputs are disabled and a FAULT reported as a result of:
Overcurrent
VDD(lower bias) and VBS(upper bias) undervoltage
VOUT/PHASE out-of-status
Simultaneously commanded TOP and BOTTOM input
(outputs disabled, no FAULT reported)
The fault can be cleared by a logic 0 at both TOP and
BOTTOM inputs for the required fault reset delay time of
3.4s to 6.6s.
Power Driver Section
The upper and lower driver output sections are nearly identi-
cal, Figure 3.4Separate sink and source transistors are sep-
arately bonded out for application specific designs requiring
additional series gate impedance(s) for slower charge anddischarge rates. This circuit property becomes particularly
important with IGTs, where a minimum turn-off impedance of
100may be required to ensure full SOA. Regardless of the
switching element used, companion flyback diode character-
istics may necessitate slower turn-on to reduce peak reverse
recovery current by increasing the gate impedance by
means of RCHARGE.
A nominal 100mVDCcomparator provides overcurrent (OC)
protection when used with either current sensing IGTs or
MOSFETS. OC can also be implemented by using low
impedance shunts with noncurrent sensing power output
devices, Figure 4.
Clamp CL1 in Figure 4 provides overvoltage protection for cur-rent sensing structures during switching intervals, and pro-
tects the comparator from any voltage transients due to
external lead inductances. To avoid nuisance OC trips caused
by reverse recovery current during turn-on transitions, the
comparators output is blanked for approximately 3s.
System Performance
The half-bridge test circuit in Figure 5 was built to demon-
strate the SP600 as a high frequency driver of MOSFETs.
The load is referenced to one-half the battery voltage, allow-
ing bidirectional load current. This circuit characteristic emu-
lates power configurations of half bridges with split supply or
full bridges implemented with multiple HVICs.
For ultimate switching speed, no additional series gate
impedances were used. Peak MOSFET gate charge and dis-
charge current waveforms of 400 and 510mADC, respec-
tively, were observed, Figure 6.
FIGURE 3. POWER-OUTPUT SECTION INTERFACING WITH CURRENT SENSING MOSFET OF IGT
UVLOCK-OUT
VDD
FAULT
ITRIPSEL
QR
S
QR
SION B
IOFF B
10
9
8
6
7
5VSS
D1L
G1L
G2L
TRIPL
CL1
+
-
RCHARGE
RDISCHARGE
RSENSE
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2002 Fairchild Semiconductor Corporation Application Note 7507 Rev. A1
FIGURE 4. POWER OUTPUT SECTION INTERFACING WITH NONCURRENT SENSING MOSFET OR IGT.
FIGURE 5. HALF-BRIDGE TEST CIRCUIT
High frequency, high voltage operation requires that upper
rail drive and level translator circuitry be immune to high
dv/dt, as this section floats with respect to VOUT/PHASE.Interjunction capacitance can dynamically inject displace-
ment currents, raising havoc in circuit performance or even
causing catastrophic failures, including the breakdown of
voltage isolation tubs or latch-up in adjacent four layer
structures.
At rail voltages of 200VDC to 400VDC, rise and fall transi-
tions of VOUT/PHASE were measured in the 20ns to 35ns
region. The HVIC operated flawlessly while being subjected
to output swings beyond 11,000V per s. Figure 7 demon-
strates the HVICs ability to sustain such dv/dt when driving
IRF820 devices.
IRF 842s were driven at 130kHz in this same half-bridge cir-
cuit, Figure 8. The ultimate switching speed of the SP600
series HVIC will depend on gate capacitance and the duty
cycle limits dictated by the minimum IONand IOFFtimes. A
minimum IONtime (1.6s to 3.1s) ensures time for refresh,
while a minimum IOFFtime (1.3s to 3.4s) prevents simul-
taneous conduction by allowing for gate discharge prior to an
opposite ION pulse. The same promising technology has
been shown to operate a half-bridge resonant converter at
frequencies up to 600kHz.6
UVLOCK-OUT
VDD
FAULT
ITRIPSEL
QR
S
QR
SION B
IOFF B
10
9
8
6
7
5VSS
D1L
G1L
G2L
TRIPL
CL1
+
-
RCHARGE
RDISCHARGE
RSHUNT
ILOAD
LOAD
VBSVDF
DF
VBIAS
VDD
FAULT
TOP BOT
TRIPL
COM
G2L
G1L
D1L
TRIPU
VOUT
PHASE
G2U
G1U
D1U
SP600HVIC
3.3
15V
33
K
0.22
CF
2200
2200
30-500VDC
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2002 Fairchild Semiconductor Corporation Application Note 7507 Rev. A1
FIGURE 6. GATE-CURRENT WAVEFORMS DRIVING AN IRF820
FIGURE 7. VOUTTRANSITION AT TURN ON OF LOWER IRF820
FIGURE 8. OUTPUT LOAD CURRENT AT 130kHz USING
IRF842s
Semicustom Capability
The SP600 family can be customized by inexpensive, final
metal mask alterations. Application specific designs are pos-
sible for variations in the following parameters:
Minimum ION/IOFFpulses
OC trip response time
Input signal conditioning filters
OC trip level
Inclusion of RCHARGE/DISCHARGE
ITRIP SELECTboost level
FAULT reset timer
Other system related options include:
Input protocol
Automatic FAULT reset
Ability to disable the automatic refresh algorithm
References
1. E. J. Wildi, et al, New High Voltage IC Technology, IEDM
84 Conference proc, pp 262-265.
2. E. J. Wildi, et al, 500V BiMOS Technology and its Appli-
cations, Electro 85 paper #24/2.
3. J. G. Mansmann, et al, ASIC Like HVIC for Interfacing to
Half-Bridge Based Power Circuits, PESC March 88.
4. J. G. Mansmann, et al A Flexible High Voltage Controller
Core for Half He N-Channel Bridge Operation, MOTOR-
CON proc, Sept 87, pp 194-205.
5. D. J. MacIntyre, Motor Control Applications of Second
Generation IGT Power Transistors, GE PESD Application
Note 200.95.
6. R. L. Steigerwald, et al, A High-Voltage Integrated Circuit
for Power Supply Applications, APEC proc, Mar 87, pp
221-229.
Appendix
Timing Waveforms
Although both SP600 and SP601 timing diagrams are shown
the SP601 was chosen to provide further explanation.
Top: Turn Off Vertical: 100mA/div
Bottom: Turn On Horizontal: 20ns/div
Vertical: 50V/div
Horizontal: 50ns/div
Vertical: 50V/div
Horizontal: 50ns/div
0
0
0
0
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2002 Fairchild Semiconductor Corporation Application Note 7507 Rev. A1
SP600 Series Timing Diagram
t0< t < t1 At t0, with the enable high, the outputs are simultaneouslycommanded to switch from lower to upper which is also
known as Bistate operation. After delay tOFFD, the lower is
turned off, followed by the uppers turned on. Dead time, tD.T.,
the difference between the lower off transition to the upper
on transition is internally set. Since this timing sets the mar-
gin of safety for simultaneous conduction, its the users re-
sponsibility to ensure that proper external gate impedance is
selected to ensure ample time for power transistor charg-
ing/discharging.t1< t < t2 The lower is turned on at t1and continues for a relatively long
period, long enough that at t2an automatic refresh will be in-
voked.
t2< t < t3 The HVIC has blinded itself to the logic inputs during this re-fresh mode. The upper is turned off, with its associated turn
off delay, tOFFD. After the fixed dead time, tD.T., the lower is
briefly turned on, ton, providing a charge refresh path for the
bootstrap capacitor, CF. Once again the dead time is ob-
served before turning the upper back on again and restoring
control to the user inputs. This refresh cycle can be detected
as a few s wide pulse of lower MOSFET/ IGT current.
t3< t < t5 The upper remains commanded on for a per iod of time lessthan tREF. At t4, the UP/DOWN time is brought low, com-
manding a lower turn on. Similar to the t0-t1interval, the up-
per turns off after delay tOFFDand the lower turns on afterthe dead time, tD.T.
t5< t < t7 The SP601 is disabled by the ENABLE line low at t5. Previ-ously conducting lower turns off after its delay, tOFFD. Since
the ENABLE line was previously brought low and neither out-
put transistors are conducting, termed as three-state mode.
The state of the output phase waveform remains unknown.
At t6, the ENABLE is once again pulled high. The lower turns
on after delay, tONDB.
t7< t < t9 At t7, the SP601 is disabled and the UP/ DOWN line is toggledto the upper position. The lower turns off and the power devic-
es go into a three-state mode. At t8, upper turn on sequence
begins. Since the auto one shot hasnt timed out yet, the turn
on delay, tONDB, is relatively short.
t9< t < t11 The chip shuts off as the ENABLE line is brought low at t9,and is enabled again at t10as the UP/DOWN line had re-
mained high. Since the disable period was long and the re-
fresh one shot had timed out, the turn on delay, tONDT, is
slow. Keep in mind that the delay time includes the time forautomatic refresh. In an attempt to not further complicate the
drawing, the detailed refresh cycle isnt actually shown.
t11< t < t13 Both inputs are brought low at t11for a duration longer than
tREF. At t13the ENABLE is restored, initiating the turn on se-
quence for the lower. This follows a long period of time where
the one shot had timed out, but in this case the lower is com-
manded on. Since it doesnt need the refresh algorithm, the
turn on delay, tONDB, is fast.
t11< t < t13 This sequence of events depicts the detection of a lower over-current trip. Between t13-t14, the lower is on. Beyond the filter
delay, tOFFTN, the overcurrent trip shuts off the lower driver. A
fraction of a s later, tFN, the flag report delay, FAULT goes low.
t15< t < t16t18< t < t19
By holding both ENABLE and UP/DOWN lines low for the re-
quired fault filter reset time, tR.T., the fault is cleared.
t16< t < t17 The upper is turned on and an overcurrent trip begins. Beyondthe filter delay, tOFFTN, the overcurrent comparator shuts off the
upper drive at t17. Since the control logic can only communicate
upwards, there is no direct means of reporting an upper trip. As
the fault has been remotely captured by the floating upper sec-
tion, shutdown has occurred. The Phase or VOUT node will
quickly fall to a diode drop below common due to inductive fly-
back current. Via the VOUT/VPHASEmonitor this is detected as
not being in agreement with the commanded input and reports
the fault. Reporting this phase out of status delay is tOSVF.
INTERVAL
TOP
BOTTOM
ENABLE
UP/DOWN
FAULT
LOWER
TRIPL
UPPER
TRIPU
PHASE+HV
COM
SP600
SP601
t0
tREF
tD.T.
tOFFD
t1 t2 t3 t4 t5t6 t7 t8 t9 t10 t11 t12 t13
1
0
1
0
1
0
1
0
1
0
1
0
t14 t15t16 t17 t18 t19
1
0
1
0
1
0
tD.T.
tON
tD.T. tONDB
tOFFD
tOFFD
tOFFD
tONDT tOFFD
tONDT
tOFFD
tONDB
tON tOFFTN
tOSVF
tOFFTNtONDB
tFN
tONDB
tR.T. tR.T.
t>tREF
t>tREF
ttREFt>tREF
t0 t1 t2 t3 t4 t5t6 t7 t8 t9 t10 t11 t12 t13 t14 t15t16 t17 t18 t19
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