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Design-For-Testability
course instructor: Mariana ILA, PhD
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Lectures, Project Classes and Grading
Lectures: Tue 16:00 ± 18:00 A416
Project: Tue 18:00 ± 19:00 A410
TextbooksVLSI Test Principles and Architectures: Design for Testability, Edited by Laung-Terng Wang, Cheng-Wen Wu, and Xiaoqing Wen, Elsevier Inc. 2006
Grading will be assigned on:Project ( 50% )
Final ( 50% )
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Projects
Groups of 2 people are strongly recommended
Tentative schedule:Make your choice by week 3 (Tue)
First update: late October Second update: late November
Final presentation: January
May be shared with other classes you are taking
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Sept.2011
Importance and challenges of testing
Modern electronic testing has a history of over 40 yrs.
The IC developed first time in 1958 at TI and FairchildSemicond.
In 2005 cc. $230 billion in sales worldwide
Introd. of new, nanotechnologies (less than 90nmgeometry) made semiconductor test grow steadily
Now test costs can amount to 40% of overall productcost
In order to tackle problems associated with testing, weneed to address them at early stages in the design
Important to expose students and practitioners to mostadvanced techniques VLSI test techniques and DFTarchitectures to help them design better quality products
that can be reliably manufactured in quantity
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Sept.2011
Importance of testing
Moore¶s law: the scale of ICs doubles every18 months
SSI MSI LSI VLSI
10s of transistors 100s 1000s 100.000sTechnologies of less than 90 nm
Clock speeds from 108kHz in 1971 to severalgigahertz today
One faulty transistor or wire can make awhole 100-million transistors chip faulty
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Sept.2010
Rule of ten
How we produce an electronic system?
1. Produce the ICs
2. Use ICs to assemble PCBs
3. Use PCBs to assemble system
Rule of ten:
³The cost of detecting a faulty IC increases
by an order of magnitude as we movethrough each stage of manufacturing,from device level to board level tosystem level and finally to system
operation in the field.´
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Sept.2010
Electronic testing: What, When
WHAT:
1. IC testing
2. PCB testing3. System testing
WHEN:
1. At various manufacturing stages
2. During system operation
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Sept.2010
Electronic testing: Why, For Whom
WHY:
1. To find fault-free ICs, PCBs, systems
2. To improve production yield by analyzing cause of defects when faults are found
3. To ensure fault-free system operation and initiaterepair procedures when faults are detected
FOR WHOM:
1. Designers
2. Test engineers3. Product engineers
4. Managers
5. Manufacturers
6. End-users
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Sept.2010
VLSI DesignFlow
layout.xxlayout.xx
Post-layout
simulation
Specs; Partitioning
Behavioral, then RTL +Testbench(es)
Verification (Incl.
Simulation)
Synthesis
P & R
Mask fabrication
Testbench.v RTL_descr.v
layout.v
Mask ready for testing
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Sept.2010
VLSI Design Verification
Tools to assist design verification process
1. CAD simulation tools
2. Hardware emulation
3. Formal verification methods
Verification ± very time-consuming andexpensive definite impact on time-to-market
Many verification techniques borrowed from testtechnology
Also, test stimulus developed for RTL verificationare used in conjunction with associated outputresponses obtained from simulation, to test VLSIdevice during manufacturing
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Sept.2010
DUT Verification
You draw it
?
So design verification can be considered a form of testing
Once verified, VLSI design goes to fabrication
In parallel, test engineers develop test procedures based on
design spec and fault models assoc. with implem. technology
DescriereRTL
Descriere
post-layout
Testbench
(test stimulus)
n
n
n
m
m
m
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Sept.2010
CUT Testing
Input
test
stimulus
Circuit
Under
Test (CUT)
Output
Response
Analysis
Input1
Input_n
Output1
Output_m
Pass = fault-free
Fail = Faulty
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Sept.2010
Defects
Defect: a flaw or physical imperfection that may lead to afault
First tests performed during manufacturing process are to
detect defects ± the wafer-level tests
Statistical flaws in the materials and masks
used to fabricate ICs are unavoidable it isimpossible for 100% of any IC to be defect-free
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Sept.2010
Testing flow during manufacturing process
Fabricate IC on wafer
Retest packaged devices to eliminate those damaged
during packaging, or put in defective packages
Extract and package defect-free devices
Additional testing to ensure final quality, before going to market
(incl. measurement of parameters such as in/out timing, specs,
voltage, current)
Additional burn-in or stress testing for chips subjected to
high temps and supply voltages
FMA
Additional testing to ensure final quality, before going to market
(incl. measurement of parameters such as in/out timing, specs,
voltage, current)
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Sept.2010
Yield and Reject Rate
Yield = -------------------------------------------------------
Total number of parts fabricated
Number of acceptable parts
Types of yield losses:
1. Catastrophic yield loss: due to random defects
2. Parametric yield losses: due to process variations
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Sept.2010
Undesirable situations during testing an IC
1. A faulty device appears to be a good part passing the test
2. A good device fails the test and appears as faulty
Why:
Poorly designed test (mainly 1) ± when faulty ICs arefinally found in a system, they are returned to the ICmanufacturer, who performs a FMA for possibleimprovements to the VLSI development and manufacturing
processes The lack of DFT
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Sept.2010
Reject Rate = Defect Level
Reject Rate = ----------------------------------------------------------
Total number of parts passing
final tests
Number of faulty parts passing final tests
The reject rate gives an indication of the overall quality of VLSI testing process
E.g. a reject rate of 500 parts per million (PPM) may beconsidered acceptable
A reject rate <= 100 PPM is high-quality
The goal of six-sigma manufacturing (called also zero
defects) is 3.4 PPM or less
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Sept.2010
Electronic System Manufacturing Process
PCB Fabrication
PCB Assembly
Unit Assembly
System Assembly
Bare Board Test
Board Test
Unit Test
System Test
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Sept.2010
Physical Implementation of an IC
The microscopic worldof the physicalstructure of an IC with
six levels of interconnections andeffective transistor channel length of
0.Qm
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Sept.2010
Cause of defects
Any small piece of dust or abnormality of geometricalshape
Process variations affecting transistor channel
length, transistor threshold voltage, metalinterconnect width and thickness, and inter-metallayer dielectric thickness will impact logical andtiming performance
Randomly localized manufacturing imperfections
can result in resistive bridging between metal lines,resistive opens in metal lines, improper viaformation, etc.
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Sept.2010
Nanometer-scale structures vs. CMOS (2)
Nanometer-scale structures:
Allow higher integration and lower cost per transistor, but
Difficulty of testing each transistor increases dueto the increased complexity of the VLSI deviceand increased potential for defects, as well as thedifficulty of detecting the faults produced by those
defects
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Sept.2010
Fault, error, failure
A fault is a representation of a defectreflecting a physical condition that causes acircuit to fail to perform in a required manner
A circuit error is a wrong output signalproduced by a defective circuit
A failure is a deviation in the performance of a circuit or system from its specified behavior
and represents an irreversible state of acomponent such that it must be repaired inorder for it to provide its intended designfunction
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Sept.2010
Fault, error, failure (2)
FaultCircuit defect Circuit error
May lead toSystem failure
Can cause Can result in
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Sept.2010
Exhaustive testing
Test vector = input pattern
2^n = total number of test vectors
If apply all
exhaustive testingIssues:
Impossible to do for big n
Even all applied, still can¶t guarantee that all
possible states have been visited
Input
test
stimulus
Circuit
Under
Test (CUT)
Output
Response
Analysis
Input1
Input_n
Output1
Output_m
Pass = fault-free
Fail = Faulty
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Sept.2010
Structural testing
Uses fault models
Saves time and improves test efficiency
Can¶t guarantee detection of all possible defects
But use of fault models provides a quantitativemeasure of fault-detection capabilities for a given setof test vectors for a targeted fault model
Fault coverage = ---------------------------------------------------
Total number of faultsNumber of detected faults
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Sept.2011
Fault coverage vs. fault detection efficiency
Impossible to get 100% fault coverage due to
Undetectable faults: there is no test to distinguish thefault-free circuit from a faulty circuit containing that
faultDifficult to identify how many are
Fault detection = ---------------------------------------------------
efficiency T otal no. of faults ± No. of undetectable faults
Number of detected faults
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Sept.2010
Defect level
Using equation we can show that a PCB with 40
chips, each having 90% fault coverage and 90%yield could result in a reject rate of 41.9% (419,000PPM)!!!!
Improving fault coverage can be easier and lessexpensive than improving manufacturing yield
because making yield enhancements can be
costly; generating test stimulus with high fault
coverage is very important!!!!
Defect level = 1 ± yield ^ (1 ± fault coverage)
(Williams)
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Sept.2010
Goal of test generation
To find an efficient set of test vectors that detects
all faults considered for a given circuit
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Sept.2010
Fault models
k = no. of types of faults that can occur at eachpotential fault site (k = 2 for most fault models)
n = no. of possible fault sites, depending on the fault
model Assuming there can be only one fault in the circuit,then the total number of possible single faults,referred to as the single-fault model or single-fault
assumption is:No. of single faults = k x n
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Sept.2010
Multiple-fault model
Multiple-fault model : the total number of possiblecombinations of multiple faults, is:
No. of multiple faults = ( k + 1) ̂ n - 1
Single-faultmodel Multiple-faultmodel
More accurate
No. of faults becomestoo large for big k and n
High fault coverage
under single-faultassumption
High fault coverage
for multiple-fault model
Typically the single-fault assumption is used for test generation and evaluation
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Sept.2010
Equivalent faults; Fault collapsing
Equivalent faults: two or more faults thatresult in identical faulty behaviour for allpossible input patterns can be represented
by any single fault from the set of equivalentfaults
So, no. of single faults to be considered for test generation becomes < k x n
called fault collapsing
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Sept.2010
Stuck-at faults
A stuck-at fault transforms the correct valueon the faulty signal line to appear to be stuckat a constant logic value, either a logic 0 or a
logic 1, referred to as stuck-at-0 (SA0) or stuck-at-1 (SA1)
A stuck-at fault affects the state of logicsignals on lines in a logic circuit, including
primary inputs (PIs), primary outputs(POs), internal gate inputs and outputs,fanout stems (sources), and fanout branches
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Sept.2010
An example
x 1
x2
x3
y
a
c
d
e f
b g
h
i
9 signal lines: a to i
b = fanout source
d, e = fanout branches
18 (9 x 2) possible faulty circuits under single-fault assumption
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Sept.2010
Thetruthtable
for fault-freeandfaulty
circuits
x 1 x 2 x 3 000 001 010 011 100 101 110 111
y 0 1 0 0 0 1 1 1
a SA0 0 1 0 0 0 1 0 0a SA1 0 1 1 1 0 1 1 1
b SA0 0 1 0 1 0 1 0 1
b SA1 0 0 0 0 1 1 1 1
c SA0 0 0 0 0 0 0 1 1
c SA1 1 1 0 0 1 1 1 1
d SA0 0 1 0 0 0 1 0 0
d SA1 0 1 0 0 1 1 1 1
e SA0 0 1 0 1 0 1 1 1
e SA1 0 0 0 0 0 0 1 1
f SA0 0 0 0 0 0 0 1 1
f SA1 0 1 0 1 1 1 1 1g SA0 0 1 0 0 0 1 0 0
g SA1 1 1 1 1 1 1 1 1
h SA0 0 0 0 0 0 0 1 1
h SA1 1 1 1 1 1 1 1 1
i SA0 0 0 0 0 0 0 0 0
i SA1 1 1 1 1 1 1 1 1
Test vectors:
011
100
001110
Enough for 100%single stuck-atfault coverage for this circuit.
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Sept.2010
Fault collapsing
Stuck-at fault collapsing typically reduces the totalnumber of faults by 50 to 60%
SA0 at the input to an AND (NAND) gate ~ the SA0 (SA1) atthe output of the gate
SA1 at the input to an OR (NOR) gate ~ SA1 (SA0) at theoutput of the gate
a SA0 (SA1) at the input of an inverter (or buffer) ~ SA1 (SA0)at the output of the inverter (or SA0 (SA1) of a buffer)
a stuck-at fault at the source (output of the driving gate) of afanout-free net ~ same stuck-at fault at the destination (gateinput being driven)
Number of collapsed faults = 2 x (number of POs+number of fanout stems) + total number of gate (including inverter) inputs - total number of inverters
For our example:
No. of collapsed faults = 2x(1+1)+7-1 = 10
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Sept.2010
Theorems for detection of SA-faults in CLBs
Theorem 1.1
A set of test vectors that detects all single stuck-at faults on allprimary inputs of a fanout-free combinational logic circuit will
detect all single stuck-at faults in that circuit.
Theorem 1.2
A set of test vectors that detect all single stuck-at faults on allprimary inputs and all fanout branches of a combinational logiccircuit will detect all single stuck-at faults in that circuit.
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Sept.2010
Stuck-at fault model for sequential circuits
High fault coverage test generation for sequentialcircuits is much more difficult than for combinationalcircuits because, for most faults in a sequential logiccircuit, it is necessary to generate sequences of test
vectors
DFT techniques are frequently used to easesequential circuit test generation
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Sept.2010
Delay faults
Fault-free operation of a logic circuit means:performing the logic function correctly
propagating the correct logic signals along paths within aspecified time limit
A delay fault causes excessive delay along a pathsuch that the total propagation delay falls outside thespecified limit
2 types of delay faults:Gate-delay fault (& transition fault) model: time interval
taken for a transition from the gate input to its outputexceeds its specified range
Path-delay fault: the cumulative propagation delay along asignal path through the CUT
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Sept.2010
Delay faults (2)
x 1
x2
x3
y 2
3
0 0
0 1
v2 v1
1 1
3 t = 7
t = 0 t = 2
t = 5
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Sept.2011
Delay faults (3) ± issues due to nanometer technologies
The portion of delay contributed by gates reduceswhile the delay due to interconnect becomesdominant
If clock frequencies increase with scaling, then on-chip inductances can play a role in determining theinterconnect delay for long wide wires, such as thosein clock trees and buses
Increase of cross-coupling capacitance andinductance between interconnects, leading to severecrosstalk effects, resulting in improper functioning of a chip
So, path delay is not equal to the sum of all delays of
gates along the path
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Sept.2011
Crosstalk effects
2 categories:Crosstalk glitch: a pulse that is provoked by couplingeffects among interconnect lines. The magnitude of theglitch depends on the ratio of the coupling capacitance to
the line-to-ground capacitanceCrosstalk delay: a signal delay that is provoked by thesame coupling effects among interconnect lines, but it maybe produced even if line drivers are balanced but have largeloads (it adds up to gate and interconnects delays)
So, critical need to develop testing techniques for manufacturing defects that produce crosstalk effects
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Sept.2010
Pattern Sensitivity and Coupling Faults
In high - density RAMsThe contents of a cell or the ability of a memorycell to change can be influenced by the contents
of its neighboring cells, referred to as a patternsensitivity fault
Coupling fault results when a transition in onecell causes the content of another cell to change
For memory testing tests for pattern sensitivitycoupling faultsstuck-at faults
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Sept.2011
March LR Algorithm
One of most efficient RAM test algorithms (in terms of test timeand fault detection capability)
Can detect:
pattern sensitivity faults
intra-word coupling faults
bridging faultsTest time on order of 16N (N = no. of address locations)
Test Algorithm March Test Sequence
March LR (w0);(r0, w1);(r1, w0, r0, r0,
w1);(r1, w0);(r0, w1, r1, r1, w0);(r0)
Notation: w0=write 0 (or all 0¶s); r1=read 1 (or all 1¶s); =address up; =address
down; =address either way.
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Sept.2010
Levels of Abstractions in Testing
BehaviouralRTL levels
Gate level
Switch level: when the switch-level model for each gate in thenetlist is substituted, we obtain an accurate abstraction of thenetlist used for physical layout
Physical level: most important for VLSI testing because it
provides the actual layout and routing information for thefabricated device
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Testing at Behavioural and RTL Levels
Common practice methodology for ASIC design is:design, simulate, and synthesize at RTL level
³Black boxes´ or IPs cores are often incorporated in SOCdesign, for which there is very little, if any structural information.
Traditional automatic test pattern generation (ATPG) tools
cannot effectively handle designs including blocks withimplementation detail unknown or subject to change
However, several approaches to test pattern generation at RTLhave been proposed. Most of these approaches can generate
test patterns of good quality, sometimes comparable to gate-level ATPG tools
They lack general applicability and so are not widely accepted
Sept.2011
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RTL testing ± an example
f = abc+abc+xabc, where x = don¶t care
Sept.2011
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RTL Testing
Despite cons, it is desirable to move ATPG
operations toward higher levels of abstraction
while targeting new types of faults in deep
submicron devices
Main advantages of high-level approaches are :
compact test sets
reduced computation time
It is expected that this trend will continue
Sept.2011
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Gate Level Testing
At this level the stuck-at fault model can be applied
There are many commercial ATPG and fault simulation
tools available
Usually the stuck-at fault model is also employed to
evaluate the effectiveness of the input stimuli used for
simulation-based design verification.
So, the design verification stimuli are often also used for
fault detection during manufacturing testing
Also delay fault models and delay testing are traditionally
based on gate-level description
Still, test development at the gate level is not enough for
deep submicron designs
Sept.2011
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Switch Level Testing
Transistor fault models (stuck-open and stuck-short) can be applied and evaluated based on the switch-level model
for each gate in the netlist , which represents an accurate
abstraction of the netlist used for physical layout
Transmission gate and tristate buffer faults can also betested at the switch level
Also, a defect-based test methodology is more effective
with a switch-level model of circuit (contains more
detailed structural info than a gate-level and will yield a
more accurate defect coverage analysis)
NB: switch-level description is more complicated than the
gate-level for both ATPG and fault simulation
Sept.2011
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Physical Level Testing
Physical Level provides the actual layout and routing
information for the fabricated device
So, gives most accurate information for delay faults,
crosstalk effects, bridging faults and interconnect delays,for more accurate delay fault analysis
For deep submicron IC chips, in order to characterize
electrical properties of interconnections, a distributed
resistance±inductance±capacitance (RLC) model is
based on the physical layout
RLC model is used to analyze and test for potential
crosstalk problems
Sept.2011
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Physical Level Testing (2)
Bridging fault sites can be determined by extracting
the capacitance between the wires from the physical
design ± it provides an accurate determination of
those wires that are adjacent and hence likely to
sustain bridging faults
Also, the value of the capacitance between two
adjacent wires is proportional to the distance between
the wires and/or the length of adjacency
So, fault sites with the highest capacitance value can
be targeted for test generation and evaluation as these
sites have a higher probability of incurring bridging
faultsSept.2011
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HISTORICAL REVIEW OF VLSI TEST TECHNOLOGY
Automatic Test Equipment (ATE)
Automatic Test Pattern Generation (ATPG)
Fault Simulation
Digital Circuit Testing
Analog and Mixed-Signal Circuit Testing
DFT
Sept.2011
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Design For Testability (DFT)
Test engineers usually have to construct testvectors AFTER the design is completed.
This invariably requires a substantial amount
of time and effort that could be avoided if testing is considered early in the design flowto make the design more testable.
As a result, integration of design and test,referred to as design for testability (DFT),was proposed in the 1970s.
Sept.2011
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DFT Techniques
To structurally test circuits, we need to control
and observe logic values of internal lines!
Difficult, especially for sequential circuits!
DFT techniques help find those parts of a digital
circuit that will be most difficult to test and to
assist in test pattern generation for fault detection
Sept.2011
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DFT Techniques - Categories
Ad-hoc DFT techniques
Level-sensitive scan design (LSSD) or scan
design
Built-in self-test (BIST)
Sept.2011
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Ad-hoc DFT Techniques
Goal: to target only those portions of the circuit
that would be difficult to test and to add circuitry
to improve the controllability or observability
Use test point insertion to access internal nodesdirectly
E.g. a multiplexer inserted to control or observe
an internal node
Sept.2011
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Level-Sensitive Scan Design (LSSD)
It is latch-based
Testability is improved by adding extra logic to
each flip-flop in the circuit to form a shift register,
or scan chain
Sept.2011
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Built-In-Self-Test (BIST)
Integrates a test-pattern generator (TPG) and an
output response analyzer (OR A ) in the VLSI
device to perform testing internal to the IC
Because the test circuitry resides with the CUT,BIST can be used at all levels of testing, from
wafer through system-level testing
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Board Testing
In the µ70s and µ80s, PCBs were tested byprobing the backs of the boards with probes(also called nails) in a bed-of-nails tester.
The probes are positioned to contact varioussolder points on the PCB in order to forcesignal values at the component pins andmonitor the output responses
A PCB tester can perform analog and digital functional tests
is designed to be modular and flexible enough tointegrate different external instruments
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Board Testing (2)
Steps to test a PCB:
Bare board testing (to target shorts and opens onall interconnections)
Testing of components to be assembled on PCB
Test on the PCB tester of assembled PCB:Solder paste inspection
automated optical and x-ray inspections
in-circuit (bed-of-nails)
Problem: When surface-mount devices onPCBs appeared in mid-1980s:
pins of the package did not go through the boardto guarantee contact sites on the bottom of the
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Boundary-Scan
Solution: boundary-scan, proposed by JTAG,i.e.
inserted logic to provide a scan path through all
I/O buffers of ICs to assist in testing theassembled PCB
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Boundary-scan cell applied to bidirectional I/O buffer
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Boundary-Scan (2)
Scan chain provides ability to shift in test vectors tobe applied through the pad to the pins andinterconnections on the PCB. Output responses arecaptured at the input buffers on other devices on the
PCB and subsequently shifted out for fault detectionBoundary scan provides access to the various signalnodes on a PCB without the need for physicalprobes
T est Access Port (TAP) provides access to theboundary scan chain through a four-wire serial bus
interface, in conjunction with instructions transmittedover the interface
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Boundary-Scan (3)
Boundary scan interface also providesaccess to DFT features (LSSD or BIST),designed and implemented in the VLSIdevices for board and system-level testing.The boundary scan description language
(BSDL) provides a mechanism with which ICmanufacturers can describe testability
features in a chip
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4-wire serialbus interface
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SoC Testing
SOCs incorporate embedded cores, difficult toaccess during testing
In 1997 IEEE developed a scalable wrapper
architecture and access mechanism similar toboundary scan, to enable test access toembedded cores and the associatedinterconnect between embedded cores
independent of the underlying functionality of theSOC or its individual embedded cores
creates necessary testability requirements for detection and diagnosis of faults for debug andyield enhancement
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Cost of Manufacturing Testing
0.5-1.0GHz, analog instruments,1,024 digitalpins: ATE purchase price
= $1.2M + 1,024 x $3,000 = $4.272M
Running cost (five-year linear depreciation)= Depreciation + Maintenance + Operation
= $0.854M + $0.085M + $0.5M
= $1.439M/year
Test cost (24 hour ATE operation)= $1.439M/(365 x 24 x 3,600)
= 4.5 cents/second
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Design for Testability Basic Techniques
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Controllability and Observability
C ontrollability of a signal reflects thedifficulty of setting a signal line to a requiredlogic value from primary inputs
Observability of a signal reflects thedifficulty of propagating the logic value of thesignal line to primary outputs
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Testing of Combinational vs. Sequential Circs.
Level of the combinational logic increases
The testability of combinational logicdecreases
Good testability for sequential circuits isdifficult to achieve due to:many internal states, so setting a sequential circuitto a required internal state can require a very largenumber of input events
Difficulty to identify the exact internal state of asequential circuit from the primary outputs
a more structured approach for testing designs withlarge amounts of sequential logic is required aspart of a methodical DFT approach
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Structured DFT Approaches
Why:
to allow DFT engineers to follow a methodicalprocess for improving the testability of a design
are much easier to automate: EDA vendorsprovide sophisticated DFT tools to simplify andspeed up DFT tasks (e.g. scan design)
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Ad-hoc DFT
Typical ad-hoc DFT techniques
A2-A6: good design practices
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Test Point Insertion (TPI)
TPI is an ad hoc DFT technique for improvingthe controllability and observability of internalnodes. Testability analysis is typically used to
identify the internal nodes where test pointsshould be inserted, in the form of control or observation points.
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Observation Point Insertion (OPI)
OP2 shows the structure of an OP: MUX + FF
SE = 0 and active CK logic values of the low-observability nodes arecaptured into the DFF
SE = 1 the 3 DFF operate as a shift register, allowing to observe the
captured logic values through OP_output during sequential clock cycles
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Control Point Insertion (CPI)
CP2 shows the structure of an CP: MUX + FF
During normal operation TM=0
During test TM=1; the 3 DFF form a shift-reg that shifts the CM_input to
control the destination end of nodes
OriginalConnection
is cut
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Control Point Insertion (CPI) (2)
Controllability of node is dramatically improvedBUT, additional delay appears in logic path
care must be taken not to insert control
points on a critical path Or better: add a scan point
Scan Point: a combination of a CP and an OP,
instead of a CP, as this allows to observe thesource end as well.
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