Digital System Ch4-1
Verilog HDL
Ping-Liang Lai (賴秉樑 )
Digital System數位系統
Digital System Ch4-2
Outline
Design Style HDL Modeling
Behavioral Modeling Structural Modeling
Description Styles Structural styles
» Gate level» Structural Hierarchy
Data Flow Behavioral styles
» Register Transfer Level Mixed
Simulation: Test bench
Digital System Ch4-3
Design Style: Schematics, Netlist, and HDLs
Language
module adder(a, b, c, s)input [31:0] a, b;output [31:0] s;output c;…endmodule.
VDD V 0 3VM1 Z IN 0 0 NCHM2 Z IN V V PCHR1 A IN 15C1 Z 0 1PVIN A 0 PWL (0 0 1N 3V)
Schematic
Gate
-Level
Sw
itch-Le
vel
HDL
Netlist
Sch
em
atic
Digital System Ch4-4
Hardware Description Language
Better be standard than be proprietary Can describe a design at some levels of abstraction Can be interpreted at many level of abstraction
Cross functional, statistical behavioral, multi-cycles behavioral, RTL
Can be used to document the complete system design tasks Testing, simulation, ..., related activities
User define types, functions and packages Comprehensive and easy to learn
Digital System Ch4-5
Design Methodology
Top-Down Design Start with system specification Decompose into subsystems, components, until indivisible Realize the components
Bottom-up Design Start with available building blocks Interconnect building blocks into subsystems, then system Achieve a system with desired specification
Meet in the middle A combination of both
Digital System Ch4-6
What is Verilog HDL?
Hardware description language Mixed level modeling
Behavioral» Algorithmic» Register transfer
Structural» Gate» Switch
Single language for design and simulation Built-in primitives, logic function User-defined primitives Built-in data types High-level programming constructs
switch
switch
gate
switch gate
algo
Digital System Ch4-7
Basic unit (Module)
Module communication externally with input, output and bidirectional ports.
A module can be instantiated in another module.
Module module_name(port_list)declarations:
reg, wire, parameter, input, output, inout, function, task
statements:initial blockalways blockmodule instantiationgate instantiationUDP instantiationcontinuous assignment
endmodule
Digital System Ch4-8
Behavioral Modeling
Procedural blocks initial block: executes only once always block: executes in a loop
Block execution is triggered based on user-specified conditional always @ (posedge clk)
All procedural blocks are automatically set at time 0 and execute concurrently
reg is the main data type that is manipulated within a procedural block It holds its value until assigned a new value
Digital System Ch4-9
An Example
Module FA_SEQ(A, B, CIN, SUM, COUT)input A, B, CIN;output SUM, COUT;reg SUM, COUT;reg T1, T2, T3;always @ (A or B or CIN) /* at any time (A or B or CIN) changes */
begin /* when (A or B or CIN) changes, the block executes again */
// sequential executionSUM = (A ^ B) ^ CIN;T1 = A & CIN;T2 = B & CIN;T3 = A & B;COUT = (T1 | T2) | T3;// SUM, T1, T2, T3, COUT must be register data-typeend
endmodule
Digital System Ch4-10
Structural Modeling
Gate-level design Built-in set of gate primitives interconnected by nets
and, nand, nor, ...
Switch-level design Built-in switch-level primitives interconnected by nets nmos, ...
Nets are continuously driven (like wires)
Digital System Ch4-11
An Example
module FA_STR(A, B, CIN, SUM, COUT)input A, B, CIN;output SUM, COUT;wire S1, S2, S3, S4, S5;
xor /* gate */X1(S1, A, B),X2(SUM, S1, CIN);
// X1, X2 are gate instantiation and
A1(S2, A, B),A2(S3, B, CIN),A3(S4, A, CIN);
orO1(S5, S2, S3),O2(COUT, S4, S5);
endmodule
A
B
CIN
X1S1 X2
A1S2
A2
S3
A3S4
O1S5 O2
SUM
COUT
Digital System Ch4-12
Mixed Styles Modeling
Structural and behavioral modelings can be freely mixed. Values produced by procedural blocks can drive gates and
switches. Values from gates and switches can in turn be used with
procedural blocks.
Digital System Ch4-13
An Example
module FA_MIX(A, B, CIN, SUM, COUT)input A, B, CIN;output SUM, COUT;reg COUT;reg T1, T2, T3;wire S1;xor X1(S1, A, B); // gate instantiationalways @ (A or B or CIN) // Always blockbegin
T1 = A & CIN;T2 = B & CIN;T3 = A & B;COUT = (T1 | T2 | T3);
endassign SUM = S1 ^ CIN; // Continuous assignment
endmodule
Digital System Ch4-14
Description Styles
Structural styles Gate level Structural Hierarchy
Data Flow Behavioral styles
Register Transfer Level
Mixed
Digital System Ch4-15
Gate Level Description Style
Supports the following Verilog “gate type” and, nand, or, nor, xor, xnor, not
The output or bidirectional terminals always come first in the terminal list, followed by the input terminals For example: nand N1 (Out1, In1, In2, In3, In4); // 4-input NAND xor X1 (Out2, In5, In6); // 2-input XOR
In the lowest level of modeling and so the real benefits of using a high level synthesis tool are not been exploited
Digital System Ch4-16
Gate Level Description Style
Example 1: Half Adder
module HA (SUM, COUT, A, B)input A, B;output SUM, COUT;
xor XOR2 (SUM, A, B);and AND2 (COUT, A, B);endmodule
A
BCOUTAND2
SUMXOR2
Digital System Ch4-17
Structural Hierarchy Description Style
Direct instantiation and connection of models from a separate calling model to form structural hierarchy in a design Gate level
A module may be declared anywhere in a design relative to where it is called
Signals in the higher “calling” model are connected to signals in the lower “called” model by named association positional association
Digital System Ch4-18
Structural Hierarchy Description Style
Example 2: Full Adder
module FULL_ADD(A, B, CIN, SUM, COUT)input A, B;output SUM, COUT;
wire NET1, NET2, NET3; HA U1 (NET1, NET2, B, CIN),
U2 (SUM, NET3, A, NET1); OR2 U3 (COUT, NET2, NET3);endmodule
A
BCOUT
SUM
OR
HA
HACIN
U2NET1
U3
NET2
U1
NET3
Digital System Ch4-19
Structural Hierarchy Description Style
Example 3: Decoder
module NAND3 (A, B, C, Y)input A, B, C;output Y;
assign Y = !(A & B & C);endmodulemodule INV (A, Y);
input A;output Y;
assign Y = !A;endmodule
module DECODER2X4 (Y, A, B, ENABLE)
input A, B, ENABLE;output [3:0] Y;
// N0 and N1 use positional associations NAND3N0 (ABAR, BBAR, ENABLE, Y[0]);
N1 (ABAR, B, ENABLE, Y[1]); // N2 and N3 use named associations
N2 (.C(ENABLE),.Y(Y[2]),.B(BBAR),.A(A)),
N3 (.B(B),.Y(Y[3]),.A(A),.C(ENABLE)); INV I0 (A,ABAR), // positional
I1 (.Y(BBAR),.A(B)); // namedendmodule
Digital System Ch4-20
Data Flow Description Style
Model combinational logic only Continuous signal assignments of type “wire” defined using the
“assign”statement Continuous assignment statements are concurrent Right-hand side can be any function expression Left-hand side (target) can be a:
part-select bit-select concatenation of both
Specified drive strengths and delays in an expression have no meaning to synthesis and are ignored
Digital System Ch4-21
Data Flow Description Style
Statements can take two forms: Explicit Specified in the declaration of the target wire
Explicit // declarations first input [3:0] A, B; input CIN; output [3:0] SUM; output COUT; // theassignment assign {COUT, SUM} = A + B + CIN;
Specified in a wire declaration // declaration and assignment combined wire [3:0] parity = A ^ B;
Digital System Ch4-22
Data Flow Description Style
Example 4: Half Adder
module HALF_ADD(SUM, COUT, A, B)input A, B;output SUM, COUT;
assign SUM = (A ^ B); assign COUT = (A & B);endmodule
Digital System Ch4-23
RTL Description Style
Using the “always” block Can represent combinational
logic, synchronous logic, or both
Statements within a “always” block are sequential; their order of appearance is important
Style of representation is very similar to C
Example 5: Full Adder
module FULL_ADD (SUM, COUT, A, B, CIN)input A, B, CIN;output COUT, SUM;reg COUT, SUM;
always @ (A or B or CIN) begininteger T1, T2, T3;
SUM = (A ^ B) ^ CIN;T1 = A & CIN;T2 = B & CIN;T3 = A & B;COUT = (T1 | T2) | T3;
endendmodule
Digital System Ch4-24
Mixed Description Style
Example 6: Full Adder
module FA_MIX (SUM, COUT, A, B, CIN)input A, B, CIN;output SUM, COUT;reg COUT;wire S1;XOR X1 (S1, A, B);always @ (A or B or CIN)begin
integer T1, T2, T3;T1 = A & B;T2 = A & CIN;T3 = B & CIN;COUT = ( T1 | T2) | T3;
endassign SUM = S1 ^ CIN;
endmodule
Digital System Ch4-25
Simulation
One language for design, stimulus, control, saving responses, and verification Stimulus and control
» Use initial procedural block Saving responses
» save on change» stored data
Verification» automatic compares with expected responses
Digital System Ch4-26
A Test Bench
module TOPreg PA, PB, PCI;wire PCO, PSUM;
// Instantiate module under test;FA_SEQ F1 (PA, PB, PCI, PSUM, PCO);// Positional.
initial begin: ONLY_ONCE //block label
reg [2:0] PAL; //3 bit vectorfor (PAL=0;PAL<8;PAL=PAL+1)begin
{PA, PB, PCI} = PAL; //PA: MSB, PCI:LSM,#5 $display (“PA,PB,PCI=%b%b%b”, PA, PB,
PCI, “ :::PCO,PSUM=%b%b”, PCO,PSUM);end$stop;
endendmodule
statements executed
sequentially
System-defined task
Delay 5ns after previous statement executed
Digital System Ch4-27
Another Example
module RS_FF (Q, QBAR, R, S);output Q, QBAR;input R, S;
nand #1 (Q, R, QBAR);nand #1 (QBAR, S, Q);
endmodulemodule test;
reg TS, TR;
//Instantiate module under test;RS_FF INST_A (.Q(TQ), .QBAR(TQB), .S(TS), .R(TR));// Using name association.
// Apply stimulusinitial begin
TR = 0; TS = 0;#5 TS = 1;#5 TS = 0; TR = 1;
1 time unit (ns) delay
not definedimplicitly defined, onebit wire
Connect TQ to Q
Q
QBAR
Q
S
TR
TS
TQ
TQB
Digital System Ch4-28
#5 TS = 1; TR = 0;#5 TS = 0;#5 TR = 1;#5 $stop;
end
// Display output;initial
$monitor (“At time %t,” $time, “TR=%b, TS=%b, TQ=%b, TQB=%b”,TR, TS, TQ, TQB);
endmodule
System-defined task