-
1
nay. PLC S7-300
trnPLC S7-300
-300
CH NG II : T P L NH LADER C A PLC S7-300
Ch-ng 3: b bin i PID trn S7 -300
-
2
-300
, SIMATIC M7,
SIMATIC C7, SIMATIC S5...
1.1. cu trc c bn ca mt trm Simatic s7 -300.
SIMATIC S7 - ,
, ,
, :
,
,
, ,
,
, ,
rack.
-
3
Hinh1:
* Module CPU: , , , cc
, , (RS485)
SIMATIC S7 - , ,
(MPI)
NET LAN.
, , ,
,
S7- :
c ,
,
* : ( ) :
Module (PS - Power Supply) : 2A, 5A,10A.
(SM - Sign Module ) :
-
4
(DI - Digital Input)
,
(DO - Digital Output)
,
/ (DI/DO - Digital Input/ Digital Output)
/ /
16 vo /
(AI - Analog Input)
,
(AO - Analog Output)
,
/ (AI/AO - Analog Input/Analog
Output) /
4 vo / /
(IM - Interface Module)
module CPU.
(FM - Function Module)
: , , module
PID...
(CP - Communication Module)
1.2. cu trc ca trm tch cc trong phng th nghim.
C - 300, CPU 315 -
S7 -300, CPU 315 -
:
(Power Supply),
-
5
, - 2DP.
(Interface module), - 1.
(Function module), - 350.
,
(slot)
(back plane bus).
1.3. cc thnh phn ca trm Simatic S7 -300.
a. Rack.
: 6ES7 390 - 1AF30 - 0AA0.
thanh rack,
/ra
( Power Supply ).
: 6ES7 307 - 1KA00 - 0AA0
(PS) / 230VAC
, /
(10A).
:
-
6
120/ 230VAC
/
20ms
hp.
50/ 60 Hz.
1,7 A
3,5 A
24VDC.
24VDC + 5 %
10A.
30 W.
0
- 2 DP.
Module CPU 315 ,
, my
:
- :
(Status and fault LEDs).
-DP.
( Terminals for power supply and functional ground).
-
7
: , bao
:
Hnh 1.3: CPU 315 - 2 DP
SF:
BATF:
DC 5V: +5VDC.
RUN:
STOP:
BUSF:
:
xo , :
RUN - P: ,
STOP.
RUN:
-
8
STOP:
MRES:
: (Multi Poit
Interface) ,
DP:
PROFIBUS - ,
Hnh 1.4: (PLC)
:
: tnh ton,
trnh
K
trung tm
+
Timer
B
vo / ra
ra onboard
CPU
Bus
-
9
: ,
RAM, EEPROM...
: / , cn
/
(Timer):
(Counter):
/ra Onboard: /
CPU
:
,
:
,
Bus:
, th
, ,
, ,
(
, )
(64Kbyte)
,
:
, ( , con,
)
-
10
,
:
, sao chp,
,
:
,
cc c
,
, , ,
/ RUN, STOP...
: (PC, PG...)
,
,
, ,
: :
/OP.
-
11
(PC) (Multi Point Interface), cc I /O phn tn,
(MPI)
(PCs, OPs),
s7 300/400,
PROFIBUS
:
, , ,
2DP.
CPU 315 - 2DP
RAM (
)
64Kbytes
16K_ ( built in )
+ Built - in.
+ Plug - in.
96 Kbytes RAM.
512 Kbytes FEPROM.
ng.
+
+
, ,
,
C
STEP 7
- (OB).
- (FBs).
- Hm (Functions) (FC).
- (DB).
- (SBF, SFC).
128 FC, 128 FB, 127 DB.
-
12
- (OB1).
- (OB 35).
- (OB 10).
- (OB 40).
- (OB 100).
Binary logic, parenthesis command,
resultn assignment, save, count,
load, transfer, compare, shift,
rotate...
dng
(SFC)
, ,
, ,
,
:
+
+
+ /
+
+
+
0, 0,6 s
1 s
12 s
2 s
50 s
150 ms (preset),
+ (
) khi c
+ (
) khi
2048
(
).
(
).
-
13
+
+ i
+
64
+
+
+
128
C
(MPI)
+
+
+
,
/ PCs, OP, cc S7 -
300/ 400, M7 300/ 400,
,
187,5 kbit/ s
- : 50m.
- : 1100m.
- : 9100 m
qua cp quang: 23,8 km (
couples hnh sao hay OLM).
/ ra On-board
+ / ,
/ O 256/ 256 bytes
/ 1024 knh
/ 128 knh
32
-
14
1/ 1
64/ 32
DP
122bytes
8
(master/ slave) 1 (CPU 342 - 5)
1(built-in, master/ slaver)
+
+
24 VDC
20, 8,8 VDC
1 A
8W
(W x H x D) (mm) 80 x 125 x 130
+ CPU
+
530
16
+ FM
+ CP, point-to-point
+ CP, LAN
8
4
2
+
+
+ S7 - GRAPH
+ S7 - HiGraph
+ S7 - SCL
+ CFC
c
c
c
c
c
c
-
15
CH NG II : T P L NH LADER C A PLC S7-300
2.1. Tng quan Bit Logic
:
--- | | ---
--- | / | ---
---
---
--- (#) ---
--- | NOT | ---
---
---
-Reset Flip Flop
-Set Flip Flop
-
16
2.1.2
Vng
BOOl I,Q,M,L,D,T,C
--- | | ---
--- | | --- V
BR CC1 CC) OV OS OR STA RLO /FC
_ _ _ _ _ X X X 1
2.1.3
Vng
BOOl I,Q,M,L,D,T,C K
--- | / | ---
ng
logic(RLO)="1".
ra.
ng logic(RLO)="0".
--- | / | ---
logic AND. Khi
-
17
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ X X X 1
2.1.4.
Vng
< address1> BOOl I,Q,M,L,D,T,C Qut bit
< address2> BOOl I,Q,M,L,D,T,C Qut bit
M
2.1.5 . --|NOT|-- bit
--|NOT|--
--|NOT|--
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ _ 1 X _
Address1 Address2
Address1 Address2
-
18
2.1.6. ---( )
---( )
Tham Vng
< address> BOOl I, Q, M, L, D Gn bit
---
logic relay.
--- NOT | --
-
MCR (Master Control Relay)
.
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ 0 X _ 0
2.1.7. ---( # )--- L ra trung bnh
---( # )---
Tham Vng
< address> BOOl I, Q, M, *L, D Gn bit
-
19
M
--- (#) ---
bnh
cc --- (#) --- --- (#) --
-
--- NOT | --- ) .
ra trung bnh
trong
.
l
:
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ 0 X _ 1
2.1.8. ---( R ) Reset
---( R )
Tham Vng
< address> BOOl I, Q, M, L, D, T,
C
Reset bit
--- (R) ( khi RLO
n trong
-
20
nh i gian (T
no p (C
no "0".
trung bnh
trong
.
g thi:
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ 0 X _ 0
2.1.10. RS Reset-Set Flip Flop
BOOL I, Q, M, L, D
S BOOL I, Q, M, L, D
R BOOL I, Q, M, L, D
Q BOOL I, Q, M, L, D
RS (Reset Flip Flop-
R
S S
R
Q
-
21
chn S=1 th
" khng
MCR off,
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ X X X 1
2.1.12. ---( N )---
---( N )---
Tham
< address> BOOl I, Q, M, L, D
RLO
--- (N) ---
-
22
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ 0 X X 1
2.1.13. ---( P )--- L p
: ---( P )---
Tham
< address> BOOl I, Q, M, L, D
,
RLO
--- (P) --- (
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ 0 X X 1
2.1.14. --- (SAVE)
: --- (SAVE)
:
---
-
23
i.
BR CC1 CC0 OV OS OR STA RLO /FC
X _ _ _ _ _ _ _ _
2.1.15. NEG
:
BOOL I, Q, M, L, D Q
BOOL I, Q, M, L, D
Q BOOL I, Q, M, L, D
NEG (
-
24
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ X 1 X 1
2.1.16. POS
BOOL I, Q, M, L, D
BOOL I, Q, M, L, D
Q BOOL I, Q, M, L, D
POS (
.
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ X 1 X 1
M_BIT
POS
Q
address1
address2
-
25
2.2. Lnh So s nh
2.2.1.
<
Cc RLO
I so snh
D So snh
2.2.2. CMP? I s
I
IN2
IN1
CMP I
IN2
IN1
CMP I
IN2
IN1
CMP
I
IN2
IN1
CMP I
IN2
IN1
CMP I
IN2
IN1
CMP
-
26
Tham
Vng
box input BOOL
I, Q, M, L, D
box output BOOL
I, Q, M, L, D
IN1 INT I, Q, M, L, D
IN2 INT I, Q, M, L, D
Cc RLO ic
BR CC1 CC0 OV OS OR STA RLO /FC
X X X 0 _ 0 X X 1
-
27
2.2.3. CMP ? D so snh hai
Tham
Vng
box input BOOL
I, Q, M, L, D
box output BOOL
I, Q, M, L, D
IN1 INT I, Q, M, L, D
IN2 INT I, Q, M, L, D
CMP? D (So snh hai
Cc RLO
D
IN2
IN1
CMP D
IN2
IN1
CMP D
IN2
IN1
CMP
D
IN2
IN1
CMP D
IN2
IN1
CMP D
IN2
IN1
CMP
-
28
BR CC1 CC0 OV OS OR STA RLO /FC
X X X 0 _ 0 X X 1
2.2.4. CMP ? R
Tham
Vng
box input BOOL
I, Q, M, L, D
box output BOOL
I, Q, M, L, D
IN1 INT I, Q, M, L, D
IN2 INT I, Q, M, L, D
CMP? I
R
IN2
IN1
CMP R
IN2
IN1
CMP R
IN2
IN1
CMP
R
IN2
IN1
CMP R
IN2
IN1
CMP R
IN2
IN1
CMP
-
29
Cc RLO
BR CC1 CC0 OV OS OR STA RLO /FC
X X X 0 _ 0 X X 1
2.3. H-ng dn chuyn i
ho
BCD
uyn
BCD
2.
EN
IN OUT
ENO
BCD_I
-
30
Tham Vng
EN BOOL I, Q, M, L, D Enable input
ENO BOOL I, Q, M, L, D Enable output
IN WORD I, Q, M, L, D BCD number
OUT INT I, Q, M, L, D Integer value of BCD
number
16
-
BR CC1 CC0 OV OS OR STA RLO /FC
t
1 _ _ _ _ 0 1 1 1
2.
Tham Vng
EN BOOL I, Q, M, L, D Enable input
ENO BOOL I, Q, M, L, D Enable output
IN WORD I, Q, M, L, D Integer number
OUT INT I, Q, M, L, D BCD value of integer
number
a 999
EN
IN OUT
ENO
I_BCD
-
31
BR CC1 CC0 OV OS OR STA RLO /FC
1 _ _ _ _ 0 1 1 1
2.
Tham Vng
EN BOOL I, Q, M, L, D Enable input
ENO BOOL I, Q, M, L, D Enable output
IN WORD I, Q, M, L, D Integer value to convert
OUT INT I, Q, M, L, D Double integer result
Bit.
BR CC1 CC0 OV OS OR STA RLO /FC
1 _ _ _ _ 0 1 1 1
2.
EN
IN OUT
ENO
I_DINT
EN
IN OUT
ENO
BCD_DI
-
32
Tham Vng
EN BOOL I, Q, M, L, D Enable input
ENO BOOL I, Q, M, L, D Enable output
IN WORD I, Q, M, L, D BCD number
OUT INT I, Q, M, L, D Double integer value of
BCD number
BR CC1 CC0 OV OS OR STA RLO /FC
1 _ _ _ _ 0 1 1 1
2. h DI_BCD
Tham Vng
EN BOOL I, Q, M, L, D Enable input
ENO BOOL I, Q, M, L, D Enable output
IN WORD I, Q, M, L, D Double integer number
OUT INT I, Q, M, L, D BCD value of a double
integer number
EN
IN OUT
ENO
DI_BCD
-
33
a 9999999
BR CC1 CC0 OV OS OR STA RLO /FC
1 _ _ _ _ 0 1 1 1
2.3.6. DI_REAL
Tham u Vng
EN BOOL I, Q, M, L, D Enable input
ENO BOOL I, Q, M, L, D Enable output
IN WORD I, Q, M, L, D Double integer value to
convert
OUT INT I, Q, M, L, D Floating-point number result
BR CC1 CC0 OV OS OR STA RLO /FC
1 _ _ _ _ 0 1 1 1
EN
IN OUT
ENO
DI_REAL
-
34
2.
Tham Vng
EN BOOL I, Q, M, L, D Enable input
ENO BOOL I, Q, M, L, D Enable output
IN WORD I, Q, M, L, D Integer input value
OUT INT I, Q, M, L, D Ones compelement of the
integer
BR CC1 CC0 OV OS OR STA RLO /FC
1 _ _ _ _ 0 1 1 1
3.8.
EN
IN OUT
ENO
INV_I
EN
IN OUT
ENO
INV_ID
-
35
Tham Vng
EN BOOL I, Q, M, L, D Enable input
ENO BOOL I, Q, M, L, D Enable output
IN WORD I, Q, M, L, D Double integer input value
OUT INT I, Q, M, L, D Ones compelement of the
Double integer IN
Bit
BR CC1 CC0 OV OS OR STA RLO /FC
1 _ _ _ _ 0 1 1 1
2.4. COUNTER
2.4.1.
C c dnh ring cho Counter a CPU.
- C
ladder counters.
Cc counters p l
:
-999.
-
36
S_CD
S_CU
---( SC )
---( CU )
---( CD )
0-999, v a
gi
counter
-
37
2.
Tham Vng
C no COUNTER C vi truy
CU BOOL I, Q, M, L, D
CD BOOL I, Q, M, L, D
S BOOL I, Q, M, L, D
counter
PV WORD I, Q, M, L, D
v constant -999
PV WORD I, Q, M, L, D
R BOOL I, Q, M, L, D
CV WORD I, Q, M, L, D
CV_BCD WORD I, Q, M, L, D
BCD
Q BOOL I, Q, M, L, D
M
l thanh ghi C- -
-Word ra ngoi C-bit qua chn -
-
38
-
-Word v C-
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ X X X 1
2.
Tham Vng
C no COUNTER C
CU BOOL I, Q, M, L, D
S BOOL I, Q, M, L, D
PV WORD I, Q, M, L, D
v constant 0-999
PV WORD I, Q, M, L, D
R BOOL I, Q, M, L, D
CV WORD I, Q, M, L, D
CV_BCD WORD I, Q, M, L, D
Q BOOL I, Q, M, L, D
-
39
S_CU (Up Counter
T
Counter .
T
khng th Q=0
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ X X X 1
2.4.4.
-
40
Tham Vng
C no COUNTER C
CD BOOL I, Q, M, L, D
S BOOL I, Q, M, L, D
counter
PV WORD I, Q, M, L, D
v constant -999
PV WORD I, Q, M, L, D
R BOOL I, Q, M, L, D
CV WORD I, Q, M, L, D
CV_BCD WORD I, Q, M, L, D
BCD
Q BOOL I, Q, M, L, D
S_CU (Up COUNTER
.
T
khng th Q=0
-
41
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ X X X 1
2.4.5. ---( SC ) ounter
---( SC )
Tham Vng
COUNTER C
WORD I, Q, M, L, D or
constant )
--- (SC) ( nter
BR CC1 CC0 OV OS OR STA RLO /FC
0 _ _ _ _ 0 X _ 0
2.4.6. ---( CU ) m ln
---( CU )
Tham Vng
COUNTER C
--- (CU) (Up Counter Coil) trong RLO
COUNTER 1
-
42
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ 0 _ _ 0
2.4.7. ---( CD )
---( CD )
Tham Vng
COUNTER C
--- (CD) (Down Counter Coil) trong RLO
Counter
---( CD ) ---( CD )
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ 0 _ _ 0
2.5. khi d liu
2.5.1. ---(OPN) L I
or
---(OPN)
BLOCK_DB DB, DI
-
43
--- (OPN) (Open a Data Block
Cc ---
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ _ _ _ _
2.6. nhm lnh nhy
2.6.1. ---(JMP)--- n
---( JMP )
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ _ _ _ _
2.6.2. ---(JMP)---
---( JMP )
---
n (nhn --- (JMP).
-
44
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ 0 1 1 0
2.6.3. ---( JMPN ) Jump -If-Not
---( JMPN )
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ 0 1 1 0
2.6.5. LABEL nhn
l .
--- --- (JMPN).
2.7. lnh Time
2.7.1. S_PULSE
R
TV
BCD
BI
Q
S_PULSE
S
T no.
-
45
Tham Vng
T no. TIMER T M
vo CPU
S BOOL I, Q, M, L, D
TV S5TIME I, Q, M, L, D
R BOOL I, Q, M, L, D
BI WORD I, Q, M, L, D
BCD WORD I, Q, M, L, D
BCD
Q BOOL I, Q, M, L, D
-
46
BR CC1 CC0 OV OS OR STA RLO /FC
q _ _ _ _ _ X X X 1
2.7.2 . S_PEXT
Tham Vng
T no. TIMER T
vo CPU
S BOOL I, Q, M, L, D
TV S5TIME I, Q, M, L, D
R BOOL I, Q, M, L, D
BI WORD I, Q, M, L, D
BCD WORD I, Q, M, L, D
BCD
Q BOOL I, Q, M, L, D
R TV
BCD BI
Q
S_PEXT
S
T no.
-
47
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ X X X 1
2.7.3 . S_ODT
R TV
BCD BI
Q
S_ODT
S
T no.
-
48
Tham Vng
T no. TIMER T
vo CPU
S BOOL I, Q, M, L, D
TV S5TIME I, Q, M, L, D
R BOOL I, Q, M, L, D
BI WORD I, Q, M, L, D
BCD WORD I, Q, M, L, D
BCD
Q BOOL I, Q, M, L, D
-
49
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ X X X 1
2.7.4. S_ODTS
Tham Vng
T no. TIMER T
vo CPU
S BOOL I, Q, M, L, D
TV S5TIME I, Q, M, L, D
R BOOL I, Q, M, L, D
BI WORD I, Q, M, L, D
BCD WORD I, Q, M, L, D
BCD
Q BOOL I, Q, M, L, D
R TV
BCD BI Q
S_ODTS
S
T no.
-
50
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ X X X 1
2.7.5. L S_OFFDT
Tham Vng
T no. TIMER T
vo CPU
S BOOL I, Q, M, L, D
TV S5TIME I, Q, M, L, D
R BOOL I, Q, M, L, D
BI WORD I, Q, M, L, D
BCD WORD I, Q, M, L, D
BCD
Q BOOL I, Q, M, L, D
R
TV
BCD
BI
Q
S_OFFDT
S
T no.
-
51
S_OFFDT S v Timer
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ X X X 1
2.7.6 . Xung ---( SP )
---( SP )
-
52
Tham Vng
TIMER T
S5TIME I, Q, M, L, D
--- (SP) (Pulse Timer Coil
value> khi c RLO.
.
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ X X X 1
2.7.7 . Xung ---( SE )
---( SE )
Tham Vng
TIMER T
S5TIME I, Q, M, L, D
---( SE ) (Extended Pulse Timer Coil)
-
53
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ X X X 1
2.7.8 . Xung ---( SD )
---( SD )
Tham Vng
TIMER T
S5TIME I, Q, M, L, D
M t
---( SD ) (On Delay Timer Coil)
Khi
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ X X X 1
-
54
2.7.9. Xung ---( SS )
---( SS ) Tham Vng
TIMER T
S5TIME I, Q, M, L, D
---( SS ) (Retentive On-Delay Timer Coil)
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ X X X 1
2.7.10. Xung ---( SF )
---( SF )
Tham Vng
TIMER T
S5TIME I, Q, M, L, D
-
55
--- (SF) (Off-
Time
n "1" trong khi Time Time
BR CC1 CC0 OV OS OR STA RLO /FC
_ _ _ _ _ X X X 1
2.8. c c php tnh trn word
2.
Tham Vng
EN BOOL I, Q, M, L, D
ENO BOOL I, Q, M, L, D
IN1 WORD I, Q, M, L, D
logic
IN2 WORD I, Q, M, L, D
logic
OUT WORD I, Q, M, L, D
BR CC1 CC0 OV OS OR STA RLO /FC
1 X 0 0 _ X 1 1 1
IN2 IN1 OUT
ENO
WAND_
W
EN
-
56
2. WOR_W
Tham Vng
EN BOOL I, Q, M, L, D
ENO BOOL I, Q, M, L, D
IN1 WORD I, Q, M, L, D
logic
IN2 WORD I, Q, M, L, D
logic
OUT WORD I, Q, M, L, D
WOR_W
BR CC1 CC0 OV OS OR STA RLO /FC
1 X 0 0 _ X 1 1 1
2.8.3. WAND_DW
Tham Vng
EN BOOL I, Q, M, L, D
ENO BOOL I, Q, M, L, D
IN1 WORD I, Q, M, L, D
logic
IN2 WORD I, Q, M, L, D g
logic
OUT WORD I, Q, M, L, D
IN2 IN1 OUT
ENO
WOR_W
EN
IN2 IN1 OUT
ENO
WAND_DW
EN
-
57
WAND_DW
vo Double Word.
BR CC1 CC0 OV OS OR STA RLO /FC
1 X 0 0 _ X 1 1 1
2.8.4. WOR_DW
Tham Vng
EN BOOL I, Q, M, L, D
ENO BOOL I, Q, M, L, D
IN1 WORD I, Q, M, L, D
IN2 WORD I, Q, M, L, D
OUT WORD I, Q, M, L, D
WOR_DW :
vo Double Word.
BR CC1 CC0 OV OS OR STA RLO /FC
1 X 0 0 _ X 1 1 1
2.8.5. WXOR_W
IN2 IN1 OUT
ENO
WOR_DW
EN
IN
2
IN1 OUT ENO
WXOR_W
EN
-
58
I
2
IN1 OUT
ENO
WOR_DW
EN
Tham Vng
EN BOOL I, Q, M, L, D
ENO BOOL I, Q, M, L, D
IN1 WORD I, Q, M, L, D
logic
IN2 WORD I, Q, M, L, D
logic
OUT WORD I, Q, M, L, D
BR CC1 CC0 OV OS OR STA RLO /FC
1 X 0 0 _ X 1 1 1
2.8.6. WXOR_DW
Tham Vng
EN BOOL I, Q, M, L, D
ENO BOOL I, Q, M, L, D
IN1 WORD I, Q, M, L, D
IN2 WORD I, Q, M, L, D
OUT WORD I, Q, M, L, D
-
59
WXOR_DW
BR CC1 CC0 OV OS OR STA RLO /FC
1 X 0 0 _ X 1 1 1
-
60
Ch-ng 3 . b bin i PID trn S7 -300
3.1. nhng module pid mm c trong step7
-
h
-
61
- -tch
Step7
2)
PULSEGEN).
-
62
sau:
CRP-IN
%
PV-NORM
DEADBAND
INT
DIF
SP-INT
PV_INT
PV_PER
PVPER_ONGAIN
ER
PV
P-SEL
I-SEL
PV-FAC
PV-OFF
%
CRP_OUT
D-SEL
LMN-P
LMN-I
LMN-D
MAIL_ONMAN
LMNLIMIT LMN_NORM
LMN_HLM
LMN_LLM
LMN_FAC
LMN_OFF
LMN
LMN_PER
DISV
0
1
0
1
1
1
1
00.0
0.0
0.0
TD,TM,LAG
QLMN-HLM
QLMN-LLM
TI, I-ITL-ON
I-ITLVAL
0
0
Hnh 3.1:
-
PV- -IN, cc
PVPER-ON, P-SEL, I-SEL, D-SEL,MAN-
-
63
-
-PER
tn CRP-
-
-
-
-IN = PV-PER 27648
100
-
- c:
- -IN) PV-FAC-OFF
-NORM l PV-FAC v
PV- - - -
-W=0.
INT
DIF
I-SEL
D-SEL
1
1
00.0
0.0
0.0
TD,TM,LAG
TI, I-ITL-ON
I-ITLVAL
0
0
P-SEL
GAIN
Hnh 3.2:
-
64
-SEL, I-SEL hay D-
NT
-LNM-P-
-
* LMN -FAC + LMN-OFF
- -
-
-PER = LMN * 100
27648
-
65
3.2.2
Tn
COM-
RST
BOOL FALSE COMPLETE RESTART
MAN-
ON
BOOL TRUE MANUAL VALUE ON
ng tay
PVPE
R-ON
BOOL FALSE PROCESS VARIABLE
PERIPHERAL ON
-
P-SEL BOOL TRUE PROPORTIONAL ACTION ON
-
66
I-SEL BOOL TRUE INTERGRAL ACTION ON
Ho
INT-
HOLD
BOOL FALSE INTERGRAL ACTION HOLD
I-ITL-
ON
BOOL FALSE INITIALIZATION OFTHE
INTERGRAL ACTION
-ITL-
D-
SEL
BOOL FALSE DERIVATE ACTION ON
-
67
CYCLE TIME T#1s SAMPLING TIME
SP-
INT
REAL -
0.0 INTERNAL SETPOINT
PV-IN REAL -
0.0 PROCESS VARIBLE IN
PV-
PER
WORD W#16#00
00
PROCESS VARIABLE
PERIPHERAL
MAN REAL -
0.0 MANUAL VALUE
GAIN REAL 2.0 PROPOTIONAL GAIN
TI TIME T#20s RESET TIME
phn.
-
68
TD TIME T#10s DERIVATE TIME
TM-
LAG
TIME T#2s TIME LAG OF DERIVATE ACTION
DEA
B-W
REAL
0.0 DEAD BAND WIDTH
LMN-
HLM
REAL LMN-LLM
100.0 MANIPULATED VALUE HIGH
LIMIT
LMN-
LLN
REAL -100%...
LMN-LLM
0.0 MANIPULATED VALUE LOW
LIMIT
PV-
FAC
REAL 1.0 PROCESS VARIALE FACTOR
-
69
LMN-
FAC
REAL 1.0 MANIPULATED VALUE
FACTOR
LMN-
OFF
REAL 0.0 MANIPULATED VALUE OFFSET
I-
ITLV
AL
REAL -
0.0 INITIALIZATION VALUE OF
THE INTERGRAL ACTION
DISV REAL -
0.0 DISTURBANCE VARIABLE
PV-
OF
REAL 1.0 PROCESS VARIALE OFFSET
-
70
LMN REAL 0.0 MANIPULATED VALUE
LMN-PER WORD W#16#
0000
MANIPULATED VALUE
PERIPHERAL
QLMN-
HLM
BOOL FALSE HIGH LIMIT OF MANIPULATED
VALUE RACHED
QLMN-
LLM
BOOL FALSE LOW LIMIT OF MANIPULATED
VALUE RACHED
LMN-P REAL 0.0 PROPOTIONAL COMPONENT