ds90ub933-q1 适用于 1mp/60fps 摄像头 10/12 位、100mhz 的 …

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DS90UB933-Q1

Serializer

FPD-Link III

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DS90UB934-Q1

or

DS90UB964-Q1

Bidirectional

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本文档旨在为方便起见，提供有关 TI 产品中文版本的信息，以确认产品的概要。有关适用的官方英文版本的最新信息，请访问 www.ti.com，其内容始终优先。 TI 不保证翻译的准确性和有效性。在实际设计之前，请务必参考最新版本的英文版本。

English Data Sheet: SNLS546

DS90UB933-Q1ZHCSFV6C –AUGUST 2016–REVISED NOVEMBER 2019

DS90UB933-Q1 适适用用于于 1MP/60fps 摄摄像像头头 10/12 位位、、100MHz 的的 FPD-Link III 串串行行器器

1

1 特特性性

1• 符合面向汽车应用的 AEC-Q100 标准具有以下结果：

– 器件温度 2 级：-40 至 +105 环境运行温度范围

• 支持 37.5MHz 至 100MHz 输入像素时钟

• 稳健的同轴电缆供电 (PoC) 运行

• 可编程数据有效载荷：

– 10 位有效载荷，高达 100MHz– 12 位有效载荷，高达 100MHz

• 连续低延迟双向控制接口通道，带有 I2C 接口，支持 400kHz 传输速率

• 具有直流均衡编码的嵌入式时钟，支持交流耦合互连

• 能够驱动长达 15m 的同轴或屏蔽双绞线 (STP) 电缆

• 4 个专用通用输入/输出 (GPIO)• 串行器上提供 1.8V、2.8V 或 3.3V 兼容并行输入

• 1.8V 单电源

• 符合 ISO 10605 和 IEC 61000-4-2 ESD 标准

2 应应用用

• 汽车

– 环视系统 (SVS)– 前置摄像头 (FC)– 后视摄像头 (RVC)– 传感器融合

– 驾驶员监视摄像头 (DMS)– 远程卫星雷达、ToF 和激光雷达传感器

• 安全和监控

• 机器视觉参考设计

3 说说明明

DS90UB933-Q1 器件提供一个具有高速正向通道和双

向控制通道的 FPD-Link III 接口，用于实现单一同轴电

缆或差分对上的数据传输。DS90UB933-Q1 器件的高

速正向通道和双向控制通道数据路径上均包含差分信

令。串行器/解串器对主要用于电子控制单元 (ECU) 中成像器与视频处理器的连接。该器件非常适用于驱动需

要高达 12 位像素深度、2 个同步信号以及双向控制通

道总线的视频数据。

凭借德州仪器 (TI) 的嵌入式时钟技术，可在单一差分

对上进行透明的全双工通信，从而运载不对称的双向控

制通道信息。这个单个串行数据流通过消除并行数据与

时钟路径间的偏差，简化了印刷电路板 (PCB) 走线和

电缆上的宽数据总线传输。这样，通过限制数据路径的

宽度，大大节省了系统成本，相应地减少了 PCB 层

数、电缆宽度以及连接器尺寸和引脚数量。内部 DC均衡编码/解码用于支持 AC 耦合互连。

器器件件信信息息(1)

器器件件型型号号封封装装封封装装尺尺寸寸（（标标称称值值））

DS90UB933-Q1 WQFN (32) 5.00mm × 5.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

简简化化原原理理图图

http://www-s.ti.com/sc/techlit/SNLS546.pdf

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2

DS90UB933-Q1ZHCSFV6C –AUGUST 2016–REVISED NOVEMBER 2019 www.ti.com.cn

版权 © 2016–2019, Texas Instruments Incorporated

目目录录

1 特特性性.......................................................................... 12 应应用用.......................................................................... 13 说说明明.......................................................................... 14 修修订订历历史史记记录录 ........................................................... 25 Pin Configuration and Functions ......................... 36 Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 56.2 ESD Ratings.............................................................. 56.3 Recommended Operating Conditions....................... 56.4 Thermal Information .................................................. 66.5 Electrical Characteristics........................................... 66.6 Recommended Serializer Timing For PCLK............. 96.7 AC Timing Specifications (SCL, SDA) - I2C-

Compatible ............................................................... 106.8 Bidirectional Control Bus DC Timing Specifications

(SCL, SDA) - I2C-Compatible ................................. 106.9 Serializer Switching Characteristics........................ 116.10 Timing Diagrams................................................... 126.11 Typical Characteristics .......................................... 14

7 Detailed Description ............................................ 157.1 Overview ................................................................. 15

7.2 Functional Block Diagram ...................................... 157.3 Feature Description................................................. 167.4 Device Functional Modes........................................ 197.5 Programming .......................................................... 247.6 Register Maps ......................................................... 28

8 Application and Implementation ........................ 358.1 Application Information............................................ 358.2 Typical Applications ................................................ 37

9 Power Supply Recommendations ...................... 4010 Layout................................................................... 41

10.1 Layout Guidelines ................................................. 4110.2 Layout Example .................................................... 42

11 器器件件和和文文档档支支持持 ..................................................... 4411.1 文档支持 ................................................................ 4411.2 接收文档更新通知 ................................................. 4411.3 社区资源 ................................................................ 4411.4 商标 ....................................................................... 4411.5 静电放电警告......................................................... 4411.6 Glossary ................................................................ 44

12 机机械械、、封封装装和和可可订订购购信信息息....................................... 44

4 修修订订历历史史记记录录

Changes from Revision B (September 2018) to Revision C Page

• Added register 0x27[5] to register map ............................................................................................................................... 33

Changes from Revision A (December 2016) to Revision B Page

• Added recommendation to ensure GPO2 is low when PDB goes high ................................................................................. 4• Added external clock input frequency range ......................................................................................................................... 6• Added strap pin input current specification for MODE and IDX pins .................................................................................... 6• Updated TJIT1 PCLK input jitter in the external oscillator mode.............................................................................................. 9• Added that 0.45UI TJIT2 maximum is when used with DS90UB934-Q1 and added new foot note ....................................... 9• Added clarification on MODE pin description in PCLK from imager mode ......................................................................... 20• Updated the MODE setting values to ratio from voltage ...................................................................................................... 21• Updated IDX setting values to ratio from voltage................................................................................................................. 26• Added register "TYPE" column per legend ......................................................................................................................... 28• Added type and default value to the reserved register bits that were missing this information ........................................... 28• Added that register 0x00[7:1] does not auto update IDX strapped address ....................................................................... 28• Added description for 0x05 bits 1 and 0 (TX_MODE_12b and TX_MODE_10b) ................................................................ 30• Added reference to Power over Coax Application report ..................................................................................................... 35• Clarified description on PDB pin usage during power up .................................................................................................... 35• Added paragraph to explain setting registers if GPO2 state is not determined when PDB goes high ............................... 35• Added GPO2 to suggested power-up sequencing diagram ................................................................................................ 35• Added timing constraint for PDB to GPO2 delay ................................................................................................................ 36• Revised coax connection diagram to include pulldown resistor for GPO2 ......................................................................... 37• Revised STP connection diagram to include pulldown resistor for GPO2 .......................................................................... 39


http://www.ti.com.cn

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31

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26

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DS90UB933-Q1

Serializer

VDDIO

DIN[8]

DIN[9]

DIN[10]

DIN[11]

DIN[7]

DIN[6]

DIN

[5]

DIN

[4]

DIN

[3]

DIN

[2]

DIN

[1]

DIN

[0]

VDDCML

VDDT

VDDPLL

PDB

DOUT-

DOUT+

HS

YN

C

VS

YN

C

PC

LK

SC

L

SD

A

ID[x

]

RE

S

MO

DE

GP

O[2

]/

CL

KO

UT

GPO[1]

GPO[0]

VDDD

GP

O[3

]/

CL

KIN

DAP = GND

3

DS90UB933-Q1www.ti.com.cn ZHCSFV6C –AUGUST 2016–REVISED NOVEMBER 2019

Copyright © 2016–2019, Texas Instruments Incorporated

Changes from Original (August 2016) to Revision A Page

• 已更改 “产品预览”至“量产数据”版本。 .................................................................................................................................... 1

5 Pin Configuration and Functions

RTV Package32-Pin WQFN

Top View

Pin FunctionsPIN

I/O DESCRIPTIONNAME NO.LVCMOS PARALLEL INTERFACE

DIN[0:11]19,20,21,22,23,24,26,27,29,30,31,32

Inputs,LVCMOS

w/ pulldown

Parallel data Inputs. For 10-bit MODE, parallel inputs DIN[0:9] are active. DIN[10:11] areinactive and should not be used. Any unused inputs (including DIN[10:11]) must be NoConnect. For 12-bit MODE, parallel inputs DIN[0:11] are active. Any unused inputs must beNo Connect.

HSYNC 1Input,

LVCMOSw/ pulldown

Horizontal SYNC input. Note: HS transition restrictions: 1. 12-bit mode: No HS restrictions(raw) 2. 10-bit mode: HS restricted to no more than one transition per 10 PCLK cycles.Leave open if unused.

VSYNC 2Input,

LVCMOSw/ pulldown

Vertical SYNC input. Note: VS transition restrictions: 1. 12-bit mode: No VS restrictions (raw)2. 10-bit mode: VS restricted to no more than one transition per 10 PCLK cycles. Leave openif unused.

PCLK 3Input,

LVCMOSw/ pulldown

Pixel clock input pin. Strobe edge set by TRFB control register 0x03[0].



4



Pin Functions (continued)PIN

I/O DESCRIPTIONNAME NO.

(1) See Power-Up Requirements and PDB Pin.

GENERAL PURPOSE OUTPUT (GPO)

GPO[1:0] 16,15 Output,LVCMOS

General-purpose output pins can be configured as outputs, used to control and respond tovarious commands. GPO[1:0] can be configured to be the outputs for input signals comingfrom GPIO[1:0] pins on the deserializer or can be configured to be outputs of the localregister on the serializer. Leave open if unused.

GPO[2]/CLKOUT 17 Output,

LVCMOS

GPO[2] pin can be configured to be the output for input signal coming from the GPIO[2] pinon the deserializer or can be configured to be the output of the local register on theSerializer. It can also be configured to be the output clock pin when the DS90UB933-Q1device is used in the external oscillator mode. See Device Functional Modes for a detaileddescription of External Oscillator mode. It is recommended to pull GPO2 to GND with aminimum 40-kΩ resistor to ensure GPO2=LOW when PDB transitions from LOW to HIGH.Leave open if unused.

GPO[3]/CLKIN 18 Input/Output,

LVCMOS

GPO[3] can be configured to be the output for input signals coming from the GPIO[3] pin onthe deserializer or can be configured to be the output of the local register setting on theserializer. It can also be configured to be the input clock pin when the DS90UB933-Q1serializer is working with an external oscillator. See Device Functional Modes for a detaileddescription of external oscillator mode. Leave open if unused.

BIDIRECTIONAL CONTROL BUS - I2C-COMPATIBLE

SCL 4 Input/Output,Open Drain

Clock line for the bidirectional control bus communicationSCL requires an external pullup resistor to V(VDDIO).

SDA 5 Input/Output,Open Drain

Data line for the bidirectional control bus communicationSDA requires an external pullup resistor to V(VDDIO).

MODE 8 Input, analog

Device mode selectResistor (Rmode) to ground and 10-kΩ pullup to 1.8 V rail. MODE pin on the serializer canbe used to select whether the system is running off the PCLK from the imager or an externaloscillator. See details in Table 2.

IDX 6 Input, analogDevice ID Address SelectThe IDX pin on the serializer is used to assign the I2C device address. Resistor (RID) toGround and 10-kΩ pullup to 1.8 V rail. See Table 6.

CONTROL AND CONFIGURATION

PDB 9Input,

LVCMOSw/ pulldown

Power-down mode input pinPDB = H, Serializer is enabled and is ON.PDB = L, Serializer is in power down mode. When the serializer is in power down, the PLL isshut down, and IDD is minimized. Programmed control register data is NOT retained andreset to default values.

RES 7Input,

LVCMOSw/ pulldown

ReservedThis pin MUST be tied LOW.

FPD–Link III INTERFACE

DOUT+ 13 Input/Output,CML

Non-inverting differential output, bidirectional control channel input. The interconnect must beAC coupled with a 0.1-µF capacitor.

DOUT- 12 Input/Output,CML

Inverting differential output, bidirectional control channel input. The interconnect must be ACcoupled with a 0.1-µF capacitor. For applications using single-ended coaxial interconnect,place a 0.047-µF AC-coupling capacitor in series with a 50-Ω resistor before terminating toGND.

POWER AND GROUND (1)

VDDPLL 10 Power,Analog PLL power, 1.8 V ±5%.

VDDT 11 Power,Analog Tx analog power, 1.8 V ±5%.

VDDCML 14 Power,Analog CML and bidirectional channel driver power, 1.8 V ±5%.

VDDD 28 Power,Digital Digital Power, 1.8 V ±5%.

VDDIO 25 Power,Digital

Power for I/O stage. The single-ended inputs and SDA, SCL are powered from V(VDDIO).VDDIO can be connected to a 1.8 V ±5% or 2.8 V ±10% or 3.3 V ±10%.



5



Pin Functions (continued)PIN

I/O DESCRIPTIONNAME NO.

VSS DAP Ground, DAP DAP must be grounded. DAP is the large metal contact at the bottom side, located at thecenter of the WQFN package. Connected to the ground plane (GND) with at least 9 vias.

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratingsonly, which do not imply functional operation of the device at these or any other conditions beyond those indicated under RecommendedOperating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6 Specifications

6.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted) (1)

MIN MAX UNITSupply voltage – V(VDD_n) (V(VDDPLL), V(VDDT), V(VDDCML), V(VDDD)) –0.3 2.5 VSupply voltage – V(VDDIO) −0.3 4 VLVCMOS input voltage −0.3 V(VDDIO) + 0.3 VFPD-Link III I/O voltage – V(VDD_n) –0.3 V(VDD_n) + 0.3 VJunction temperature 150 °CStorage temperature, Tstg −65 150 °C

(1) AEC Q100-002 indicates HBM stressing is done in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.2 ESD RatingsVALUE UNIT

V(ESD)Electrostaticdischarge

Human body model (HBM), per AEC Q100-002 (1)

HBM ESD Classification Level 3B ±8000

V

Charged device model (CDM), per AECQ100-011CDM ESD Classification Level C6

Corner pins (1, 8, 9, 16, 17, 24, 25, 32)±1000

Other pins

(IEC 61000-4-2)D R = 330 Ω, Cs = 150 pF

Air Discharge(DOUT+, DOUT-, RIN+, RIN-) ±25000

Contact Discharge(DOUT+, DOUT-, RIN+, RIN-) ±7000

(ISO10605)RD = 330 Ω, Cs = 150/330 pFRD = 2 KΩ, Cs = 150/330 pF

Air Discharge(DOUT+, DOUT-, RIN+, RIN-) ±15000

Contact Discharge(DOUT+, DOUT-, RIN+, RIN-) ±8000

(1) Supply noise testing was done with minimum capacitors (as shown on Figure 36, Figure 32 on the PCB. A sinusoidal signal is ACcoupled to the V(VDD_n) (1.8 V) supply with amplitude = 25 mVp-p measured at the device V(VDD_n) pins. Bit error rate testing of input tothe serializer and output of the deserializer with 10-meter cable shows no error when the noise frequency on the serializer is less than 1MHz. The deserializer, on the other hand, shows no error when the noise frequency is less than 750 kHz.

6.3 Recommended Operating Conditionsover operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNITSupply voltage, V(VDD_n) 1.71 1.8 1.89 V

LVCMOS supply voltageV(VDDIO)= 1.8 V 1.71 1.8 1.89

VV(VDDIO)= 3.3 V 3 3.3 3.6V(VDDIO)= 2.8 V 2.52 2.8 3.08

Supply noise (1)

V(VDD_n) = 1.8 V 25mVp-pV(VDDIO) = 1.8 V 25

V(VDDIO) = 3.3 V 50



6



Recommended Operating Conditions (continued)over operating free-air temperature range (unless otherwise noted)

MIN NOM MAX UNIT

Power-Over-Coax SupplyNoise

ƒ = 30 Hz - 1 KHz, trise > 100 µsMeasured differentially between DOUT+ and DOUT–(coax mode only)

35 mVp-p

ƒ = 1 KHz - 50 MHzMeasured differentially between DOUT+ and DOUT-(coax mode only)

35 mVp-p

Operating free air temperature, TA –40 25 105 °CPCLK clock frequency - 10-bit mode 50 100 MHzPCLK clock frequency - 12-bit mode 37.5 100 MHzExternal clock input frequency to GPO3 - 10-bit mode 25 50 MHzExternal clock input frequency to GPO3 - 12-bit mode 25 66.67 MHz

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport (SPRA953).

6.4 Thermal Information

THERMAL METRIC (1)DS90UB933-Q1

UNITRTV (WQFN)32 PINS

RθJA Junction-to-ambient thermal resistance 34.9 °C/WRθJC(top) Junction-to-case (top) thermal resistance 8.8 °C/WRθJC(bot) Junction-to-case (bottom) thermal resistance 3.4 °C/WRθJB Junction-to-board thermal resistance 23.4 °C/WψJT Junction-to-top characterization parameter 0.3 °C/WψJB Junction-to-board characterization parameter 8.8 °C/W

(1) The Electrical Characteristics tables list verified specifications under the listed Recommended Operating Conditions except as otherwisemodified or specified by the Electrical Characteristics Conditions and/or Notes. Typical specifications are estimations only and are notverified.

(2) Current into device pins is defined as positive. Current out of a device pin is defined as negative. Voltages are referenced to groundexcept VOD and ΔVOD which are differential voltages.

(3) Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at the Recommended Operating Conditions atthe time of product characterization and are not verified.

6.5 Electrical CharacteristicsOver recommended operating supply and temperature ranges unless otherwise specified. (1) (2) (3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNITLVCMOS DC SPECIFICATIONS 3.3 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)VIH High level input voltage VIN = 3 V to 3.6 V 2 VIN VVIL Low level input voltage VIN = 3 V to 3.6 V GND 0.8 VIIN Input current VIN = 0 V or 3.6 V, VIN = 3 V to 3.6 V –20 ±1 20 µAVOH High level output voltage V(VDDIO) = 3 V to 3.6 V, IOH = −4 mA 2.4 V(VDDIO) VVOL Low level output voltage V(VDDIO) = 3 V to 3.6 V, IOL = 4 mA GND 0.4 V

IOSOutput short-circuitcurrent VOUT = 0 V Serializer

GPO outputs –15 mA

IOZ Tri-state output current PDB = 0 V,VOUT = 0 V or V(VDDIO)

SerializerGPO outputs –20 20 µA

CGPO Pin capacitance GPO [3:0] 1.5 pFLVCMOS DC SPECIFICATIONS 1.8 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)VIH High level input voltage VIN = 1.71 V to 1.89 V 0.65 VIN VIN VVIL Low level input voltage VIN = 1.71 V to 1.89 V GND 0.35 VIN

IIN Input current VIN = 0 V or 1.89 V, VIN = 1.71 V to 1.89 V –20 ±1 20 µA



http://www.ti.com/cn/lit/pdf/spra953

7



Electrical Characteristics (continued)Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

(4) The back channel frequency (MHz) listed is the frequency of the internal clock used to generate the encoded back channel data stream.The data rate (Mbps) of the encoded back channel stream is the back channel frequency divided by 2.

VOH High level output voltage V(VDDIO) = 1.71 V to 1.89 V, IOH = −4 mA V(VDDIO) –0.45 V(VDDIO) V

VOL Low level output voltage V(VDDIO) = 1.71 V to 1.89 V IOL = 4 mA GND 0.45 V





CGPO Pin capacitance GPO [3:0] 1.5 pFIIN_STRAP Strap pin input current VIN = 0 V to VDD_n MODE, IDX –1 1 µALVCMOS DC SPECIFICATIONS 2.8 V I/O (SER INPUTS, GPIO, CONTROL INPUTS AND OUTPUTS)VIH High level input voltage VIN = 2.52 V to 3.08 V 0.7 VIN VIN VVIL Low level input voltage VIN = 2.52 V to 3.08 V GND 0.3 VIN

IIN Input current VIN = 0 V or 3.08 V, VIN = 2.52 V to 3.08 V –20 ±1 20 µA

VOH High level output voltage V(VDDIO) = 2.52 V to 3.08 V, IOH = −4 mA V(VDDIO) -0.4 V(VDDIO) V

VOL Low level output voltage V(VDDIO) =2.52 V to 3.08V IOL = 4 mA GND 0.4 V





CGPO Pin capacitance GPO [3:0] 1.5 pFCML DRIVER DC SPECIFICATIONS (DOUT+, DOUT–)

VODDifferential outputvoltage RL = 100 Ω (Figure 6) 640 824

mVVOUT

Single-ended outputvoltage RL = 50 Ω (Figure 6) 320 412

ΔVODDifferential outputvoltage unbalance RL = 100 Ω 1 50 mV

VOS Output offset voltage RL = 100 Ω (Figure 6) V(VDD_n) –(VOD /2) V

ΔVOS Offset voltage unbalance RL = 100 Ω 1 50 mV

IOSOutput short-circuitcurrent DOUT+ = 0 V or DOUT– = 0 V –26 mA

RT

Differential internaltermination resistance Differential across DOUT+ and DOUT– 80 100 120

ΩSingle-endedtermination resistance DOUT+ or DOUT– 40 50 60

VID-BCBack channel differentialinput voltage

Back Channel Frequency = 5.5 MHz (4)260 mV

VIN-BCBack channel single-ended input voltage 130 mV

SERIALIZER SUPPLY CURRENT

IDDT

Serializer (Tx)V(VDD_n) supply current(includes load current)

RL = 100 ΩWORST CASE pattern(Figure 2)

V(VDD_n) = 1.89 VV(VDDIO) = 3.6 Vƒ = 100 MHz, 12-bitmodeDefault registers

76 95 mA

V(VDD_n) = 1.89 VV(VDDIO) = 3.6 Vƒ = 75 MHz, 12-bitmodeDefault registers

61 80 mA



8



Electrical Characteristics (continued)Over recommended operating supply and temperature ranges unless otherwise specified.(1)(2)(3)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

IDDT

Serializer (Tx)V(VDD_n) supply current(includes load current)

RL = 100 ΩRANDOM PRBS-7pattern

V(VDD_n) = 1.89 VV(VDDIO) = 3.6 Vƒ = 100 MHz, 12-bitmodeDefault Registers

80

mAV(VDD_n) = 1.89 VV(VDDIO) = 3.6 Vƒ = 75 MHz, 12-bitmodeDefault Registers

64

I(VDDIO)T

Serializer (Tx)V(VDDIO) supply current(includes load current)

RL = 100 ΩWORST CASE pattern(Figure 2)

V(VDDIO) = 1.89 Vƒ = 75 MHz, 12-bitmodeDefault Registers

1.5 3

mAV(VDDIO) = 3.6 Vƒ = 75 MHz, 12-bitmodeDefault registers

5 8

IDDTZSerializer (Tx) supplycurrent power down

PDB = 0 V; All otherLVCMOS inputs = 0 V

V(VDDIO)=1.89 VDefault registers 300 1000 µA

V(VDDIO) = 3.6 VDefault registers 300 1000 µA

I(VDDIO)TZ

Serializer (Tx) V(VDDIO)supply current powerdown

PDB = 0 V; All otherLVCMOS inputs = 0 V





9



(1) Recommended input timing requirements are input specifications and not tested in production.(2) T is the period of the PCLK.(3) Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at Recommended Operating Conditions at the

time of product characterization and are not verified.(4) ƒPCLK denotes input PCLK frequency to the device.(5) 0.45UI maximum when used with DS90UB934-Q1 deserializer. When used with DS90UB914A-Q1 deserializer, the maximum is 0.3UI.(6) ƒOSC denotes input external oscillator frequency to the device (GPO3/CLKIN).

6.6 Recommended Serializer Timing For PCLKOver recommended operating supply and temperature ranges unless otherwise specified. (1) (2)

PARAMETER TEST CONDITIONS PIN / FREQ MIN NOM MAX UNIT

tTCP Transmit clock period

10-bit mode50 MHz – 100 MHz 7.52 T 20 ns

12-bit mode37.5 MHz - 100 MHz 10 T 26.67 ns

tTCIHTransmit clockinput high time 0.4T 0.5T 0.6T

tTCILTransmit clockinput low time 0.4T 0.5T 0.6T

tCLKTPCLK input transition time(Figure 7)

10-bit mode50 MHz – 100 MHz 0.05T 0.25T 0.3T

12-bit mode37.5 MHz – 100 MHz 0.05T 0.25T 0.3T

tJIT0PCLK input jitter (3)

(PCLK from imager mode)

LPF = ƒ/20, CDR PLL Loop BW= ƒ/15, BER = 1E-10

ƒPCLK =37.5 – 100MHz (4)

0.45 UI

tJIT1PCLK input jitter (3)

(External oscillator mode)LPF = ƒ/20, CDR PLL Loop BW= ƒ/15, BER = 1E-10

ƒPCLK =37.5 – 100MHz (4)

1T

tJIT2 External oscillator jitter (3) (5)LPF = ƒ/20, CDR PLL Loop BW= ƒ/15, BER = 1E-10, paired withDS90UB934-Q1 deserializer

ƒOSC = 25 –66.67 MHz (6) 0.45 UI

ΔOSCExternal OscillatorFrequency Stability

ƒOSC = 25 –66.67 MHz (6) ±50 ppm

tDCCLKOUT duty cycle(external oscillator mode)

ƒOSC = 25 –66.67 MHz (6) 45% 50% 55%



10



6.7 AC Timing Specifications (SCL, SDA) - I2C-CompatibleOver recommended supply and temperature ranges unless otherwise specified. (Figure 1)

PARAMETER TEST CONDITIONS MIN NOM MAX UNITRECOMMENDED INPUT TIMING REQUIREMENTS

ƒSCL SCL Clock FrequencyStandard mode 100 kHzFast mode 400 kHz

tLOW SCL Low PeriodStandard mode 4.7 µsFast mode 1.3 µs

tHIGH SCL high periodStandard mode 4.0 µsFast mode 0.6 µs

tHD:STAHold time for a start or a repeated startcondition

Standard mode 4.0 µsFast mode 0.6 µs

tSU:STASetup time for a start or a repeated startcondition

Standard mode 4.7 µsFast mode 0.6 µs

tHD:DAT Data hold timeStandard mode 0 3.45 µsFast mode 0 900 ns

tSU:DAT Data setup timeStandard mode 250 nsFast mode 100 ns

tSU:STO Setup time for stop conditionStandard mode 4.0 µsFast mode 0.6 µs

tBUF Bus free time between stop and startStandard mode 4.7 µsFast mode 1.3 µs

tr SCL and SDA rise timeStandard mode 1000 nsFast mode 300 ns

tf SCL and SDA fall timeStandard mode 300 nsFast mode 300 ns

(1) Specification is verified by design.(2) FPD-Link device was designed primarily for point-to-point operation and a small number of attached slave devices. As such the

minimum IOL pullup current is targeted to lower value than the minimum IOL in the I2C specification.

6.8 Bidirectional Control Bus DC Timing Specifications (SCL, SDA) - I2C-CompatibleOver recommended supply and temperature ranges unless otherwise specified (1)

PARAMETER TEST CONDITIONS MIN NOM MAX UNITRECOMMENDED INPUT TIMING REQUIREMENTSVIH Input high level SDA and SCL 0.7 × V(VDDIO) V(VDDIO) V

VIL Input low level SDA and SCL GND 0.3 ×V(VDDIO)

V

VHY Input hysteresis > 50 mV

VOL Output low level (2) SDA, V(VDDIO) = 1.8 V, IOL= 0.9 mA 0 0.36V

SDA, V(VDDIO) = 3.3 V, IOL= 1.6 mA 0 0.4IIN Input current SDA or SCL, VIN= V(VDDIO) OR GND −10 10 µAtR SDA rise time-READ SDA, RPU = 10 kΩ, Cb ≤ 400 pF

(Figure 1)430 ns

tF SDA fall time-READ 20 nsCIN SDA or SCL <5 pF



11



(1) tPLD is the time required by the serializer to obtain lock when exiting power-down state with an active PCLK.(2) Specification is verified by design.(3) Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at Recommended Operating Conditions at the

time of product characterization and are not verified.(4) Specification is verified by characterization and is not tested in production.(5) UI – Unit Interval is equivalent to one ideal serialized data bit width. The UI scales with PCLK frequency.

10-bit mode: 1 UI = 1 / ( PCLK_Freq. /2 × 28 )12-bit mode: 1 UI = 1 / ( PCLK_Freq. × 2/3 × 28 )

(6) Typical values represent most likely parametric norms at 1.8 V or 3.3 V, TA = 25°C, and at Recommended Operating Conditions at thetime of product characterization and are not verified.

(7) Serializer output peak-to-peak total jitter includes deterministic jitter, random jitter, and jitter transfer from serializer input.

6.9 Serializer Switching CharacteristicsOver recommended operating supply and temperature ranges unless otherwise specified.

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT

tLHTCML low-to-hightransition time RL = 100 Ω (Figure 3) 150 330 ps

tHLTCML high-to-lowtransition time RL = 100 Ω (Figure 3) 150 330 ps

tDISData inputSetup to PCLK

Serializer data inputs (Figure 8)2 ns

tDIHData inputHold from PCLK 2 ns

tPLDSerializer PLL locktime (1) (2) RL = 100 Ω (Figure 9) 1 2 ms

tSD Serializer delay (2)

RT = 100 Ω, 10–bit modeRegister 0x03h b[0] (TRFB = 1) (Figure 10) 32.5T 38T 44T

RT = 100 Ω, 12–bit modeRegister 0x03h b[0] (TRFB = 1) (Figure 10) 11.75T 13T 15T

tJIND

Serializer outputdeterministic jitter(3) (4) (5)

PRBS-7 test pattern, CDR PLL LoopBW = ƒ/15, BER = 1E-10 DOUT± 0.17 UI

tJINRSerializer outputrandom jitter (3) (4) (5)


tJINT

Peak-to-peakserializer output totaljitter (6) (5) (7)


λSTXBW

Serializer jittertransfer function–3 dB bandwidth

10–bit modePCLK = 100 MHz, Default registers 2.2

MHz12–bit modePCLK = 100 MHz, Default registers 2.2

δSTX

Serializer jitterTransfer Function(peaking)

10–bit modePCLK = 100 MHz, Default registers 1.06

dB12–bit modePCLK = 100 MHz, Default registers 1.09

δSTXf

Serializer jittertransfer function(peaking frequency)

10–bit modePCLK = 100 MHz, Default registers 400

kHz12–bit modePCLK = 100 MHz, Default registers 500



Copyright © 2016, Texas Instruments Incorporated

PA

RA

LL

EL

-TO

-SE

RIA

L

DOUT+

DOUT-

10/12,

HS,VS

DIN RL

PCLK


ZDiff = 100 : 100 :

DOUT+

DOUT-

100 nF

100 nF

SCOPE

BW 8 4.0 GHz

50 :

50 :

80%

20%

80%

20%

Vdiff = 0 V

tLHT tHLT

Vdiff

Vdiff = (DOUT+) - (DOUT-)

PCLK

(RFB = H)

DIN/ROUT

Signal PatternDevice Pin Name

T

SCL

SDA

tHD;STA

tLOW

tr

tHD;DAT

tHIGH

tf

tSU;DAT

tSU;STA tSU;STO

tf

START REPEATED

START

STOP

tHD;STA

START

tr

tBUF

12



6.10 Timing Diagrams

Figure 1. Bidirectional Control Bus Timing

Figure 2. “Worst Case” Test Pattern for PowerConsumption

Figure 3. Serializer CML Output Load andTransition Times

Figure 4. Measurement Setup Serializer CML Output Load and Transition Times

Figure 5. Serializer VOD Setup



||

SYMBOL N

||

SYMBOL N-1

||

SYMBOL N-2

||

SYMBOL N-3SYMBOL N-4

||

DOUT+-

|PCLK

tSD

DIN SYMBOL N+1SYMBOL N SYMBOL N+2 SYMBOL N+3

||

|||

||

||

||

VDDIO/2

0V

VDDIO/2

PCLK

DOUT± Output Active

tPLD

PDB

TRI-STATE TRI-STATE

SetupVDDIO/2 Hold

tDIHtDIS

PCLK

DINn

tTCP

0V

VDDIO/2

VDDIO/2 VDDIO/2VDDIO/2

VDDIO

80%

20%

80%

20%

tCLKT tCLKT

PCLK

VDD

0V

0V

VOUT

VOUT

Single-Ended

Differential

VOS

(DOUT+) - (DOUT-)

|

VOD

DOUT+ or DOUT-

13



Timing Diagrams (continued)

Figure 6. Serializer VOD Diagram

Figure 7. Serializer Input Clock Transition Times Figure 8. Serializer Setup/Hold Times

Figure 9. Serializer PLL Lock Time

Figure 10. Serializer Delay



Jitter Frequency (MHz)

Jitte

rA

mplit

ude (

UI)

0.1 1 100

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

- 18

- 16

-14

-12

-10

- 8

- 6

- 4

- 2

0

2

4

MODULATION FREQUENCY (Hz)

1.0E+04 1.0E+071.0E+061.0E+05

JIT

TE

RT

RA

NS

FE

R (

dB

)

14



6.11 Typical Characteristics

Figure 11. Typical Serializer Jitter Transfer Function Figure 12. Typical System Input Jitter Tolerance Curve -DS90UB933 Linked to DS90UB934



DIN

10 or 12

DS90UB933-Q1 - SERIALIZER

Clock Gen

Timing and Control

DOUT-

DOUT+

Inp

ut L

atc

h

FIF

O

De

co

de

r

En

co

de

r

Se

ria

lize

r

PLL

I2C

Co

ntr

olle

r

En

co

de

r

RT RT

PCLK

SDA

SCL

GPO[3:0]4

PDB

ID[x]

HSYNC

VSYNC

MODE


15



7 Detailed Description

7.1 OverviewThe DS90UB933-Q1 is optimized to interface with the DS90UB934-Q1 or DS90UB964-Q1 using a 50-Ω coaxinterface. The DS90UB933-Q1 also works with the DS90UB934-Q1 or DS90UB964-Q1 using an STP interface.

The DS90UB933/934 FPD-Link III chipsets are intended to link mega-pixel camera imagers and videoprocessors in ECUs. The Serializer/Deserializer chipset can operate from 37.5 MHz to 100 MHz pixel clockfrequency. The DS90UB933-Q1 device transforms a 10/12-bit wide parallel LVCMOS data bus along with abidirectional control channel control bus into a single high-speed differential pair. The high-speed serial bitstream contains an embedded clock and DC-balanced information which enhances signal quality to support ACcoupling. The DS90UB934-Q1 device receives the single serial data stream and converts it back into a 10/12-bitwide parallel data bus together with the control channel data bus. The DS90UB933/934 chipsets can accept upto:• 12-bits of DATA + 2 SYNC bits for an input PCLK range of 37.5 MHz to 100 MHz in the 12-bit mode. Note:

No HS/VS restrictions (raw).• 10-bits of DATA + 2 SYNC bits for an input PCLK range of 50 MHz to 100 MHz in the 10-bit mode. Note:

HS/VS restricted to no more than one transition per 10 PCLK cycles.

The DS90UB933/934 chipset offer customers the choice to work with different clocking schemes. TheDS90UB933/934 chipsets can use an external oscillator as the reference clock source for the PLL (seeDS90UB933/934 Operation With External Oscillator as Reference Clock) or PCLK from the imager as primaryreference clock to the PLL (see DS90UB933/934 Operation With Pixel Clock From Imager as Reference Clock).

7.2 Functional Block Diagram



16



7.3 Feature Description

7.3.1 Serial Frame FormatThe high-speed forward channel is composed of 28 bits of data containing video data, sync signals, I2C, andparity bits. This data payload is optimized for signal transmission over an AC-coupled link. Data is randomized,balanced and scrambled. The 28-bit frame structure changes in the 12-bit mode and 10-bit mode internally and isseamless to the customer. The bidirectional control channel data is transferred over the single serial link alongwith the high-speed forward data. This architecture provides a full-duplex low-speed forward and backward pathacross the serial link together with a high-speed forward channel without the dependence on the video blankingphase.

7.3.2 Line Rate Calculations for the DS90UB933/934The DS90UB933-Q1 device divides the clock internally by divide-by-2 in the 10-bit mode and by divide-by-1.5 inthe 12-bit mode. Conversely, the DS90UB934-Q1 multiplies the recovered serial clock to generate the properpixel clock output frequency. The following are the formulae used to calculate the maximum line rate in thedifferent modes:• For the 12-bit mode, Line rate = ƒPCLK × (2/3) × 28; for example, ƒPCLK = 100 MHz, line rate = (100 MHz) ×

(2/3) × 28 = 1.87 Gbps• For the 10-bit mode, Line rate = ƒPCLK/2 × 28; for example, ƒPCLK = 100 MHz, line rate = (100 MHz/2) × 28 =

1.40 Gbps

7.3.3 Error DetectionThe chipset provides error detection operations for validating data integrity in long distance transmission andreception. The data error detection function offers users flexibility and usability of performing bit-by-bit datatransmission error checking. The error detection operating modes support data validation of the following signals:• Bidirectional control channel data across the serial link• Parallel video/sync data across the serial link

The chipset provides 1 parity bit on the forward channel and 4 cyclic redundancy check (CRC) bits on the backchannel for error detection purposes. The DS90UB933/934 chipset checks the forward and back channel seriallinks for errors and stores the number of detected errors in two 8-bit registers in the serializer and thedeserializer, respectively.

To check parity errors on the forward channel, monitor registers 0x55 and 0x56 on the DS90UB934. The parityerror counter registers return the number of data parity errors that have been detected on the FPD3 receiver datasince the last detection of valid lock or last read of these registers (0x55 and 0x56). These registers are clearedon read.

To check CRC errors on the back channel, monitor registers 0x0A and 0x0B on the serializer.



DES A

GPIO[n] Input

DES B

GPIO[n] Input

SER A

GPIO[n] Output

SER B

GPIO[n] Output

t1

||

t2


ECU

Module

Deserializer ASerializer A

CMOS

Image

Sensor

I2C I2C

PC

Deserializer BSerializer B

CMOS

Image

Sensor

I2C I2C

Camera B

Camera A

DATAPCLK

DATAPCLK

FSYNC

FSYNC

GP

O

GP

IO FSYNC

GP

O

GP

IO FSYNC

DATAPCLK

DATAPCLK

FS

OF

SO

FS

INF

SIN

17



Feature Description (continued)7.3.4 Synchronizing Multiple CamerasFor applications requiring multiple cameras for frame-synchronization, TI recommends using the general purposeinput/output (GPIO) pins to transmit control signals to synchronize multiple cameras together. To synchronize thecameras properly, the system controller must provide a field sync output (such as a vertical or frame syncsignal), and the cameras must be set to accept an auxiliary sync input. The vertical synchronize signalcorresponds to the start and end of a frame and the start and end of a field. Note this form of synchronizationtiming relationship has a non-deterministic latency. After the control data is reconstructed from the bidirectionalcontrol channel, there is a time variation of the GPIO signals arriving at the different target devices (between theparallel links). The maximum latency (t1) of the GPIO data transmitted across the link is 32 µs.

NOTEThe user must verify that the timing variations between the different links are within theirsystem and timing specifications.

See Figure 13 for an example of this function.

The maximum time (t2) between the time the GPIO signal arrives at Camera A and Camera B is 23 µs.

Figure 13. Synchronizing Multiple Cameras

Figure 14. GPIO Delta Latency



DIN/

ROUT

PCLK

TRFB/RRFB: 0 TRFB/RRFB: 1

18



Feature Description (continued)7.3.5 General Purpose I/O (GPIO) DescriptionsThere are 4 GPOs on the serializer and 4 GPIOs on the deserializer when the DS90UB933/934 chipsets are runoff the pixel clock from the imager as the reference clock source. The GPOs on the serializer can be configuredas outputs for the input signals that are fed into the deserializer GPIOs. In addition, the GPOs on the serializercan behave as outputs of the local register on the serializer. The GPIOs on the deserializer can be configured tobe the input signals feeding the GPOs (configured as outputs) on the serializer. In addition the GPIOs on thedeserializer can be configured to behave as outputs of the local register on the deserializer. The DS90UB933-Q1serializer GPOs cannot be configured as inputs for remote communication with deserializer. If theDS90UB933/934 chipsets are run off the external oscillator source as the reference clock, then GPO3 on theserializer is automatically configured to be the input for the external clock and GPO2 is configured to be theoutput of the divide-by-2 clock which is fed into the imager as its reference clock. In this case, the GPIO2 andGPIO3 on the deserializer can only behave as outputs of the local register on the deserializer. The GPIOmaximum switching rate is up to 66 kHz when configured for communication between deserializer GPIO toserializer GPO.

7.3.6 LVCMOS V(VDDIO) Option1.8 V/2.8 V/3.3 V Serializer inputs are user configurable to provide compatibility with 1.8 V, 2.8 V, and 3.3 Vsystem interfaces.

7.3.7 Pixel Clock Edge Select (TRFB / RRFB)The TRFB/RRFB selects which edge of the pixel clock is used. For the SER, this register determines the edgethat the data is latched on. If TRFB register is 1, data is latched on the rising edge of the PCLK. If TRFB registeris 0, data is latched on the falling edge of the PCLK. For the DES, this register determines the edge that the datais strobed on. If RRFB register is 1, data is strobed on the rising edge of the PCLK. If RRFB register is 0, data isstrobed on the falling edge of the PCLK.

Figure 15. Programmable PCLK Strobe Select

7.3.8 Power DownThe SER has a PDB input pin to ENABLE or power down the device. Enabling PDB on the SER disables the linkto save power. If PDB = HIGH, the SER operates at its internal default oscillator frequency when the input PCLKstops. When the PCLK starts again, the SER locks to the valid input PCLK and transmit the data to the DES.When PDB = LOW, the high-speed driver outputs are static HIGH. See Power-Up Requirements and PDB Pin forpower-up requirements.




FPD Link III-

High Speed

Bi-Directional

Control Channel

Image

Sensor

ECU Module

DIN[11:0] or DIN[9:0]HSYNC, VSYNC

SDA

SCL

DOUT- RIN-

DOUT+ RIN+

Camera Unit

10 or 12

DATA

HSYNC

VSYNC

PCLKPixel Clock

SDA

SCL

Microcontroller

ROUT[11:0] or

ROUT[9:0] HSYNC, VSYNC

SDA

SCL

PCLK

10 or 12

DATA

HSYNC

VSYNC

Pixel Clock

SDA

SCL

Camera Data

DeserializerSerializer

GPO[1:0]

GPO[1:0]2

GPO[3:0]

4GPIO[3:0]

Camera Data

External

Oscillator

PLL

÷2

GPO3

GPO2

Reference Clock (Ext. OSC/2)

19



7.4 Device Functional Modes

7.4.1 DS90UB933/934 Operation With External Oscillator as Reference ClockIn some applications, the pixel clock that comes from the imager can have jitter which exceeds the tolerance ofthe DS90UB933/934/964 chipsets. In this case, operate the DS90UB933-Q1 device by using an external clocksource as the reference clock for the DS90UB933/934/964 chipsets. This is the recommended operating mode.The external oscillator clock output goes through a divide-by-2 circuit in the DS90UB933-Q1 serializer, and thisdivided clock output is used as the reference clock for the imager. The output data and pixel clock from theimager are then fed into the DS90UB933-Q1 device. Figure 16 shows the operation of the DS90UB33/934chipsets while using an external automotive grade oscillator.

Figure 16. DS90UB933-Q1/934-Q1 Operation in the External Oscillator Mode

When the DS90UB933-Q1 device is operated using an external oscillator, the GPO3 pin on the DS90UB933-Q1is the input pin for the external oscillator. In applications where the DS90UB933-Q1 device is operated from anexternal oscillator, the divide-by-2 circuit in the DS90UB933-Q1 device feeds back the divided clock output to theimager device through GPO2 pin. The pixel clock to external oscillator ratios must be fixed for the 12–bit modeand the 10–bit mode. In the 10-bit mode, the pixel clock frequency divided by the external oscillator frequencymust be 2. In the 12-bit mode, the pixel clock frequency divided by the external oscillator frequency must be 1.5.For example, if the external oscillator frequency is 48 MHz in the 10-bit mode, the pixel clock frequency of theimager must be twice of the external oscillator frequency, that is, 96 MHz. If the external oscillator frequency is48 MHz in the 12-bit mode, the pixel clock frequency of the imager must be 1.5 times of the external oscillatorfrequency, that is, 72 MHz. For the range of PCLK frequency and the external clock input frequency to GPO3 in10-bit and 12-bit modes, see Recommended Operating Conditions.

When PCLK signal edge is detected, and 0x03[1] = 0, the DS90UB933-Q1 switches from internal oscillator modeto an external PCLK. Upon removal of PCLK input, the device switches back into internal oscillator mode. Inexternal oscillator mode, GPO2 and GPO3 on the serializer cannot act as the output of the input signal comingfrom GPIO2 or GPIO3 on the deserializer.

Table 1. Device Functional Mode With Example XCLKIN = 48 MHz

MODE GPIO3 XCLKIN GPIO2 XCLKOUT =XCLKIN / 2 RATIO INPUT PCLK FREQUENCY =

XLCKIN * RATIO10-bit 48 MHz 24 MHz 2 96 MHz12-bit 48 MHz 24 MHz 1.5 72 MHz



Serializer

R1

R2

MODE

1.8 V

VMODE


FPD-Link III

Bi-Directional

Back Channel

Image Sensor

ECU Module

DIN[11:0] or

DIN[9:0]

FV,LV

SDA

SCL

DOUT- RIN0-

DOUT+ RIN0+

Camera Unit

10 or 12

YUV

HSYNC

VSYNC

PCLKPixel Clock

SDA

SCL

Microcontroller

ROUT[11:0]

or

ROUT[9:0] FV, LV

SDA

SCL

PCLK

10 or 12

YUV

HSYNC

VSYNC

Pixel Clock

SDA

SCL

Camera Data

DeserializerSerializer

GPOGPO[3:0]

4

GPIO

4GPIO[3:0]

Camera Data

Ext. Oscillator

PLL RIN1-

RIN1+

20



7.4.2 DS90UB933/934 Operation With Pixel Clock From Imager as Reference ClockThe DS90UB933/934/964 chipsets can be operated by using the pixel clock from the imager as the referenceclock. Figure 17 shows the operation of the DS90UB933/934/964 chipsets using the pixel clock from the imager.If the DS90UB933-Q1 device is operated using the pixel clock from the imager as the reference clock, then theimager uses an external oscillator as its reference clock. There are 4 GPIOs available in this mode (PCLK fromimager mode).

Figure 17. DS90UB933-Q1/934-Q1 Operation in PCLK mode

7.4.3 MODE Pin on SerializerThe MODE pin on the serializer can be configured to select if the DS90UB933-Q1 device is to be operated fromthe external oscillator or the PCLK from the imager. The pin must be pulled to VDD_n(1.8 V, not VDDIO) with aresistor R1 and a pulldown resistor R2 for external oscillator mode to create the ratio shown in Figure 18. If thedevice is to be operated from PCLK from imager mode, MODE pin can be pulled up to VDD_n (1.8V) with a 10-kΩresistor directly or use the ratio shown in Figure 18 and Table 2. Suggested resistor values are given in Table 2.The recommended maximum resistor tolerance is 1%. Other resistor values can be used as long as the ratio ismet under all conditions.

Figure 18. MODE Pin Configuration on DS90UB933-Q1



21



Table 2. DS90UB933-Q1 SerializerMODE Setting

DS90UB933-Q1 SERIALIZER MODE SETTING

MODE SELECT MINIMUM RATIO(VMODE/V(VDD_n))

MAXIMUM RATIO(VMODE/V(VDD_n))

SUGGESTED R1RESISTOR VALUE (kΩ)

SUGGESTED R2 RESISTORVALUE (kΩ)

PCLK from imagermode 0.750 1.000 10 50

External oscillatormode 0.292 0.339 10 4.7

7.4.4 Internal OscillatorWhen a PCLK is not applied to the DS90UB933-Q1, the serializer establishes the FPD-III link using an internaloscillator. During normal operation (not BIST) the frequency of the internal oscillator can be adjusted fromDS90UB933-Q1 register 0x14[2:1] according to Table 3. In BIST mode, the internal oscillator frequency shouldonly be adjusted from the DS90UB934-Q1. The BIST frequency can be set by either pin strapping (Table 4) orregister (Table 5). In BIST DS90UB933-Q1 register 0x14[2:1] is automatically loaded from the DS90UB934-Q1through the bi-directional control channel.

Table 3. Clock Sources for Forward Channel Frame on the Serializer During Normal OperationDS90UB933-Q1Reg 0x14 [2:1]

10-BITMODE

12-BITMODE

00 50 MHz 37.5 MHz01 100 MHz 75 MHz10 50 MHz 37.5 MHz11 Reserved Reserved

7.4.5 Built-In Self TestAn optional at-speed built-in self test (BIST) feature supports the testing of the high-speed serial link and low-speed back channel. This is useful in the prototype stage, equipment production, and in-system test and also forsystem diagnostics.



22



7.4.6 BIST Configuration and StatusThe chipset can be programmed into BIST mode using either pins or registers on the DES only. By default, BISTconfiguration is controlled through pins. BIST can be configured via registers using BIST Control register (0xB3).Pin-based configuration is defined as follows:• BISTEN = HIGH: Enable the BIST mode, BISTEN = LOW: Disable the BIST mode.• Deserializer GPIO0 and GPIO1: Defines the BIST clock source (PCLK vs various frequencies of internal

OSC)

Table 4. BIST Pin ConfigurationDESERIALIZER GPIO[0:1] OSCILLATOR SOURCE BIST FREQUENCY

00 External PCLK PCLK or external oscillator01 Internal ~50 MHz10 Internal ~25 MHz

Table 5. BIST Register ConfigurationDS90UB934-Q1Reg 0xB3 [2:1]

10-BITMODE

12-BITMODE

00 PCLK PCLK01 100 MHz 75 MHz10 50 MHz 37.5 MHz11 Reserved Reserved

BIST mode provides various options for the PCLK source. Either external pins (GPIO0 and GPIO1) or registerscan be used to program the BIST to use external PCLK or various OSC frequencies. Refer to Table 4 for pinsettings. The BIST status can be monitored real-time on the PASS pin. For every frame with error(s), the PASSpin toggles low for one-half PCLK period. If two consecutive frames have errors, PASS toggles twice to allowcounting of frames with errors. Once the BIST is done, the PASS pin reflects the pass/fail status of the last BISTrun only for one PCLK cycle. The status can also be read through I2C for the number of frames in errors. BISTstatus register retains results until it is reset by a new BIST session or a device reset. To evaluate BIST inexternal oscillator mode, both the external oscillator and PCLK must be present. For all practical purposes, theBIST status can be monitored from the BIST Error Count register 0x57 on the DS90UB934 deserializer.

7.4.7 Sample BIST Sequence• Step 1: For the DS90UB933/934 FPD-Link III chipset, BIST mode is enabled via the BISTEN pin of

DS90UB934-Q1 FPD-Link III deserializer. The desired clock source is selected through the deserializerGPIO0 and GPIO1 pins as shown in Table 4.

• Step 2: The DS90UB933-Q1 serializer BIST pattern is enabled through the back channel. The BIST pattern issent through the FPD-Link III to the deserializer. Once the serializer and deserializer are in the BIST modeand the deserializer acquires lock, the PASS pin of the deserializer goes high, and BIST starts checking theFPD-Link III serial stream. If an error in the payload is detected, the PASS pin switches low for one half of theclock period. During the BIST test, the PASS output can be monitored and counted to determine the payloaderror rate.

• Step 3: To stop the BIST mode, the deserializer BISTEN pin is set LOW. The deserializer stops checking thedata. The final test result is not maintained on the PASS pin. To monitor the BIST status, check the BISTError Count register, 0x57 on the deserializer.

• Step 4: The link returns to normal operation after the deserializer BISTEN pin is low. Figure 20 shows thewaveform diagram of a typical BIST test for two cases. Case 1 is error free, and Case 2 shows one withmultiple errors. In most cases, it is difficult to generate errors due to the robustness of the link (differentialdata transmission, etc.); thus, they may be introduced by greatly extending the cable length, faulting theinterconnect, or by reducing signal condition enhancements (Rx equalization).



X XX

PCLK

(RFB = L)

BISTEN

(DES)

PASS

DATA

(internal)

PASS

BIST Duration

Prior Result

BIST

Result

Held

PASS

FAIL

X = bit error(s)

ROUT[0:11],

HS, VS

DATA

(internal)

Ca

se

1 -

Pa

ss

Ca

se

2 -

Fa

il

Prior Result

Normal BIST Test Normal

DE

S O

utp

utsLOCK

Normal

BIST

start

BIST

stop

BIST

Wait

Step 1: DES in BIST

Step 2: Wait, SER in BIST

Step 3: DES in Normal

Mode - check PASS

Step 4: DES/SER in Normal

23



Figure 19. At-Speed BIST System Flow Diagram

Figure 20. BIST Timing Diagram



SCL

SDA

START STOP

1 2 6 7 8 9 1 2 8 9

MSB

7-bit Slave Address

R/W

Direction

BitAcknowledge

from the Device

MSB

Data Byte

*Acknowledge

or Not-ACK

ACK N/ACK

Repeated for the Lower Data Byte

and Additional Data Transfers

LSB LSB

Bus Activity:

Master

SDA Line

Bus Activity:

Slave

Sta

rt

Slave

Address

A

C

K

S

Address

A

C

K

S

Sta

rt

Slave

Address

A

C

K

N

A

C

K

P

Sto

p

Data

0 1

Register

7-bit Address 7-bit Address

A

C

K

A

C

K

A

C

K

S P

Sto

p

Bus Activity:

Slave

SDA Line

Bus Activity:

MasterSlave

Address Address Data

Sta

rt

0

Register

7-bit Address

24



7.5 Programming

7.5.1 Programmable ControllerAn integrated I2C slave controller is embedded in the DS90UB933-Q1 serializer. It must be used to configure theextra features embedded within the programmable registers or it can be used to control the set of programmableGPIOs.

7.5.2 Description of Bidirectional Control Bus and I2C ModesThe I2C-compatible interface allows programming of the DS90UB933-Q1, DS90UB934-Q1, DS90UB964-Q1, oran external remote device (such as image sensor) through the bidirectional control channel. Registerprogramming transactions to/from the DS90UB933/934/964 chipset are employed through the clock (SCL) anddata (SDA) lines. These two signals have open drain I/Os, and both lines must be pulled up to V(VDDIO) by anexternal resistor. Pullup resistors or current sources are required on the SCL and SDA busses to pull them highwhen they are not being driven low. A logic LOW is transmitted by driving the output low. Logic HIGH istransmitted by releasing the output and allowing it to be pulled up externally. The appropriate pullup resistorvalues depend upon the total bus capacitance and operating speed. The DS90UB933-Q1 I2C bus data ratesupports up to 400 kbps according to I2C fast mode specifications.

For further description of general I2C communication, refer to the Understanding the I2C Bus application note .For more information on choosing appropriate pullup resistor values, see the I2C Bus Pullup Resistor Calculationapplication note .

Figure 21. Write Byte

Figure 22. Read Byte

Figure 23. Basic Operation



http://www.ti.com/cn/lit/pdf/SLVA704


ECU

Module

DS90UB934-Q1DS90UB933-Q1

DIN[11:0]

,HS,VS

PCLK

CMOS

Image

Sensor

I2C

ROUT[11:0],

HS,VS,

PCLK

I2C

SDASCL

SDASCL

PC

DES B: I2C_SLAVE

Local

I2C_PASS_THRU Disabled


DIN[11:0]

,HS,VS

PCLK

CMOS

Image

Sensor

I2C

ROUT[11:0],

HS,VS,

PCLK

I2C

SDASCL

SDASCL

Camera B

Slave ID: (0xA0)

SER A:

Remote I2C _MASTER Proxy

DES A: I2C_SLAVE

Local

I2C_PASS_THRU Enabled

Camera A

Slave ID: (0xA0)

MasterSER B:

Remote I2C_MASTER Proxy

SDA

SCL

S P

START condition, or

START repeat condition

STOP condition

25



Programming (continued)

Figure 24. Start and Stop Conditions

7.5.3 I2C Pass-ThroughI2C pass-through provides a way to access remote devices at the other end of the FPD-Link III interface. Thisoption is used to determine if an I2C instruction is transferred over to the remote I2C bus. For example, when theI2C master is connected to the deserializer and I2C pass-through is enabled on the deserializer, any I2C traffictargeted for the remote serializer or remote slave is allowed to pass through the deserializer to reach thoserespective devices.

If the master controller transmits an I2C transaction for address 0xA0, the DES A with I2C pass-through enabledtransfers I2C commands to remote Camera A. The DES B (with I2C pass-through disabled) will NOT pass I2Ccommands on the I2C bus to Camera B.

Figure 25. I2C Pass-Through

7.5.4 Slave Clock StretchingThe I2C-compatible interface allows programming of the DS90UB933-Q1, DS90UB934-Q1, DS90UB964-Q1, oran external remote device (such as image sensor) through the bidirectional control. To communicate andsynchronize with remote devices on the I2C bus through the bidirectional control channel/MCU, the chipsetutilizes bus clock stretching (holding the SCL line low) during data transmission; where the I2C slave pulls theSCL line low on the 9th clock of every I2C transfer (before the ACK signal). The slave device does not controlthe clock and only stretches it until the remote peripheral has responded. The I2C master must support clockstretching to operate with the DS90UB933/934/964 chipset.




HOST Serializer

SCL

SDA

RPU RPU

R3

R4

SCL

SDA

To other Devices

ID[x]

1.8V

VDDIO

VID[x]

26



Programming (continued)7.5.5 IDX Address Decoder on the SerializerThe IDX pin on the serializer is used to decode and set the physical slave address of the serializer (I2C only) toallow up to five devices on the bus connected to the serializer using only a single pin. The pin sets one of the 4possible addresses for each serializer device. The pin must be pulled to V(VDD_n) (1.8 V, not V(VDDIO)) with aresistor, R3, and a pulldown resistor R4. Suggested resistor values are given in Table 6. The recommendedmaximum resistor tolerance is 1%. Other resistor values can be used as long as the ratio is met under allconditions.

Figure 26. IDX Address Decoder on the Serializer

Table 6. IDX Setting for DS90UB933-Q1 SerializerIDX SETTING — DS90UB933-Q1 SERIALIZER

MINIMUMRATIO

(VIDX/V(VDD_n))

MAXIMUMRATIO

(VIDX/V(VDD_n))

SUGGESTEDR3 RESISTORVALUE (kΩ)

SUGGESTEDR4 RESISTORVALUE (kΩ)

Address 7-bitAddress 8-bit0 appended

(WRITE)0 0 Open 0 0x58 0xB0

0.114 0.186 10 2 0x59 0xB20.297 0.347 10 4.7 0x5A 0xB40.742 1.0 10 100 0x5D 0xBA



ECU

Module


DIN[11:0]

, HS, VS,

PCLK

CMOS

Image

Sensor

I2C I

2C

SDASCL

SDASCL

PC

DES B: ID[x](0xC2)

SLAVE_ID0_ALIAS(0xA4)

SLAVE_ID0_ID(0xA0)


SLAVE_ID1_ID(0xA2)


CMOS

Image

Sensor

I2C I

2C

SDASCL

SDASCL

Camera BSlave ID: (0xA0)

SER A: ID[x](0xB0)DES A: ID[x](0xC0)


SLAVE_ID0_ID(0xA0)


SLAVE_ID1_ID(0xA2)

Camera ASlave ID: (0xA0)

MasterSER B: ID[x](0xB2)

Slave ID: (0xA2)

Slave ID: (0xA2)

ROUT[11:0],

HS, VS,

PCLK

DIN[11:0]

, HS, VS,

PCLK

ROUT[11:0],

HS, VS,

PCLK

PC/EEPROM

PC/EEPROM

27



7.5.6 Multiple Device AddressingSome applications require multiple camera devices with the same fixed address to be accessed on the same I2Cbus. The DS90UB933-Q1 provides slave ID matching/aliasing to generate different target slave addresses whenconnecting more than two identical devices together on the same bus. This allows the slave devices to beindependently addressed. Each device connected to the bus is addressable through a unique ID by programmingof the slave alias register on deserializer. This remaps the slave alias address to the target SLAVE_ID address;up to 8 ID aliases are supported in sensor mode when slaves are attached to the DS90UB933-Q1 serializer. Indisplay mode, when the external slaves are at the deserializer the DS90UB933-Q1 supports one ID alias. TheECU controller must keep track of the list of I2C peripherals in order to properly address the target device.

See Figure 27 for an example of this function.• ECU is the I2C master and has an I2C master interface.• The I2C interfaces in DES A and DES B are both slave interfaces.• The I2C protocol is bridged from DES A to SER A and from DES B to SER B.• The I2C interfaces in SER A and SER B are both master interfaces.

If master controller transmits I2C slave 0xA0, DES A (address 0xC0), with pass-through enabled, forwards thetransaction to remote Camera A. If the controller transmits slave address 0xA4, the DES B 0xC2 recognizes that0xA4 is mapped to 0xA0 and is transmitted to the remote Camera B. If controller sends command to address0xA6, the DES B (address 0xC2), with pass-through enabled, forwards the transaction to slave device 0xA2.

Figure 27. Multiple Device Addressing



28



(1) To ensure optimum device functionality, TI recommends to NOT write to any RESERVED registers.

7.6 Register MapsSee note (1)

In the register definitions under the TYPE and DEFAULT heading, the following definitions apply:• R = Read only access• R/W = Read / Write access• R/RC = Read only access, Read to Clear• (R/W)/SC = Read / Write access, Self-Clearing bit• (R/W)/S = Read / Write access, Set based on strap pin configuration at startup• LL = Latched Low and held until read• LH = Latched High and held until read• S = Set based on strap pin configuration at startup

Table 7. DS90UB933-Q1 Control RegistersAddr(Hex) Name Bits Field TYPE Default Description

0x00 I2C Device ID7:1 DEVICE ID

R/W 0xB0

7-bit address of serializer (0x58'h default). This fielddoes not auto update IDX strapped address.

0 Serializer ID SEL 0: Device ID is from IDX1: Register I2C Device ID overrides IDX

0x01 Power and Reset

7 RSVD R/W 0 Reserved

6 RDS R/W 0Digital output drive strength1: High drive strength0: Low drive strength

5 V(VDDIO) Control R/W 1Auto voltage control1: Enable0: Disable

4 V(VDDIO) MODE R/W 1V(VDDIO) voltage set1: V(VDDIO) = 3.3 V0: V(VDDIO) = 1.8 V

3 ANAPWDN R/W 0

This register can be set only through local I2C access.1: Analog power down. Powers down the analog blockin the serializer.0: No effect


1 DIGITALRESET1 R/W 0

1: Resets the digital block except for register values.Does not affect device I2C bus or Device ID. This bit isself-clearing.0: Normal operation

0 DIGITALRESET0 R/W 0

1: Digital reset, resets the entire digital block includingall register values. This bit is self-clearing.0: Normal operation.

0x02 Reserved



29



Register Maps (continued)Table 7. DS90UB933-Q1 Control Registers (continued)

Addr(Hex) Name Bits Field TYPE Default Description

0x03 GeneralConfiguration

7 RX CRC CheckerEnable R/W 1

Back-channel CRC checker enable1: Enable0: Disable

6 TX ParityGenerator Enable R/W 1

Forward channel parity generator enable.1: Enable0: Disable

5 CRC Error Reset R/W 0

Clear CRC error countersThis bit is NOT self-clearing.1: Clear counters0: Normal operation

4I2C Remote WriteAutoAcknowledge

R/W 0

Automatically acknowledge I2C remote writeThe mode works when the system is LOCKed.1: Enable: When enabled, I2C writes to thedeserializer (or any remote I2C Slave, if I2C PASSALL is enabled) are immediately acknowledgedwithout waiting for the deserializer to acknowledge thewrite. The accesses are then remapped to addressspecified in 0x06.0: Disable

3 I2C Pass-Through All R/W 0

1: Enable Forward Control Channel pass-through of allI2C accesses to I2C IDs that do not match theserializer I2C ID. The I2C accesses are thenremapped to address specified in register 0x06.0: Enable Forward Control Channel pass-through onlyof I2C accesses to I2C IDs matching either the remotedeserializer ID or the remote I2C IDs.

2 I2C Pass-Through R/W 1

I2C Pass-through mode1: Pass-through enabled. DES alias 0x07 and slavealias 0x090: Pass-through disabled

0x03 GeneralConfiguration

1 OV_CLK2PLL R/W 0

1:Enabled : When enabled this register overrides theclock to PLL mode (External Oscillator mode or DirectPCLK mode) defined through MODE pin and allowsselection through register 0x35 in the serializer.0: Disabled : When disabled, Clock to PLL mode(External Oscillator mode or Direct PCLK mode) isdefined through MODE pin on the Serializer.

0 TRFB R/W 1

Pixel clock edge select1: Parallel interface data is strobed on the rising clockedge0: Parallel interface data is strobed on the falling clockedge

0x04 Reserved



30





0x05 Mode Select

7 RSVD R/W 0 Reserved6 RSVD R/W 0 Reserved

5 MODE_OVERRIDE R/W 0

Allows overriding mode select bits coming from back-channel.1: Overrides MODE select bits0: Does not override MODE select bits

4 MODE_UP_TO_DATE R 0

1: Status of mode select from deserializer is up-to-date.0: Status is NOT up-to-date.

3 Pin_MODE_12–bit mode R 0 1: 12-bit mode is selected.

0: 12-bit mode is not selected.

2 Pin_MODE_10–bit mode R 0 1: 10-bit mode is selected.

0: 10-bit mode is not selected.

1 TX_MODE_12b R/W 0

Selects 12 bit data-bus. This bit changes the Tx modesettings if MODE_OVERRIDE is SET 0x05[5] = 1.1: Enables 12 bit HF mode0: Disables 12 bit HF modeNote: This bit changes mode settings on TX. WhenTX_MODE_12b is set TX_MODE_10b must becleared; 0x05[1:0] = 10.

0 TX_MODE_10b R/W 0

Selects 10 bit data-bus. This bit changes the Tx modesettings if MODE_OVERRIDE is SET 0x05[5] = 1.1: Enables 10b mode0: Disables 10b modeNote: This bit changes mode settings on TX. WhenTX_MODE_10b is set TX_MODE_12b must becleared; 0x05[1:0] = 01.

0x06 DES ID

7:1 DeserializerDevice ID R/W 0x00

7-bit deserializer Device ID Configures the I2C SlaveID of the remote deserializer. A value of 0 in this fielddisables I2C access to the remote deserializer. Thisfield is automatically configured by the bidirectionalcontrol channel once RX Lock has been detected.Software may overwrite this value, but should alsoassert the FREEZE DEVICE ID bit to preventoverwriting by the bidirectional control channel.

0 Freeze Device ID R/W 0

1: Prevents auto-loading of the deserializer Device IDby the bidirectional control channel. The ID is frozen atthe value written.0: Update

0x07 DES Alias7:1 Deserializer

ALIAS ID R/W 0x00

7-bit remote deserializer device alias ID Configures thedecoder for detecting transactions designated for anI2C deserializer device. The transaction is remappedto the address specified in the DES ID register.A value of 0 in this field disables access to the remotedeserializer.


0x08 SlaveID7:1 SLAVE ID R/W 0x00

7-bit remote slave device ID Configures the physicalI2C address of the remote I2C slave device attachedto the remote deserializer. If an I2C transaction isaddressed to the slave alias ID, the transaction isremapped to this address before passing thetransaction across the bidirectional control channel tothe deserializer and then to remote slave. A value of 0in this field disables access to the remote I2C slave.




31





0x09 Slave Alias7:1 SLAVE ALIAS ID R/W 0x00

7-bit remote slave device alias ID Configures thedecoder for detecting transactions designated for anI2C slave device attached to the remote deserializer.The transaction is remapped to the address specifiedin the slave ID register. A value of 0 in this fielddisables access to the remote I2C slave.


0x0A CRC Errors 7:0 CRC Error Byte 0 R 0x00 Number of back-channel CRC errors during normaloperation. Least significant byte.

0x0B CRC Errors 7:0 CRC Error Byte 1 R 0x00 Number of back-channel CRC errors during normaloperation. Most significant byte

0x0C General Status

7:5 Rev-ID R 0x0 Revision ID0x0: Production Revision ID

4 RX Lock Detect R 0 1: RX LOCKED0: RX not LOCKED

3 BIST CRCError Status R 0 1: CRC errors in BIST mode

0: No CRC errors in BIST mode

2 PCLK Detect R 0 1: Valid PCLK detected0: Valid PCLK not detected

1 DES Error R 0

1: CRC error is detected during communication withdeserializer.This bit is cleared upon loss of link or assertion ofCRC ERROR RESET in register 0x03[5].0: No effect

0 LINK Detect R 0

1: Cable link detected0: Cable link not detectedThis includes any of the following faults:— Cable open— '+' and '-' shorted— Short to GND— Short to battery

0x0DGPO[0]

and GPO[1]Configuration

7 GPO1 OutputValue R/W 0

Local GPIO output value. This value is output on theGPIO pin when the GPIO function is enabled. Thelocal GPIO direction is output, and remote GPIOcontrol is disabled.

6 GPO1 RemoteEnable R/W 1

Remote GPIO Control1: Enable GPIO control from remote deserializer. TheGPIO pin must be an output, and the value is receivedfrom the remote Deserializer.0: Disable GPIO control from remote deserializer


4 GPO1 Enable R/W 1 1: GPIO enable0: Tri-state




Remote GPIO Control1: Enable GPIO control from remote deserializer. TheGPIO pin must be an output, and the value is receivedfrom the remote Deserializer.0: Disable GPIO control from remote deserializer.





32





0x0EGPO[2]

and GPO[3]Configuration




Remote GPIO vontrol1: Enable GPIO control from remote Deserializer. TheGPIO pin must be an output, and the value is receivedfrom the remote deserializer.0: Disable GPIO control from remote Deserializer.

5 GPO3 Direction R/W 1 1: Input0: Output





Remote GPIO Control1: Enable GPIO control from remote deserializer. TheGPIO pin must be an output, and the value is receivedfrom the remote deserializer.0: Disable GPIO control from remote deserializer.



0x0F I2C MasterConfig

7:5 RSVD R 0x0 Reserved

4:3 SDA OutputDelay R/W 00

SDA output delay This field configures output delay onthe SDA output. Setting this value increases outputdelay in units of 50 ns. Nominal output delay valuesfor SCL to SDA are:00: ~350 ns01: ~400 ns10: ~450 ns11: ~500 ns

2 Local WriteDisable R/W 0

Disable remote writes to local registers setting this bitto a 1 prevents remote writes to local device registersfrom across the control channel. This prevents writesto the serializer registers from an I2C master attachedto the deserializer. setting this bit does not affectremote access to I2C slaves at the serializer.

1 I2C Bus TimerSpeed up R/W 0

Speed up I2C bus watchdog timer1: Watchdog timer expires after approximately 50microseconds.0: Watchdog timer expires after approximately 1second.

0 I2C Bus TimerDisable R/W 0

1. Disable I2C bus watchdog timer when the I2Cwatchdog timer may be used to detect when the I2Cbus is free or hung up following an invalid terminationof a transaction. If SDA is high and no signalingoccurs for approximately 1 second, the I2C bus isassumed to be free. If SDA is low and no signalingoccurs, the device attempts to clear the bus by driving9 clocks on SCL.0: No effect



33





0x10 I2C Control


6:4 SDA Hold Time R/W 0x1Internal SDA hold time. This field configures theamount of internal hold time provided for the SDAinput relative to the SCL input. Units are 50 ns.

3:0 I2C Filter Depth R/W 0x7I2C glitch filter depth. This field configures themaximum width of glitch pulses on the SCL and SDAinputs that will be rejected. Units are 10 ns.

0x11 SCL High Time 7:0 SCL High Time R/W 0x82

I2C master SCL high time This field configures thehigh pulse width of the SCL output when the serializeris the master on the local I2C bus. Units are 50 ns forthe nominal oscillator clock frequency. The defaultvalue is set to provide a minimum (4 µs + 1 µs of risetime for cases where rise time is very fast) SCL hightime with the internal oscillator clock running at 26MHz rather than the nominal 20 MHz.

0x12 SCL LOW Time 7:0 SCL Low Time R/W 0x82

I2C SCL low time This field configures the low pulsewidth of the SCL output when the serializer is themaster on the local I2C bus. This value is also used asthe SDA setup time by the I2C slave for providing dataprior to releasing SCL during accesses over thebidirectional control channel. Units are 50 ns for thenominal oscillator clock frequency. The default value isset to provide a minimum (4.7 µs + 0.3 µs of fall timefor cases where fall time is very fast) SCL low timewith the internal oscillator clock running at 26 MHzrather than the nominal 20 MHz.

0x13 General PurposeControl 7:0 GPCR[7:0] R/W 0x00 1: High

0: Low

0x14 BIST Control

7:5 RSVD R 0x0 Reserved4:3 RSVD R/W 0x0 Reserved

2:1 Clock Source R/W 0x0

Allows choosing different OSC clock frequencies forforward channel frame.OSC clock frequency in functional mode when OSCmode is selected or when the selected clock source isnot present, for example, missing PCLK/ externaloscillator. See Table 3 for oscillator clock frequencieswhen PCLK/ external clock is missing.

0 RSVD R/W 0 Reserved0x15 -0x1D Reserved

0x1E BCC WatchdogControl

7:1 BCC WatchdogTimer R/W 0x7F

The watchdog timer allows termination of a controlchannel transaction if it fails to complete within aprogrammed amount of time. This field sets thebidirectional control channel watchdog timeout value inunits of 2 ms. This field should not be set to 0.

0 BCC WatchdogTimer Disable R/W 0 1: Disables BCC watchdog timer operation

0: Enables BCC watchdog timer operation0x1F -0x26 Reserved

0x27 Analog PowerDown Control

7:6 Reserved R 0 Reserved

5 Power Down PLL RW 0 1: Power down forward channel PLL0: Normal operation

4:0 Reserved RW 0 Reserved0x28 Reserved



34





0x29 OSC Divider 7:6 RSVD R/W 0x0 Reserved5 OSC Divider R/W 0 Selects the OSC frequency to drive out on GPO2 in

external oscillator mode.0: Divide by 2 (default)1: Divide by 4

4:0 RSVD R/W 0x06 Reserved

0x2A CRC Errors 7:0 BIST Mode CRCErrors Count R 0x00 Number of CRC errors in the back channel when in

BIST mode0x2B -0x2C Reserved

0x2D Inject ForwardChannel Error

7 Force ForwardChannel Error R/W 0

1: Forces 1 (one) error over forward channel frame innormal operating mode. Self-clearing bit.0: No error

6:0 Force BIST Error R/W 0x00

N: Forces N number of errors in BIST mode. Thisregister MUST be set BEFORE BIST mode is enabled.BIST error count register on the deserializer must beread AFTER BIST mode is disabled for the correctnumber of errors incurred while in BIST mode.0: No error

0x2E -0x34 Reserved

0x35 PLL ClockOverwrite

7:4 RSVD R/W 0x0 Reserved

3PIN_LOCK toExternalOscillator

R 0

Status of mode select pin1: Indicates external oscillator mode is selected bymode-resistor0: External oscillator mode is not selected by mode-resistor

2 RSVD R 0 Reserved

1 LOCK to ExternalOscillator R/W 0

Affects only when 0x03[1] =1 (OV_CLK2PLL) and0x35[0] = 01: Routes GPO3 directly to PLL0: Allows PLL to lock to PCLK

0 LOCK2OSC

R/W 1 Affects only when 0x03[1] = 1 (OV_CLK2PLL)1: Allows internal OSC clock to feed into PLL0: Allows PLL to lock to either PCLK or external clockfrom GPO3



VDDIO

VDD_n

PDB

t0

t1

t2

1.8 V or 3.3 V

1.8V

VDDIO

GND

GND

GND

t3

GPO2 'RQ¶W&DUH

35



8 Application and Implementation

NOTEInformation in the following applications sections is not part of the TI componentspecification, and TI does not warrant its accuracy or completeness. TI’s customers areresponsible for determining suitability of components for their purposes. Customers shouldvalidate and test their design implementation to confirm system functionality.

8.1 Application InformationThe DS90UB933-Q1 was designed as a serializer to support automotive camera designs. Automotive camerasare often located in remote positions such as bumpers or trunk lids, and a major component of the system cost isthe wiring. For this reason it is desirable to minimize the wiring to the camera. This chipset allows the video data,along with a bidirectional control channel, and power to all be sent over a single coaxial cable. The chipset isalso able to transmit over STP and is pin-to-pin/backwards compatible with the DS90UB913A-Q1 andDS90UB913Q-Q1.

8.1.1 Power Over CoaxSee application report Sending Power Over Coax in DS90UB933 Designs for more details.

8.1.2 Power-Up Requirements and PDB PinTransition of the PDB pin from LOW to HIGH must occur after the VVDDIO and VVDD_n supplies have reached theirrequired operating voltage levels. Direct control of the PDB timing by processor GPIO is recommended ifpossible. When direct control of PDB is not available, the PDB pin can be tied to the power supply rail with anRC filter network to help ensure proper power up timing. GPO2 should be low when PDB goes high. Timingconstraints are noted in Figure 28 and Table 8. Please refer to Power Down for device operation when powereddown.

If GPO2 state is not determined when PDB goes high, DS90UB933 registers must be programmed to configurethe transmission mode. Mode Select register 0x05[5] must be set to 1 and register 0x05 bit 1 and 0 are to beselected based on desired 12-bit or 10-bit transmit data format.

Common applications tie the V(VDDIO) and V(VDD_n) supplies to the same power source of 1.8 V typically. This is anacceptable method for ramping the V(VDDIO) and V(VDD_n) supplies. The main constraint here is that the V(VDD_n)supply does not lead in ramping before the V(VDDIO) system supply. This is noted in Figure 28 with therequirement of t1 ≥ 0. V(VDDIO) must reach the expected operating voltage earlier than V(VDD_n) or at the sametime.

Figure 28. Suggested Power-Up Sequencing



http://www.ti.com/cn/lit/pdf/SNLA224


DOUT-

DOUT+

SER

RIN-

RIN+

DES

50Q 50Q


DOUT-

DOUT+

SER

RIN-

RIN+

DES

36



Application Information (continued)Table 8. Power-Up Sequencing Constraints for DS90UB933-Q1

SYMBOL DESCRIPTION TEST CONDITIONS MIN TYP MAX Units

t0 V(VDDIO) rise time 10% to 90% of nominal voltage on risingedge. Monotonic signal ramp is required 0.05 5 ms

t1 V(VDDIO) to V(VDD_n) delay 10% of rising edge (V(VDDIO)) to 10% ofrising edge (V(VDD_n))

0 ms

t2 V(VDD_n) rise time10% to 90% of nominal voltage on risingedge. Monotonic signal ramp is required.

VPDB < 10% of V(VDDIO)

0.05 5 ms

t3 PDB to GPO2 delay 90% of rising edge (PDB) to 10% ofrising edge (GPO2) 1.3 ms

8.1.3 AC CouplingThe SER/DES supports only AC-coupled interconnects through an integrated DC-balanced decoding scheme.External AC-coupling capacitors must be placed in series in the FPD-Link III signal path as shown in Figure 29.For applications utilizing single-ended 50-Ω coaxial cable, the unused data pin (DOUT–, RIN–) must utilize a0.047-µF capacitor and must be terminated with a 50-Ω resistor. For high-speed FPD–Link III transmissions, thesmallest available package should be used for the AC-coupling capacitor. This helps minimize degradation ofsignal quality due to package parasitics.

Figure 29. AC-Coupled Connection (STP)

Figure 30. AC-Coupled Connection (Coaxial)

8.1.4 Transmission MediaThe DS90UB933/934/964 chipset is intended to be used in a point-to-point configuration through a shieldedcoaxial cable. The serializer and deserializer provide internal termination to minimize impedance discontinuities.The interconnect (cable and connectors) must have a differential impedance of 100 Ω, or a single-endedimpedance of 50 Ω. The maximum length of cable that can be used is dependent on the quality of the cable(gauge, impedance), connector, board(discontinuities, power plane), the electrical environment (for example,power stability, ground noise, input clock jitter, PCLK frequency, etc.). The resulting signal quality at the receivingend of the transmission media may be assessed by monitoring the differential eye opening of the serial datastream. A differential probe should be used to measure across the termination resistor at the CMLOUTP/N pins.

Contact TI for a channel specification regarding cable loss parameters and further details on adaptive equalizerloss compensation.



DIN0

DIN1

DIN2

DIN3

DIN4

DIN5

DIN6

DIN7

DIN8

DIN9

DIN10

DIN11

HS

VS

PCLK

PDB

DOUT+

DOUT-

VDDCML

DAP (GND)

VDDPLL

VDDT

1.8 VDS90UB933-Q1

C4

C5 C10

C11

C1

C2

NOTE:C1 = 0.1 µF (50 WV)C2 = 0.047 µF (50 WV)C3:C7 = 0.01 µFC8:C12 = 0.1 µFC13, C14 = 4.7 µFC15 = 22 µFC16 - C17 = >100 pFC18 = 1 µFRTERM = 50 RPU = 1 k to 4.7 kRPD minimum =40 kR1, R2 (see MODE Setting Table)R3, R4 (see ID[x] Setting Table)FB1:FB4: Impedance = 1 k (@ 100 MHz) low DC resistance (<1 )

The "Optional" components shown are provisions to provide higher system noise immunity and will therefore result in higher performance.

LVCMOS

Parallel

Bus

Serial

FPD-Link III

Interface

MODE

ID[X]

VDDIO

RES

C8VDDIO

1.8 V

R4

R3

C13C3

FB1

FB2

VDDD

C7

SCL

VDDIO

C17

RPU

C16

RPU

SDA

I2C

Bus

Interface

FB3

FB4

GPO[1]

GPO[0]GPO

Control

Interface

C6

Optional

Optional

GPO[3]

GPO[2]

C9

1.8 V

C12

1.8 V

C15

C14

1.8 V

1.8 V

R2

R1RTERM

VDDIO

10 kQ

C18


RPD

37



8.2 Typical Applications

8.2.1 Coax Application

Figure 31. Coax Application Connection Diagram

8.2.1.1 Design RequirementsFor the typical coax design applications, use the following as input parameters:

Table 9. Coax Design ParametersDESIGN PARAMETER EXAMPLE VALUE

V(VDDIO) 1.8 V, 2.8 V, or 3.3 VV(VDD_n) 1.8 V

AC-coupling capacitors for DOUT± 0.1 µF, 0.047 µF (For the unused data pin, DOUT– )PCLK frequency 100 MHz (12-bit), 100 MHz (10-bit)



CM

L S

eria

lize

r D

ata

Th

rou

gh

pu

t

(80

mV

/DIV

)

Time (250 ps/DIV)

CM

L S

eria

lize

r D

ata

Th

rou

gh

pu

t

(80

mV

/DIV

)

Time (250 ps/DIV)

FPD-Link III

Bi-DirectionalControl Channel

Image Sensor

ECU Module

DIN[11:0] or

DIN[9:0]

HSYNC,

VSYNC

SDA

SCL

DOUT- RIN-

DOUT+ RIN+

Camera Unit

10 or 12

DATA

HSYNC

VSYNC

PCLKPixel Clock

SDA

SCL

Microcontroller

ROUT[11:0]

or

ROUT[9:0]

HSYNC, VSYNC

SDA

SCL

PCLK

10 or 12

DATA

HSYNC

VSYNC

Pixel Clock

SDA

SCL

Camera Data

DS90UB934-Q1Deserializer

DS90UB933-Q1Serializer

GPO[3:0]GPO[3:0]

4

GPIO[3:0]

4GPIO[3:0]

Camera Data

50Q 50Q


38



8.2.1.2 Detailed Design ProcedureFigure 32 shows the typical connection of a DS90UB933-Q1 serializer using a coax interface.

Figure 32. Coax Application Block Diagram

8.2.1.3 Application Curves

Figure 33. Coax Eye Diagram at 1.4-Gbps Line Rate (100-MHz Pixel Clock, 10-bit Mode) from Serializer Output

(DOUT+)

Figure 34. Coax Eye Diagram at 1.87-Gbps Line Rate (100-MHz Pixel Clock, 12-bit Mode) from Serializer Output

(DOUT+)



DIN0

DIN1

DIN2

DIN3

DIN4

DIN5

DIN6

DIN7

DIN8

DIN9

DIN10

DIN11

HS

VS

PCLK

PDB

DOUT+

DOUT-

VDDCML

DAP (GND)

VDDPLL

VDDT

1.8 VDS90UB933-Q1

C4

C5 C10

C11

C1

C2

NOTE:C1, C2 = 0.1 µF (50 WV)C3:C7 = 0.01 µFC8:C12 = 0.1 µFC13, C14 = 4.7 µFC15 = 22 µFC16 - C17 = >100 pFC18 = 1 µFRPU = 1 k to 4.7 kRPD minimum =40 kR1, R2 (see MODE Setting Table)R3, R4 (see ID[x] Setting Table)FB1:FB4: Impedance = 1 k (@ 100 MHz) low DC resistance (<1 )

The "Optional" components shown are provisions to provide higher system noise immunity and will therefore result in higher performance.

LVCMOS

Parallel

Bus

Serial

FPD-Link III

Interface

MODE

ID[X]

VDDIO

RES

C8VDDIO

1.8 V

R4

R3

C13C3

FB1

FB2

VDDD

C7

SCL

VDDIO

C17

RPU

C16

RPU

SDA

I2C

Bus

Interface

FB3

FB4

GPO[1]

GPO[0]GPO

Control

Interface

C6

Optional

Optional

GPO[3]

GPO[2]

C9

1.8 V

C12

1.8 V

C15

C14

1.8 V

1.8 V

R2

R1VDDIO

10 kQ

C18


RPD

39



8.2.2 STP Application

Figure 35. STP Application Connection Diagram

8.2.2.1 Design RequirementsFor the typical STP design applications, use the following as input parameters:

Table 10. STP Design ParametersDESIGN PARAMETER EXAMPLE VALUE

V(VDDIO) 1.8 V, 2.8 V, or 3.3 VV(VDD_n) 1.8 V

AC-coupling capacitors for DOUT± 0.1 µFPCLK frequency 100 MHz (12-bit), 100 MHz (10-bit)



FPD-Link III

Bi-Directional

Control Channel

Image Sensor

ECU Module

DIN[11:0] or

DIN[9:0]HSYNC,

VSYNC

SDA

SCL

DOUT- RIN-

DOUT+ RIN+

Camera Unit

10 or 12

DATA

HSYNC

VSYNC

PCLKPixel Clock

SDA

SCL

Microcontroller

ROUT[11:0]

or

ROUT[9:0] HSYNC,

VSYNC

SDA

SCL

PCLK

10 or 12

DATA

HSYNC

VSYNC

Pixel Clock

SDA

SCL

Camera Data

DS90UB934-Q1Deserializer

DS90UB933-Q1Serializer

GPO[3:0]GPO[3:0]

4

GPIO[3:0]

4GPIO[3:0]

Camera Data


40



8.2.2.2 Detailed Design ProcedureFigure 36 shows a typical connection of a DS90UB933-Q1 Serializer using an STP interface.

Figure 36. STP Application Block Diagram

Eye diagrams in STP applications have roughly double the swing as with coax (Figure 33 and Figure 34).

9 Power Supply RecommendationsThis device is designed to operate from an input core voltage supply of 1.8 V. Some devices provide separatepower and ground terminals for different portions of the circuit. This is done to isolate switching noise effectsbetween different sections of the circuit. Separate planes on the PCB are typically not required. Pin descriptiontables typically provide guidance on which circuit blocks are connected to which power terminal pairs. In somecases, an external filter may be used to provide clean power to sensitive circuits such as PLLs. The voltageapplied on V(VDDIO) (1.8 V, 2.8 V, 3.3 V) or other power supplies making up V(VDD_n) (1.8 V) must be at the inputpin - any board level DC drop must be compensated (that is, ferrite beads in the path of the power supply rails).



41



10 Layout

10.1 Layout GuidelinesDesign circuit board layout and stack-up for the serializer/deserializer devices to provide low-noise power feed tothe device. Good layout practice also separates high frequency or high-level inputs and outputs to minimizeunwanted stray noise pickup, feedback and interference. Power system performance may be greatly improved byusing thin dielectrics (2 to 4 mils) for power / ground sandwiches. This arrangement provides plane capacitancefor the PCB power system with low-inductance parasitics, which has proven especially effective at highfrequencies, making the value and placement of external bypass capacitors less critical. External bypasscapacitors should include both RF ceramic and tantalum electrolytic types. RF capacitors may use values in therange of 0.01 µF to 0.1 µF. Tantalum capacitors may be in the 2.2-µF to 10-µF range. Voltage rating of thetantalum capacitors should be at least 5× the power supply voltage being used.

TI recommends surface mount capacitors due to their smaller parasitics. When using multiple capacitors persupply pin, locate the smaller value closer to the pin. A large bulk capacitor is recommend at the point of powerentry. This is typically in the 50-µF to 100-µF range and smooths low frequency switching noise. TI recommendsconnecting power and ground pins directly to the power and ground planes with bypass capacitors connected tothe plane with via on both ends of the capacitor. Connecting power or ground pins to an external bypasscapacitor increases the inductance of the path.

A small body size X7R chip capacitor, such as 0603, is recommended for external bypass. Its small body sizereduces the parasitic inductance of the capacitor. The user must pay attention to the resonance frequency ofthese external bypass capacitors, usually in the range of 20 to 30 MHz. To provide effective bypassing, multiplecapacitors are often used to achieve low impedance between the supply rails over the frequency of interest. Athigh frequency, it is also a common practice to use two vias from power and ground pins to the planes, reducingthe impedance at high frequency.

Some devices provide separate power for different portions of the circuit. This is done to isolate switching noiseeffects between different sections of the circuit. Separate planes on the PCB are typically not required. PinDescription tables typically provide guidance on which circuit blocks are connected to which power pin pairs. Insome cases, an external filter many be used to provide clean power to sensitive circuits such as PLLs.

Use at least a four-layer board with a power and ground plane. Locate LVCMOS signals away from thedifferential lines to prevent coupling from the LVCMOS lines to the differential lines. Closely-coupled differentiallines of 100 Ω are typically recommended for differential interconnect. The closely coupled lines help to ensurethat coupled noise appears as common-mode and thus is rejected by the receivers. The tightly coupled lines alsoradiate less.

Information on the WQFN package is provided in AN-1187 Leadless Leadframe Package (LLP) (SNOA401).

10.1.1 Interconnect GuidelinesSee Application Note 1108 Channel-Link PCB and Interconnect Design-In Guidelines (SNLA008) for full details.• Use 100-Ω coupled differential pairs• Use the S/2S/3S rule in spacings

– – S = space between the pair– – 2S = space between pairs– – 3S = space to LVCMOS signal

• Minimize the number of Vias• Use differential connectors when operating above 500-Mbps line speed• Maintain balance of the traces• Minimize skew within the pair

Additional general guidance can be found in the LVDS Owner’s Manual - available in PDF format from the TexasInstrument web site at: www.ti.com/lvds.



http://www.ti.com/cn/lit/pdf/SNOA401


http://www.ti.com/lvds

Buried FPD-Link III

High-speed Trace

on Signal Layer 1

AC-Coupling

Capacitor on

Top Layer

42



10.2 Layout ExampleStencil parameters such as aperture area ratio and the fabrication process have a significant impact on pastedeposition. Inspection of the stencil prior to placement of the WQFN package is highly recommended to improveboard assembly yields. If the via and aperture openings are not carefully monitored, the solder may flowunevenly through the DAP. Stencil parameters for aperture opening and via locations are shown in the following:

Figure 37. No Pullback WQFN, Single Row Reference Diagram

Table 11. No Pullback WQFN Stencil Aperture Summary for DS90UB933-Q1

DEVICE PINCOUNT MKT DWG PCB I/O PAD

SIZE (mm)PCB

PITCH(mm)

PCB DAPSIZE(mm)

STENCIL I/OAPERTURE

(mm)

STENCILDAP

APERTURE(mm)

NUMBER OFDAP

APERTUREOPENINGS

GAPBETWEEN

DAPAPERTURE(Dim A mm)

DS90UB933-Q1 32 RTV 0.25 × 0.6 0.5 3.1 × 3.1 0.25 × 0.7 1.4 × 1.4 4 0.2

Figure 38. DS90UB933-Q1 Serializer DOUT+ Trace Layout



Power-over-Coax

Network Placed

Close to Connector

Coax Connector

43



Figure 39. DS90UB933-Q1 Power-over-Coax Layout

Figure 38 and Figure 39 are derived from the layout design of the DS90UB933-Q1 evaluation module (EVM).The EVM is designed for coax operation. The trace carrying high-speed serial signal DOUT+ is critical and mustbe kept as short as possible. Burying this trace in an internal PCB layer may help reduce emissions. If Power-over-Coax is used, the stub must be minimized by placing the filter network as close as possible to the coaxconnector. These graphics and additional layout description are used to demonstrate both proper routing andproper solder techniques when designing in this serializer.



44



11 器器件件和和文文档档支支持持

11.1 文文档档支支持持

11.1.1 相相关关文文档档

请参阅如下相关文档：

• 《通过具有双向控制通道的 DS90UB913/4 FPD-Link III 进行 I2C 通信》 (SNLA222)• 《在 DS90UB913A 设计中进行同轴电缆供电》 (SNOA549)• FPD-Link 学习中心

• 《理解 I2C 总线》

• 《I2C 总线上拉电阻计算》

• 应用报告《焊接规范，

• 应用报告《IC 封装热指标》，

• 应用报告《AN-1187 无引线框架封装 (LLP)》• LVDS 用户手册

• 《一种适用于 FPD-Link III SerDes 的 EMC/EMI 系统设计和测试方法》

• 《按照车用 EMC/EMI 要求进行成功设计的 10 个技巧》

11.2 接接收收文文档档更更新新通通知知

要接收文档更新通知，请导航至 ti.com. 上的器件产品文件夹。单击右上角的通知我进行注册，即可每周接收产品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.3 社社区区资资源源

TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straightfrom the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and donot necessarily reflect TI's views; see TI's Terms of Use.

11.4 商商标标

E2E is a trademark of Texas Instruments.All other trademarks are the property of their respective owners.

11.5 静静电电放放电电警警告告

这些装置包含有限的内置 ESD 保护。存储或装卸时，应将导线一起截短或将装置放置于导电泡棉中，以防止 MOS 门极遭受静电损伤。

11.6 GlossarySLYZ022 — TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 机机械械、、封封装装和和可可订订购购信信息息

以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且不会对此文档进行修订。如需获取此数据表的浏览器版本，请查阅左侧的导航栏。





https://training.ti.com/fpd-link-learning-center




http://www.ti.com/cn/lit/pdf/SPRA953



http://www.ti.com/cn/lit/pdf/SLYT719

http://www.ti.com/cn/lit/pdf/SLYT636

http://e2e.ti.com

http://www.ti.com/corp/docs/legal/termsofuse.shtml

http://www.ti.com/cn/lit/pdf/SLYZ022

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

DS90UB933TRTVRQ1 ACTIVE WQFN RTV 32 2500 RoHS & Green SN Level-3-260C-168 HR -40 to 105 UB933Q

DS90UB933TRTVTQ1 ACTIVE WQFN RTV 32 250 RoHS & Green SN Level-3-260C-168 HR -40 to 105 UB933Q

(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

http://www.ti.com/product/DS90UB933-Q1?CMP=conv-poasamples#samplebuy

http://www.ti.com/product/DS90UB933-Q1?CMP=conv-poasamples#samplebuy

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

DS90UB933TRTVRQ1 WQFN RTV 32 2500 330.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1

DS90UB933TRTVTQ1 WQFN RTV 32 250 178.0 12.4 5.3 5.3 1.3 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 30-Oct-2021

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

DS90UB933TRTVRQ1 WQFN RTV 32 2500 853.0 449.0 35.0

DS90UB933TRTVTQ1 WQFN RTV 32 250 208.0 191.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 30-Oct-2021

Pack Materials-Page 2

www.ti.com

PACKAGE OUTLINE

C

5.154.85

5.154.85

0.80.7

0.050.00

2X 3.5

28X 0.5

2X 3.5

32X 0.50.3

32X 0.300.18

3.1 0.1

(0.1) TYP

WQFN - 0.8 mm max heightRTV0032APLASTIC QUAD FLATPACK - NO LEAD

4224386/B 04/2019

0.08 C

0.1 C A B0.05

NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.

PIN 1 INDEX AREA

SEATING PLANE

PIN 1 ID

SYMMEXPOSEDTHERMAL PAD

SYMM

1

8

9 16

17

24

2532

33

SCALE 2.500

AB

www.ti.com

EXAMPLE BOARD LAYOUT

28X (0.5)

(1.3)

(1.3)

(R0.05) TYP

0.07 MAXALL AROUND

0.07 MINALL AROUND

32X (0.6)

32X (0.24)

(4.8)

(4.8)

(3.1)

(3.1)

( 0.2) TYPVIA


4224386/B 04/2019

NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271).5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown on this view. It is recommended that vias under paste be filled, plugged or tented.

SYMM

SYMM

SEE SOLDER MASKDETAIL

LAND PATTERN EXAMPLEEXPOSED METAL SHOWN

SCALE: 15X

1

8

9 16

17

24

2532

33

METAL EDGE

SOLDER MASKOPENING

EXPOSED METAL

METAL UNDERSOLDER MASK

SOLDER MASKOPENING

EXPOSEDMETAL

NON SOLDER MASKDEFINED

(PREFERRED)SOLDER MASK DEFINED

SOLDER MASK DETAILS

www.ti.com

EXAMPLE STENCIL DESIGN

32X (0.6)

32X (0.24)

28X (0.5)

(4.8)

(4.8)

(0.775) TYP

(0.775) TYP

4X (1.35)

4X (1.35)

(R0.05) TYP


4224386/B 04/2019

NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

SOLDER PASTE EXAMPLEBASED ON 0.125 MM THICK STENCIL

SCALE: 20X

EXPOSED PAD 3376% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SYMM

SYMM

1

8

9 16

17

24

2532

33

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