dsd vhdl ch4

7/31/2019 Dsd Vhdl Ch4

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Ch. 4 Design of Arithmetic

Operations

1 . Se rial Adde r

2 . Mult iplie r - s ig ne d, u ns ig ne d

3 . Divide r - s igne d, uns igne d

2

Serial Adder with Accumulator

( 0 )( 1)001111100T 4

01111101000T 3

11111010001T 2

10110110010T 1

10001110101T 0

Ci+ 1Sum iCiYX

x


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Control Circuit input: N, Clock

output: Sh

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State Graphs for Control Networks

Notation of Mealy Machine

Input/Output

XiXj/ZpZq : Xi= 1 , Xj= 1 , Zp= 1 , Zq= 1

Ex) input ( X1 , X2 , X3 , X4) , Output ( Z1 , Z2 , Z3 , Z4)

X1X4/Z2Z3 : 10/0110

State Sk input labe l constraints

1. S k input label Ii, Ij , IiIj= 0 if ij

2 . N- input la be l I1+ I2+ + In = 1


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5

Examples

Good!

Bad!

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4.3 Unsigned Multiplication

Produc t


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7

Design of a Binary Multiplier

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Multiplication

add and shift operation Produc t Mplie r

Mcand


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State Graph for Multiplier Control input: M, St

output : Load, Sh, Ad, Done

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VHDL for 4x4 Multiplier

- - This is a behavioral model of a mult ip lier for unsigned binarynumbers. It multiplies a

- - 4 - b it mult ip licand by a 4 - b it mult ip lie r to g ive an 8 - b it p roduc t.

- - The maximum number of c lock cycles nee ded for a mult ip ly is 10.

library BITLIB;

us e BITLIB.bit_pack.all;

entity mult4X4 is

port (Clk, St: in bit;

Mplier,Mcand : in bit_vector(3 downto 0 ) ;

Done: ou t bit);

e nd mult4X4;

architecture behave1 of mult4X4 is

signal State: integer range 0 to 9;

signal ACC: bit_vect or( 8 downto 0 ) ; - - a cc um ula tor

alias M: bit is A CC( 0 ) ; - - M is b it 0 of A CC

begin


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process

begin

wait until Clk = ' 1' ; - - e x e c ut e s on r is ing e d ge of

clock

case State is

when 0 = > - - init ia l S ta te

if St= '1 ' then

ACC(8 downto 4)


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13

General Case: NxN-bits Multiplier Multiplier contr ol with Counte r

inp ut: M, S t

output: Loa d,

Sh, Ad, Done

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Operation with Counter


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4-bit Multiplier Partial Products

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4 x 4 Array Multiplier

total delay- >8tad+t g

n2 AND, n(n- 2) FA

n HA are needed!


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4.4 Multiplication of Signed Binary Numbers1. Complement the multiplier if negative

2. Complement the m ultiplicand if negative

3. Multiply the two positive binary number s

4. Complement the product if it should be negative

Multiplication of the Signed fr act ional Binar y

numbers

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Signed Fractional Binary Numbers

2 s Compleme nt Signed binary fraction

(Sign b it + f ract ion)

Ex) Sign bit + three fractional bits

0 .1 01 b = 2 ^( - 1 ) + 2 ^( - 3 ) = + 5 /8

1 .0 11 b = - ( 0.1 00 + 0 .0 01 ) = - ( 0 .1 01 ) = - 5/ 8 - - 2

Or

1.011 b = - 2^0 + 2 ^( - 2 ) + 2 ^( - 3) = - 1+ 3/8 = - 5 /81 .000 b = - 2^0 = - 1 ( smalles t nega t ive va lue)

0 .1 11 b = 2 ^( - 1 ) + 2 ^( - 2 ) + 2 ^( - 3 ) = + 7 /8 ( la rge s t

positive value)


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Multiplication of Signed Binary Numbersi) (+) x (+)

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ii) (- ) x (+)


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iii) (+) x (- ) =1.g = - 1 + 0.g

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iv) (- ) x (- )


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Multiplication of Signed Binary Numbers 2 s complement multiplier

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Control of 2s complement multiplier

inputs : St, M

outputs: Load, Sh, Ad

Done, Cm


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Faster Multiplier

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Control of Fast Multiplier


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2

s complement

library BITLIB;

use BITLIB.bit_pack.all;

entity mult2C is

port (CLK, St: in bit;

Mplier,Mcand : in bit_vector(3 downto 0);

Product: out bit_vector (6 downto 0);

Done: out bit);

end mult2C;

architecturebehave1 of mult2C is

signal State : integer range 0 to 5;

signal A, B: bit_vector(3 downto 0);

alias M: bit is B(0);

begin

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process

variable addout: bit_vector ( 4 downto 0) ;

begin

wait until CLK = '1 ' ;

case State is

when 0 = > - - initial S tat eif S t= ' 1' then

A


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when 1 | 2 | 3 = > - - "add/ shift " Sta te

if M = '1' then

a ddout := a dd4 ( A,Mc and,'0 ') ; - - Add- - mult ip licand to A and sh if t

A


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Command File and Simulation Results for

(+5/8 by -3/8)

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Test Bench for Signed Multiplier

library BITLIB;

us e BITLIB.bit_pac k.all;

entity testmult is end testmult;

architecture t e s t1 of testmult is

component mult2C


Mplier,Mcand : in bit_vector(3 downto 0 ) ;

Product: ou t b it_vec tor (6 downto 0) ;

Done: ou t bit);end component;

constant N: in teger := 11; type ar r is array ( 1 to N) of bit_vector(3 downto0 ) ;

constant Mcandarr : arr :=("0111", "1101", "0101", "1101", "0111", "1000", "0111",

"1000", "0000", "1111", "1011");

constant Mplierarr : arr :=("0101", "0101", "1101", "1101", "0111", "0111", "1000",

"1000", "1101", "1111", "0000");

signal CLK, St, Done: bit; signal Mplier, Mcand: bit_vec tor( 3 downto 0) ;

signal Product: bit_vector( 6 downto 0) ;


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begin

CLK


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[revised] Model for 2s Complement

Multiplierlibrary BITLIB;


entity mult2Cs is


Mplier ,Mcand : in bit_vector(3 downto 0) ;

Product: ou t b it_vec tor (6 downto 0) ; Done: ou t bit);

e nd mult2Cs;

architecture behave2 of mult2Cs is

signal State, Nextst ate: integer range 0 to 5; signal A, B:

bit_vector(3 downto 0) ;

signal AdSh, Sh, Load, Cm: bit; signal addout: bit_vect or( 4

downto 0) ;

alias M: bit is B(0) ;

begin

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process (state, st , M)

begin

Load


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end process ;

addout


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Model for 2

s Complement Multiplier- - This model of a 4- b it mult ip lier for 2 ' s complement numbers

- - implements the contro ller us ing a counter and logic equat ions .

library BITLIB;


entity mult2CEQ is

port(CLK, St: in bit;

Mplier,Mcand: in bit_vector(3 downto 0) ;

Product: ou t bit_vector(6 downto 0 ) ) ;

e nd mult2CEQ;

architecture m2ceq of mult2CEQ is

signal A, B, Q, Comp: bit_vect or( 3 downto 0) ;

signal addout: bit_vect or( 4 downto 0) ;

signal AdSh, Sh, Load, Cm, Done, Ld1, CLR1, P1 : bit;

Signal One: bit:= '1';

Signal Din: bit_vector(3 downto 0) := "0100 ";

alias M: bit is B(0) ;

begin

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Count1: C74163 port map ( Ld1, CLR1, P1, One, CLK, Din, open ,Q) ;

P1


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if AdS h = ' 1' then - - Add mult ip licand to A and sh if t

A


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Design of a Parallel Binary Divider F ig. 4 - 1 9

44


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Overflow

quotient of greate r t han 15

inspect dividend and divisor

Ex) 135/7= 19.2857.. ..

Over flow condition

X8X7X6X5X4Y3Y2Y1Y0

can subtract but,

quotient bit of 1 will

destroy LSB of

dividend

overflow!

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Review

F ig. 4 - 1 9

Su=1: subtract signal, and set the quotient bit to 1

Su=0: can not subtract

C=0: divisor is greater than the 4 leftmost dividend bits,

thus, subtract can not occur


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Unsigned Divider Control

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Control Signals for Signed Divider

LdULoad upper half of dividend from bus

LdL Load lower half of dividend from bus

Lds Load sign of dividend into s ign flip- flop

S Sign of dividend

Cm 1 Complement dividend register (2 's

complement) LddLoad divisor from bus

S u Enable adder output onto bus ( Ena) and load

upper half of dividend from bus


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Cm 2 Enable compleme nter (Cm2 equals the complement of

the s ign bit of the divisor ,

so that a positive divisor is complemented and a negative

divisor is not)

S h Shift the dividend register left one place and increment

the counter

CCarry output from adder ( If C = 1, the divis or can be

subtract ed from the upper

dividend.)

S t Star t

V Overflow

Qneg Quotient will be negative (Qneg = 1 when s ign of

dividend and divisor are

different)

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Signed Divider

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Signed Divider


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Control

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VHDL Model of 32-bit Signed Divider

library BITLIB;

use BITLIB.bit_pack.all;

entity sdiv is

port(Clk,St: in bit;

Dbus: in bit_vector(15 downto 0) ; Quotient: ou t bit_vector(15downto 0) ;

V, Rdy: ou t bit);

end sdiv;

architecture Signdiv of Sdiv is

constant zero_vector: bit_vector(31 downto 0 ) := ( others = >'0 ' ) ;

signal State: integer range 0 to 6; signal Count : intege r range 0 to15;

signal Sign,C,NC: bit; signal Divisor,Sum,Compout: bit_vector(15downto 0) ;

signal Dividend: bit_vector(31 downto 0) ;

alias Q: bit_vector( 15 downto 0) is Dividend(15 downto 0) ;

alias Acc: bit_vector(15 downto 0) is Dividend(31 downto 16) ;


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begin - - c onc ur r ent s t at e me nt s

compout


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when 5 = >

if C = '1 ' t hen - - C

ACC


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constant dividendarr : arr1 :=(X"0000006F",X"07FF00BB",X"FFFFFE08",

X"FF80030A",X"3FFF8000",X"3FFF7FFF",X"C0008000",X"C0008000",

X"C0008001",X"00000000",X"FFFFFFFF",X"FFFFFFFF");

constant divis orar r: ar r2 := ( X"000 7", X"E005 ",X"001E", X"EFFA", X"7FFF", X"7FFF", X"7FFF",

X"8000", X"7FFF", X"0001", X"7FFF", X"0000");

signal CLK, St, V, Rdy: bit; signal Dbus , Quotient ,divisor : bit_vector ( 15 downto 0) ;

signal Dividend: bit_vector(31 downto 0) ; signalcount: intege r range 0 to N;

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begin

CLK


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Simulation Result of Signed Divider - - Command file to tes t results of s igned divider

lis t - hex - Notr igger dividend divisor Quotient V - T rigger count

run 5300

ns delta dividend divisor quotient v count

0 + 0 0 0 00 0 00 0 0 00 0 0 00 0 0 0

470 + 3 0000006F 0007 000F 0 1

910 + 3 07FF00BB E005 BFFE 0 2

1330 + 3 FFFFFE08 001E FFF0 0 3

1910 + 3 FF80030A EFFA 07FC 0 4

2010 + 3 3FFF8000 7FFF 0000 1 5

2710 + 3 3FFF7FFF 7FFF 7FFF 0 6

2810 + 3 C0008000 7FFF 0000 1 7 3510 + 3 C0008000 8000 7FFF 0 8

4210 + 3 C0008001 7FFF 8001 0 9

4610 + 3 00000000 0001 0000 0 A

5010 + 3 FFFFFFFF 7FFF 0000 0 B

5110 + 3 FFFFFFFF 0000 0002 1 C

dsd vhdl ch4

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