EDA 實作Verilog Tutorial

國研院國家晶片系統設計中心July 2005

陳正斌

Traditional VLSI Design Flow

Traditional VLSI Design Flow

EDA

• Electronic Design Automation (EDA)

• Computer-Aided Design (CAD)

Hardware Description Language

• A hardware description language (HDL) is a high-level programming language with special constructs used to model the function of hardware logic circuits.

• The special language constructs can:– Describe the connectivity of the circuit

– Describe the functionality of the circuit

– Describe the timing of a circuit

Verilog

• Verilog is a Hardware Description Language.

• Verilog models digital circuits.

• Verilog lets you develop tests to verify the functionality of the circuits you model.

Verilog Module

module DFF

endmodule

module ALU

endmodule

module cache

endmodule

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Module Ports

module DFF (d, clk,q,qb); input d, clk; output q, qb;

endmodule

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Q

QSET

CLR

Dd

clk

q

qb

Module Instances

module REG4 (d, clk,q,qb); input [3:0] d; input clk; output [3:0] q, qb;

DFF d0 (d[0], clk, q[0], qb[0]); DFF d1 (d[1], clk, q[1], qb[1]); DFF d0 (d[2], clk, q[2], qb[2]); DFF d0 (d[3], clk, q[3], qb[3]);

endmodule

d clk

q qb

Q

QSET

CLR

S

R Q

QSET

CLR

S

R Q

QSET

CLR

S

R Q

QSET

CLR

S

R

d0 d1 d2 d3

4

4 4

module DFF (d, clk,q,qb);………………….endmodule

A Simple and Complete Example

Stimulus and

Control

Response Generation

and Verification

Sample Design – Full Adder

xin yin cin cout sum0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

Full Adder – Boolean Algebra

• cout = xinyincin’+ xinyincin+xin’yincin+xinyin’cin

= xinyin+cin(xin’yin+xinyin’) = xinyin + cin(xin y⊕ in)

• sum = xin’yin’cin+ xin’yincin’+xinyin’cin’+xinyincin

= (xin’yin+xinyin’)cin’ + (xin’yin’+xinyin) cin = (xin ⊕ yin ) c⊕ in

Full Adder – Schematic

xin

yin

cin

cout

p1

p2

p3

xin

yin

cin

sum

Full Adder – Verilog Model

module COUT(cout, xin, yin, cin);

input xin;input yin;input cin;output cout;wire xin, yin, cin, out;wire p1, p2, p3;

and (p1, xin, yin);xor (p2, xin, yin);and (p3, p2, cin);or (cout, p1, p3);

endmodule

module SUM(sum, xin, yin, cin);

input xin;input yin;input cin;output sum;

xor (sum, xin, yin, cin);

endmodule

Full Adder -- Schematic

Xi

Yi

Ci

Cii

Si

Full Adder -- Schematic

Xi

Yi

Ci

Cii

Si

COUT

xinyincin

cout

SUM

xinyincin

sum

Full Adder – Verilog Model

module FA(Cii,Si,Xi,Yi,Ci);

input Xi;input Yi;input Ci;output Cii;output Si;

SUM inst0 (.sum(Si), .xin(Xi), .yin(Yi), .cin(Ci));COUT inst1 (.cout(Cii), .xin(Xi), .yin(Yi), .cin(Ci));

endmodule

Test Bench -- Template

module FA_test; //Signal declaration

//Instantiate modules

//Apply stimulus

//Display results

endmodule

Test Bench --Instance

module FA_test; //Signal declaration

//Instantiate modules FA inst0 (Cii,Si,Xi,Yi,Ci); //Apply stimulus

//Display results

endmodule

Test Bench -- Stimulus

module FA_test;// Signal declaration reg Xi, Yi, Ci;// Instantiate modulesFA inst0 (Cii,Si,Xi,Yi,Ci);// Apply Stimulusinitialbegin #0 Xi = 0; Yi = 0; Ci = 0; #10 Xi = 0; Yi = 0; Ci = 1; #10 Xi = 0; Yi = 1; Ci = 0; #10 Xi = 0; Yi = 1; Ci = 1; #10 $finish;end//Display results

endmodule

Time Values

Xi Yi Ci

0 0 0 0

10 0 0 1

20 0 1 0

30 0 1 1

Test Bench – Display Result

module FA_test;// Signal declaration reg Xi, Yi, Ci;// Instantiate modulesFA inst0 (Cii,Si,Xi,Yi,Ci);// Apply Stimulusinitialbegin #10 Xi = 0; Yi = 0; Ci = 0; #10 Xi = 0; Yi = 0; Ci = 1; #10 Xi = 0; Yi = 1; Ci = 0; #10 Xi = 0; Yi = 1; Ci = 1; #10 $finish;end//Display resultsinitial // print all changes to all signal values $monitor($time, " Xi = %b Yi = %b Ci = %b Ci+1 = %b Si = %b", Xi,Yi,Ci,Cii,Si);endmodule

Dump Waveform

initial

begin

$dumpfile(“file.vcd”);

$dumpvars(0,inst0);

end

Simulation

• unix> verilog FA_test.v FA.v COUT.v SUM.v

• unix> nWave &

Waveform

Quiz

• Design a 4 bit adder by instancing 4 full adder

coutcin co0FA

Ci

Xi Yi

Cii

Si

FACi

Xi Yi

Cii

Si

FACi

Xi Yi

Cii

Si

FACi

Xi Yi

Cii

Si

co1 co2

b[0] a[0] b[1] a[1] b[2] a[2] b[3] a[3]

sum[2] sum[3]sum[1]sum[0]

Edit ADDR4.v

module ADDR4(cout,sum,a,b,cin);

input cin;input [3:0] a;input [3:0] b;output [3:0] sum;output cout;

//Design Started Here!!!

endmodule

Apply Stimulus

• Edit ADDR4_test.v

// Apply Stimulusinitialbegin // ** Add stimulus here **

end

Apply Stimulus

Time Values

a b Cin

0 0 0 0

10 3 5 1

20 10 11 0

30 5 7 1

40 15 15 0

50 15 15 1

60 15 1 0

70 1 15 1

80 7 8 0

90 5 10 1

100 4 9 0

110 8 6 1

120 7 13 0

130 9 12 0

140 14 13 1