lesson verilog
TRANSCRIPT
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Introduction to CadenceOpus
Digital HDL design
Logic simulation
(NCVerilog / NCVHDL)
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Introduction
In the next few pages, you will become familiar with theNC-Verilog logic simulator interface.
The presentation that follows lets you experiment withthe simulation of the digital circuits.
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Overview
The Cadence NC-Verilogsimulator is a digital logicsimulator that combines the high-performance of native
compiled code simulation with the accuracy, flexibility, and
debugging capabilities of the event-driven simulation.
In a Verilog/VHDL configuration, both the Verilog and VHDL
compilers are used to generate code for the Verilog and VHDLportions of the design, respectively. During an elaboration
process (similar to the linking used in computer programming),
the Verilog and VHDL code segments are combined into asingle code stream. This single executable code is then directly
executed by the host processor (simulator).
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HDL simulation flow
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Short Verilog syntax summary
The basic structure of a Verilog description
`timescale ns/ps
module name(p1, p2, p3, ... pn);input p1, p2;input [msb1 : lsb1] p3;output p4, p5;
output [msb2 : lsb2] p6;...
...
Body of the module
...
...
endmodule
The basic unit of a Verilogdescription is the module,
delimited by the keywords
module and endmodule
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Department of Electron Devices, CAD Laboratory
Simple Verilog behavioral example
A simple example - RS Latch
`timescale 1ns/10ps
module rsl1(q, qn, preset, clear);output q, qn;input preset, clear;wire preset, clear;
reg q, qn;always @(preset or qn)
#1 q = !(qn && preset);
always @(clear or q)
#1 qn= !(q && clear);endmodule
In the body of the module the
input and output ports,registers, wires have to bedeclared
The identifiers of the registers
and wires can be used as
output and input ports of the
module, respectively
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Simple Verilog behavioral example
The simple example - RS Latch
`timescale 1ns/10ps
module rsl1(q, qn, preset, clear);output q, qn;input preset, clear;wire preset, clear;
reg q, qn;always @(preset or qn)
#1 q = !(qn && preset);
always @(clear or q)
#1 qn= !(q && clear);endmodule
The timescale determines theperiod of the time between two
steps for the simulator
always (condition)
#n what to do If there are any changes on the
input ports and the condition is true
then the procedure will be executedIn this example both alwaysprocedures have unit delay
(in this case 10ns)
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Simple Verilog RTL example
The simple example - RS LatchThe other possibility to
describe a structure is using
built-in generic gates
(RT level description)
wires have to be declared
as connecting elementsbetween the parts of the
model
In this example two nand
gates are defined having
unit delay
`timescale 1ns/10psmodule rsl2(q, qn, preset, clear);
output q, qn;input preset, clear;wire preset, clear;wire q, qn;
// declare two nand gates
// with unit delay
nand #1
g1(q, qn, preset),g2(qn, q, clear);
endmodule
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Department of Electron Devices, CAD Laboratory
Generating testbench
If the model of a circuit (or a function) has been constructed
then the next step is verifying it by simulation. For this
purpose a testbench is needed, which contains an instanceof the modeland provides the stimuli (input test signal
sequence).
The testbench forms the external world for the model to betested. The driving signals have to be generated here as well
as the outputs of the model have to be received and, if
necessary, processed.
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Department of Electron Devices, CAD Laboratory
Generating testbench
The simple example - RS Latch testbench
`timescale 1ns/10psmodule rslx_test;
wire q, qn;reg preset, clear;parameterd = 10;rsl1 latch(q, qn, preset, clear);
initialbegin
preset = 0; clear = 1;
#d preset = 1;
#d clear = 0;#d clear = 1;
endendmodule
Declaration part of two output
wires and two input variables(registers)
Create an instance of the
RS-Latch modul (instance call)
Initial procedure
initialbegin
runs only once
end
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Starting the Verilog GUI
Make a middle click at an
empty place of the screen andthe Engineering Tools popupwindow opens.
Make a left click on the
Simulators Verilog/VHDL
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Department of Electron Devices, CAD Laboratory
Starting the Verilog GUI
A new UNIX shell comes up andasks for the Verilog homedirectory, where the Verilog
source files will be stored
If this directory doesnt exist, it will
be created automatically (the
default name is NCHDL)
If you first run the Verilog tool
the program asks if you wantMultiple Step orSingle Stepprocedure. Choose Multiple Stepitem in that dialog box
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Starting the Verilog GUI
The multiple step process flow contains:
Compilation - it is analogous to that of computer programs.
Each module is taken one by one and translated into aninternal format (such as object files in computers)
Elaboration - it does some kind of linking the modules witheach other to form a single code stream per unit
Simulation of the elaborated objects
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Setting your environment
First determine the working
directory
In the menubar left clickFileSet Design Directory
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Budapest University of Technology & Economy
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Setting your environment
Click the Create cds.lib File
Click Save button
Select the 3rdcheckbox, and
press OK
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Setting your environment
The default Work Library nameautomatically appears, and in the
main window directory structures can
be seen:
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Generating HDL description
The next step is to start writing the Verilog source code(s)
First at all the text editor has to be selected
Select Edit Preferences
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Generating HDL description
The Editor Command can bechanged fortextedit %F
orgvim %F
Then press OK button
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Generating HDL description
Next, create a new directory forHDL sources
Enter the name of the directory
(e.g. sources) then press OK.
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Generating HDL description
The file name of the Verilog
source can be entered here
Click FileEdit New Filemenu item in the main window It shows the actual directory,
in most cases it is the recently
specified Veriloghome directory
The contents of the
directory are shown here
Change directory to sources
(double click at sources), thenspecify a Verilogfilename (e.g.:
alu.v) then click the Save button
and the text editor opens
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Generating HDL description
In the text editor the Verilog
source can be entered
To save the code right click
at File -> Save
When finished close thewindow
`timescale 1ns/10ps
module rsl1(q, qn, preset, clear);
output q, qn;input preset, clear;
wire preset, clear;
reg q, qn;
always @(preset or qn)
#1 q = !(qn && preset);
always @(clear or q)#1 qn= !(q && clear);
endmodule
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Compiling Verilog sources
To compile the sourcesclick on the VLOG icon
or
Select ToolsVerilogCompilermenu itemu
Compiling the Verilog
sources generates the
new modules in the
module window assubentries of worklib
El b ti th il d d l ( )
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Budapest University of Technology & Economy
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Elaborating the compiled module(s)
Select the highest
hierarchical level
module of the
testbench
CLICK on the
Elaborate button
or
Select theToolsElaboratormenu item
El b ti th il d d l ( )
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Elaborating the compiled module(s)
At the first elaboration selectthe ToolsElaboratormenuitem which invokes the
Elaborate dialog box
Check Access Visibility and
set it to All !!!
Then press OK button
Si l ti th d t
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Simulating the code stream
After elaboration theSnapshots folder has to
be opened in the
module panel
Select the snapshot of
your testbench and click
on the Simulate button
or
Select ToolsSimulatemenu item
Si l ti th d t
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Simulating the code stream
The ncsim simulator
windowopens
Left click SelectSignals in the menubar
In the source code all
selected signals
become highlighted
Simulating the code stream
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Simulating the code stream
Left click the
Waveform button
After a while the
waveform window
appears
Click the big play
button to run thesimulation
Simulating the code stream
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Simulating the code stream
Simulating the code stream
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Simulating the code stream
In the waveform window at the upper left corner of thewaveform pane there is a small red flag of the cursors. It can be
dragged by the left and the middle mouse button. In the narrow
pane between the signal list and the waveform the signalvalues can be read, at the simulation time indicated by the
cursorTimeA.
For a simple zoom facility hold down the right mouse button on
the waveform and a zoom menu appears
Simulating the code stream
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Department of Electron Devices, CAD Laboratory
Simulating the code stream
Displaying internal signalsBy clicking right of the
Subscopes box at the
small button with theblack triangle a
dropdown list appears
showing the internal
modules of thesimulated system
Selecting one of them
the actual source codetext appears in the
source code pane.
Simulating the code stream
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Budapest University of Technology & Economy
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Simulating the code stream
Displaying internal signals
If all the signals of
the internal module
are needed to
display, then they
can be selected byleft clicking at
Select->Signals
Case study I
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Case study I
Arithmetic Logic Unit (ALU)The core of a central processing unit, CPU; performs a setof arithmetic and logic micro operations.
Generate a behavioral Verilogdescription of an ALU.
ShifterMUX
Sel[4:0]
A[7:0]
B[7:0]
Carryin
Sel[1:0] Sel[2] Sel[4:3]
LogicUnit
Logic Unit [7:0]
Arith Unit [7:0]
ALU_noShift[7:0]
Case study I
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Case study I
Arithmetic Logic Unit (ALU)It has n encoded inputs for selecting the operation to be performedS4 S3 S2 S1 S0 Cin Operation Function Implementation block
0 0 0 0 0 0 Y
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Case study I
Arithmetic Logic Unit (ALU)First define the ports and registers:
`timescale 1ns/10psmoduleALU (Sel, CarryIn, A, B, Y);
input [4:0] Sel;input CarryIn;input [7:0] A, B;output [7:0] Y;
reg [7:0] Y;reg [7:0] LogicUnit, ArithUnit, ALU_NoShift;
always @(Sel or A or B or CarryIn)begin
the descriptions of different units come here
endendmodule
Case study I
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Case study I
Arithmetic Logic Unit (ALU) the operations:
Logic Unit Arithmetic Unit
case ({Sel[1:0]})2'b00 : LogicUnit = A & B;
2'b01 : LogicUnit = A | B;
2'b10 : LogicUnit = A ^ B;
2'b11 : LogicUnit = ~A;
default : LogicUnit = 8'bX;endcase
case ({Sel[1:0], CarryIn})3'b000 : ArithUnit = A;
3'b001 : ArithUnit = A + 1;
3'b010 : ArithUnit = A + B;
3'b011 : ArithUnit = A + B + 1;
3'b100 : ArithUnit = A + ~B;
3'b101 : ArithUnit = A - B;
3'b110 : ArithUnit = A - 1;
3'b111 : ArithUnit = A;default : ArithUnit = 8'bX;endcaseDo not forget to type { and } !!!
Case study I
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case study I
Arithmetic Logic Unit (ALU) the operations:
Multiplexer unit Shifter unit
case ({Sel[4:3]})2'b00 : Y = ALU_NoShift;
2'b01 : Y = ALU_NoShift
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Case studyArithmetic Logic Unit (ALU) Testbench
`timescale 1ns/10psmodule TESTGEN_ALU;reg [4:0] Sel;reg CarryIn;
reg [7:0] A,B;wire [7:0] Y;integeri;
ALU ALU(Sel, CarryIn, A, B, Y);
initialbegin
Sel = 5'b00000;A = 8'h33;
B = 8'hcc;
CarryIn = 0;
// Test Arithmetic Unitfor(i=0; i
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Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
Case study I
In this exercise you have to do these steps:
Create the ALU verilog source Create the ALU testbench
Check the arithmetic unit
Check the logic unit Check the shifter unit
Compile, elaborate and simulate Check the operation of the ALU
Case study II
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Case study II
Central Processor Unit (CPU)
The design of a processor is a complex scenario. Multimillion
instruction processors (MIPS), complex instruction setprocessors (CISC), reduced instruction set processors (RISC)
are all models that are used in different applications.
The HDL description you will be working with is a simple
processor that does 4 simple mathematical functions.
The circuit implements addition, incrementing, complementing
and XOR.
Case study II
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Case study II
There are five modules used in this exercise:
alu.v Contains the mathematical operations
reg8.v Works as the random access memory (RAM)
count5.v Works as a program counter
decode.v Controls the flow of data through a state machine
cpu.v Top-level design
The Verilogdescription of all models are completed.
The intention of this lab is creating a testbench and simulatingthe top level design (CPU).
Case study II
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y
The schematic of the CPU
Case study II
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y
The operation of the CPU
The CPU begins to operate on the positive edge of the reset.
At each positive edge of the clock the state of the CPU changes.There are 8 states per instruction cycle.
On reset signal the counterof the CPU resets, and sets pcout(address of instructions) to 00h this is the address of the firstinstruction. The value of the PC register is incremented in each
instruction cycle.
The ALU executes an instruction (which one is determined by
opcode) when it is enabled (en_alu = 1).
Case study II(
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The decode module
determines the operation ofthe CPU in different states
and determines the order of
the states (Gray counter).
module decode(ld_acc, mem_rd, mem_wr,inc_pc, ld_pc, ld_ir, sel_dat, en_alu, sel_adr,
opcode, zero, clk, rst);
always @(posedge clk or negedge rst)begin
if(!rst) state = 3'b000;elsecase (state)3'b000: state = 3'b001;3'b001: state = 3'b011;3'b011: state = 3'b010;3'b010: state = 3'b110;3'b110: state = 3'b111;3'b111: state = 3'b101;
3'b101: state = 3'b100;3'b100: state = 3'b000;
endcaseend
.
10 3
2
75 6
4 The cycle ofstates
Reset
Case study II
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In the testbench, imagine, there is a RAM connected to the CPU.
Operand A is stored in the RAM at the address 08h, theoperand B is stored at the address 09h.The instructions are stored from the address 00h.
CPU
0000
1111
0100 A operand
0101 B operand
RAM
memrd / 1
memwr / 1clock / 1
dataout / 8
datain / 8
reset / 1
testbench
address/ 5
Case study II
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Department of Electron Devices, CAD Laboratory
The instruction word format (8 bit)
ooo | aaaaa MSB (3 bit) the operation code LSB (5 bit) the address of the operand,
they are stored in the instruction register(IR) after being read from the memory
Example:
100 | 01001 (89h) Memory read (dataIn F0h) from 09h
Generate accumulatorXOR dataIn (04h)
Case study II( t t )
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case (state)
State 0 set the address topcout
3'b000: {inc_pc, ld_acc, ld_pc,mem_wr, mem_rd, ld_ir, sel_dat, en_alu, sel_adr} =9'b000000001
3'b001: {inc_pc, ld_acc, ld_pc, mem_wr, mem_rd, ld_ir, sel_dat, en_alu, sel_adr} =
9'b000011001; State 1 read from memory, and load theinstruction to the IR
3'b011: {inc_pc, ld_acc, ld_pc, mem_wr, mem_rd, ld_ir, sel_dat, en_alu, sel_adr} =
9'b000000001; State 3 stop reading from the memory
3'b010: {inc_pc, ld_acc, ld_pc, mem_wr, mem_rd, ld_ir, sel_dat, en_alu, sel_adr} =9'b100000001;
State 2 increment PC
State 6 set the address to IR (for read
operand from the memory)
3'b110: {inc_pc, ld_acc, ld_pc, mem_wr, mem_rd, ld_ir, sel_dat, en_alu, sel_adr} =9'b000000000;
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3'b111: case (opcode)
3'b111: {inc_pc, ld_acc, ld_pc, mem_wr, mem_rd, ld_ir, sel_dat, en_alu, sel_adr} =9'b001000010;
3'b010,3'b100,3'b101: {inc_pc, ld_acc, ld_pc, mem_wr, mem_rd, ld_ir, sel_dat, en_alu, sel_adr} =
9'b000010010;
3'b000: begin{inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} =
9'b000000010;
end
default: {inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} =9'b000000010;
endcase
State 7 depends on the opcode
Opcode 7 - enable ALU, load IR address to PC
register (simple goto)
Opcode 2,4,5 enable ALU, enable mem_rd
Opcode 0 enable ALU
Opcode 1,3,6 enable ALU
Case study II
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Department of Electron Devices, CAD Laboratory
3'b101: case (opcode)
3'b001: {inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} =9'b000000100;
3'b010,3'b100,3'b101: {inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} =
9'b010000000;
3'b000: begin{inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} =
9'b000000100;
end
default: {inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} =9'b000000100;
endcase
State 5 depends on the opcode
Opcode 1 enable sel_dat
Opcode 2,4,5 enable ld_acc (Load to
accumulator)
Opcode 0 enable sel_dat
Opcode 3,6,7 enable sel_dat
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3'b100: case (opcode)
3'b110: {inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} =9'b000100100;
3'b010,3'b100,3'b101: {inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} =
9'b000000000;
3'b000: begin{inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} =
9'b000000100;
end
default: {inc_pc,ld_acc,ld_pc,mem_wr,mem_rd,ld_ir,sel_dat,en_alu,sel_adr} =9'b000000100;
State 4 depends on the opcode
Opcode 6 enable sel_dat, mem_wr
Opcode 2,4,5 disable all
Opcode 0 enable sel_dat
Opcode 3,6,7 enable sel_dat
Case study II
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Department of Electron Devices, CAD Laboratory
In this exercise you have to do these steps:
Create the CPU testbench
Read two operands from the memory
(from the 16h and 17h address)
Generate A and B Write the result to the 1Ch address
Compile, elaborate and simulate
Check the operation of CPU
Delay backannotation
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Department of Electron Devices, CAD Laboratory
In the next few pages, you will become familiar with the
verilog backannotation interface. The presentation that
follows lets you experiment with the simulation of thecorrect physical delays.
Delay backannotation
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Standard Delay File (SDF)
After the VerilogRTL description is synthesised by any Physical
Synthesis (e.g. Cadence PKS) or backannotated by any Physical
Design Tool (e.g. Silicon Ensemble) the real constraints of the
physical design are computed and stored in an SDF file.
The SDF file contains the pre-calculated or the real delays of
each net (RC) and the delays of each block (gates).
This file can be loaded into the VerilogSimulator Environment,
so the pre-calculated or real, accurate timing rule violationscan be viewed and checked.
Delay backannotation
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To enable the SDF elaborating:
Select ToolsElaboratormenu item
and
Click on Advanced Optionsbutton, then the Elaborator
Advanced Options windowsss
appears
Delay backannotation
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Select Verilog
Perfomance tab,
and check in
Delay Modes andselectpath mode
Select PLItab,
and check in
Enable delayannotation at
simulation time
Delay backannotation
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Select
Annotation and
check in Specify
delay types and
select Maximum
mode.
Check in, too,
Use worst case...
Delay backannotation
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The VerilogRTL source simulation result, without using SDF file
(the 0.1ns - the default delay of the gates - can be seen)
Delay backannotation
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Department of Electron Devices, CAD Laboratory
timescale 1ns/10psmodule test_alu;
reg clk, ena, rst;
wire [7:0] aluout;
parameter half_cyc = 100;alu alu(aluout, zero, opcode, data, accum, clk, ena, rst);
initial $sdf_annotate("alu_rtl.sdf",alu);
initial
begin
.
end
endmodule
Add to the testbench source initialthe instruction to
use SDF in the elaboration and in the simulation:
$sdf_annotate(sdf_file_name.sdf,module_name)
Should be the first initial before the other initials !!!
Delay backannotation
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7/29/2019 Lesson Verilog
58/59
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
The VerilogRTL source simulation result with using the SDF file
(the 1.4ns - the delays of the nets and the gates)
Case study III
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7/29/2019 Lesson Verilog
59/59
Budapest University of Technology & Economy
Department of Electron Devices, CAD Laboratory
In this exercise you have to do these steps:
Use the previously generated CPU testbench Compile, elaborate and simulate using the delay file Check the operation of the CPU
Compare the delays with the original ones