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吳俊興高雄大學 資訊工程學系

November 2004

EEA051 - Digital Logic數位邏輯

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5-1 Sequential Circuits5-2 Latches5-3 Flip-Flops5-4 Analysis of Clocked Sequential Circuits5-5 HDL for Sequential Circuits5-6 State Reduction and Assignment5-7 Design Procedure

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Combinational circuitsThe outputs are entirely dependent on the current inputs Contains no storage elements, no feedback

Sequential circuitsConsists of a combinational circuit to which storage elementsare connected to form a feedback pathOutputs are a function of both the current inputs and the present state of the storage elements

Storage/memory elementscapable of storing binary informationdefining the state of the sequential circuitNext state is a function of external inputs and current state

(inputs, current state) ⇒ (outputs, next state)

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Two major types: depending on timing of their signalsAsynchronous sequential circuits (see Chapter 9)

The transition happens at any instant of timeDo not use clock pulses. Change of internal state occurs when there is a change in input variables

Instability problem: may become unstable at timesStorage elements work as time-delay device

May be regarded as a combinational circuit with feedback

Synchronous sequential circuitsThe transition happens at discrete instants of timeThe circuit responds only to pulses on particular inputsStorage elements are affected only with the arrival of each pulse

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Clocked sequential circuits (CSC)Synchronous sequential circuits that use clock pulses in the inputs of storage elementsSynchronization is achieved by a master-clock generator to generate a periodic train of clock pulsesmost commonly used, no instability problems

Flip-flops: the storage elements used in CSCbinary cells capable of storing one bit of informationMaintains a binary state indefinitely until directed by an input signal to switch states

The states change only during a clock pulse transitionmajor differences in the number of inputs they possess and in the manner in which the inputs affect the binary state

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The outputs can come either from the combinational circuit or from the flip-flops or bothThe flip-flops receive their inputs from the combinational circuit and also from a clock signal with pulse that occurs at fixed intervals of time

The flip-flop outputs cannot change and the feedback loop is broken when a clock pulse is not active

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Latches: basic circuits to construct flip-flopscapable of storing binary information, impractical for use in synchronous sequential circuits

more complicated types can be built upon itSR Latch

Two states: Set and Reset statesan asynchronous sequential circuit with two cross-coupled NOR gates

S’-R’ LatchSR latch with two cross-coupled NAND gates

0 signal to change its stateSR latch with control input

Determines when the state of the latch can be changedD Latch

eliminate undesirable condition of indeterminate state in SR latch

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Two inputs labeled S for set and R for reset(S,R)=(1,0): set (Q=1, the set state)(S,R)=(0,1): reset (Q=0, the reset/clear state)(S,R)=(0,0): normal condition

no operation, in either the set or the reset statedepending on which input was most recently at 1

(S,R)=(1,1): indeterminate state (Q=Q'=0)consider (S,R) = (1,1) ⇒ (0,0)unpredictable next state when both inputs return to 0(depend on which input returns to 0 first)

(S+Q)’

(R+Q’)’

Q = [R+(S+Q)’]’ = R’(S+Q)Q’ = [S+(R+Q’)’]’ = S’(R+Q’)

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0 signal to change its state(S,R)=(0,1): set (Q=1, the set state)(S,R)=(1,0): reset (Q=0, the reset/clear state)(S,R)=(1,1): normal condition(S,R)=(0,0): indeterminate state (Q=Q’=1)

unpredictable next state

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An additional input as an enable signalC=0 ⇒ quiescent condition, no changeC=1 ⇒ S or R is allowed to affect the SR latch

(1 signal to change its state)

0/1

S_ 1/S'

R_ 1/R'

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S=D and R=D’Ensure S and R are never equal to 1 at the same timeEliminate the undesirable conditions of the indeterminate state in the RS latch

One output Q and two inputs: D (data) and C (control)Q = D when C=1Q = no change when C=0

0/1

S_ 1/D'

R_ 1/D

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A trigger: the momentary change to switch the state of a latch or flip-flop

The transition it causes is said to trigger the flip-flopTypes of triggers

Level triggered – latchesD latch is triggered every time the pulse stays at logic 1 level.Be used as a temporary storage between a unit and its environment

Edge triggered – flip-flopsIf level-triggered flip-flops are used, the feedback path may cause instability problem as long as the clock pulse stays in the active leveltriggered only during a signal transition (0⇒1 or 1⇒0)

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Store binary info during transitionMethod 1: Master-slave D flip-flop

two separate flip-flopsa master flip-flop (positive-level triggered)a slave flip-flop (negative-level triggered)change only during negative edge of clock

longer propagation delay

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(cont.)

Method 2: D-type positive-edge-triggered flip-flopThe most efficient flip-flop constructed with 3 SR latchesCLK=0 ⇒ S=R=1, no changeCLK=positive transition ↑⇒ Q=D (state changes once)

D=0 when CLK becomes 1 ⇒ R=1 to 0 ⇒ D changes further, no effectD=1 when CLK becomes 1 ⇒ R=stay 1 ⇒ D changes further, no effect

CLK=negative transition or 1 ⇒ quiescent condition (state holds)

Q=R ⇒ Q=D

(RD)’R

(RD)’

(RD)’S [S(RD)’]’=S’+RD

S

[S(RD)’]’

RR=CLK’+S’+RD

SS=CLK’+S(RD)’

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(RD)’R

(RD)’

(RD)’S [S(RD)’]’=S’+RD

S

[S(RD)’]’

RR=CLK’+S’+RD=CLK’+[S(RD)’]’

SS=CLK’+S(RD)’

D=1

D=0

SS=SR’RR=(SR’)’=S’

SS=RR=1QQ=Q

SS=SRR=S’

SS=RR=1QQ=Q

CLK=1CLK=0

D=1SS=CLK’+SR’RR=CLK’+(SR’)’

D=0SS=CLK’+SRR=CLK’+S’

t 0 1 2 3 4 5 6 7 8 9 10 12 14 16 18 20 22 24 26 28 30

CLK __--__--__--__--__--__--__--__--D _______--------________--------_

Q --________--------________-----

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Setup timea minimum time for which the D input must be maintained at a constant value (or be ready) prior to the occurrence of the clock transitiondata to the internal latch

Hold timea minimum time for which the D input must not changes after the application of the positive transition of the clockclock to the internal latch

These parameters are usually specified in manufacturer’s data books.

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> dynamic indicator

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Edge-triggered D flip-flopStore binary information during edge triggerRequire the smallest number of gatesOther types of flip-flops can be constructed using it

JK Flip-Flop: D=JQ'+K'QJ=0, K=0: D=Q ⇒ Q no changeJ=0, K=1: D=0 ⇒ Q =0 reset to 0J=1, K=0: D=1 ⇒ Q =1 set to 1J=1, K=1: D=Q’ ⇒ Q =Q’ complement output

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T (toggle) flip-flop: D = T⊕Q = TQ'+T'QT=0: D=Q, no changeT=1: D=Q' ⇒ Q=Q'

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Characteristic equationsD flip-flop Q(t+1) = DJK flip-flop Q(t+1) = JQ’+K’QT flop-flop Q(t+1) = T⊕Q = TQ’ + T’Q

Characteristic Tables

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preset/direct set: the inputs that sets the flip-flop to 1clear/direct reset: the inputs that clears the flip-flop to 0

to a known starting stateasynchronous reset

reset=0 ⇒ force Q=0, resetting

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State equation (transition equation)A(t+1) = A(t)x(t) + B(t)x(t)B(t+1) = A’(t)x(t)y(t)=[A(t)+B(t)]x’(t)orA(t+1)=Ax+BxB(t+1)=A’xy=(A+B)x’

CSC diagram ⇒ state equation

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state table ⇐ state equation ⇐ CSC diagramFour sections: present state, input, next state and outputList all possible binary combinations of present state and inputsDetermine next states and outputs from the logic diagram or from the state equations

A(t+1)=Ax+BxB(t+1)=A’xy=(A+B)x’

m flip-flops and n inputs• 2m+n rows• m column of next-state

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Only 3 sections: present state, next state, and outputGiven one input, there are two possible next states and outputs for each present state

What form to be used depends on applications

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State Diagram - pictorial view of state transitions

input/outputx/y

A(t+1)=Ax+BxB(t+1)=A’xy=(A+B)x’

state diagram⇔ state table⇔ state equation⇔ logic diagram

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logic diagram of a sequential circuit consists of flip-flops + gatesoutput equations: the circuit that generates external outputsinput equations: the circuit that generates inputs to flip-flops

Symbol convention: DQ = x + yan OR gate with inputs x and y connected to the D input of a flip-flop whose output is labeled with the symbol Q

xy

output equations

input equations

(or excitation equations)state equationscharacteristic

equations

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D/JK/T FF input equation⇔ state equation⇔ CSC logic diagram⇔ state diagram⇔ state table

State EquationsA(t+1)=Ax+BxB(t+1)=A’x ⇒

y=(A+B)x’

FF Input EquationsDA=Ax+BxDB=A’x

y=(A+B)x’Output Equation

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Given:input function: DA=A⊕x⊕ystate equation: A(t+1)=A⊕x⊕yone flip-flop and 2 inputs

Find:⇔ logic diagram⇔ state table⇔ state diagram

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Analysis with JK Flip-Flops

(1) Flip-flop input equations

(2) State equations

(4)(3)

Given logic circuit, find the others

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Analysis with T Flip-FlopsCharacteristic equation: Q(t+1)=T⊕Q=T’Q+TQ’Input equations and output equation:

TA=Bx; TB=x; y=ABState equations

A(t+1)=(Bx)’A+(Bx)A’=AB’+Ax’+A’BxB(t+1)=x⊕B

Given logic circuit, find the others

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Mealy modelThe output is a function of both the present state and input

— The outputs may change if the inputs change during the clock cycle— The outputs may have momentary false values due to delay— To synchronize, the outputs must be sampled only during the clock edge

Mealy finite state machine (FSM, machine): the Mealy model of a sequential circuitexample: Fig. 5-15 (D)

Moore modelThe output is a function of the present state only

— The outputs are synchronized with the clockMoore finite state machine (FSM, machine): the Moore model of a sequential circuitexample: Figure 5-19 (JK), 5-20 (T)

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Sequential circuit analysis:starts from a circuit diagram andculminates in a state table or state diagram

Sequential circuit design:starts from a set of specifications andculminates in a logic diagram

State reduction problem: reduction of the number of flip-flops in a sequential circuit, while keeping the external input-output requirements unchanged

m flip-flops produce 2m statesState reduction ⇒ fewer flip-flops

but may require more combinational gates

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Example: Figure 5-22 (7 states)Given a state table or state diagramFind ways of reducing the number of states without altering the input-output relationships

Test sequence•Initial state: a•Input sequence: 01010110100

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State equivalence: Two states are equivalent if, for each member of the set of inputs, theygive exactly the same output andsend the circuit either to the same state or to an equivalent state

Algorithm:1.Look for two present states that

go to the same next state andhave the same output for both input combinations

2.Remove one of the equivalent state and replace by the other state each time it occurs in the table

Another approach: systematic reduction with an implication table(see Section 9-5)

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State Reduction Example

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State assignment: assign coded binary values to the stateIn order to design a sequential circuit with physical componentsA circuit with m states need n bits where 2n >= m

Transition table: a state table with a binary assignmentTo distinguish it from a stable table with symbolic names for states

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Design of a clocked sequential circuitstarts from a set of specificationsobtains a state table/diagram (or equivalences) firstculminates in a logic diagram (or a list of Boolean functions)

TasksChoosing the flip-flops

Determined from the number of states neededFinding a combinational gate structure

Derived from the state table by evaluating the flip-flop input equations and output equations

Summarized proceduremost challenging

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Specification: Design a circuit that detects three or more consecutive 1’s in a string of bits combining through an input line

1st Step – deriving state diagram or state table

Moore model circuit –output is 1 when circuit is in state S3 and 0 otherwise

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Step 2-4: Assign binary codes and list state table (Table 5-11)Step 5:Choose type of flip-flopsStep 6:Derive simplified input and output equations

01234567

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(cont.)

Step 7 – Draw the logic diagram (using simplified functions)

Excitation table: a table that lists required inputs

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input equations next states

Excitation Table

present states

? output equations

input equations state

equations

characteristic equations

present states ?

output equations ?

(1) Stable table (2) Input equations (3) Circuit diagram

(1) Input equations (2) Output equations (3) State table (4) State diagram

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The input equations for the circuit using flip-flops other than the D type, i.e. JK and T types, must be derived indirectly from the state tableExcitation table: list the required inputs for a given change of state

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The input equations must be evaluated from the present-state to next-state transition derived from the excitation table

(1)

(2)

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Logic Diagram for Sequential Circuit with JK Flip-Flops

JA=Bx’ KA=Bx JB=x KB=(A⊕ x)’

(3)

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Example: 3-bit counter (1)

(2)

(0)

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TA2=A1A0 TA1=A0 TA0=1

(3)

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Chapter 5 Synchronous Sequential Logic5-1 Sequential Circuits5-2 Latches5-3 Flip-Flops5-4 Analysis of Clocked Sequential Circuits5-5 HDL for Sequential Circuits5-6 State Reduction and Assignment5-7 Design Procedure