eeet2097 lecture 11 2013(1)

EEET 2097 Electronic Circuits Lecture 11

High Frequency Response of Differential Amplifiers and Advances in Transistor

Technologies Assoc. Prof. James Scott [email protected]

EEET2097: Electronic Circuits

1–1

Outline •  High Frequency Response of Differential

Amplifiers –  Resistively loaded MOS amplifier –  Actively loaded MOS amplifier

•  High Frequency Transistors –  Heterojunction Bipolar Transistor (HBT) –  High Electron Mobility Transistor (HEMT)

•  Future Trends in CMOS devices •  Advanced amplifier configurations


Page 11–2

Resistively Loaded MOS Differential Amplifier


Page 11–3

Differential Half-Circuit The half circuit is a simple common-source amplifier.


Page 11–4

Ad =VoVid

=− gmRL

'( ) 1− s Cgd gm( )"# $%

1+ s Cgs +Cgd 1+ gmRL'( )"

#$%Rsig + CL +Cgd( )RL'{ }+ s2 CL +Cgd( )Cgs +CLCgd

"# $%RsigRL'

whereRL

' = RD || roThe upper 3dB frequency is

fH ≅ fP1 ≅1

2π Cgs +Cgd 1+ gmRL'( )"

#$%Rsig + CL +Cgd( )RL'{ }

Common-mode Half-Circuit


Page 11–5

CSS/2 together with 2RSS forms a real axis zero in the common-mode gain function. This is much lower in frequency than the other poles and zeroes in the circuit.

Common-mode Half-Circuit (2)


Page 11–6

Acm (s) = −RD2ZSS

ΔRDRD

#

$%

&

'(

= −12RD

ΔRDRD

#

$%

&

'(YSS

= −12RD

ΔRDRD

#

$%

&

'(1RSS

+ sCSS

#

$%

&

'(

= −RD2RSS

ΔRDRD

#

$%

&

'( 1+ sCSSRSS( )

where ΔRD is the mismatch between the two drain resistances of the differential amplifier

The zero on the negative real axis of the s-plane has a frequency

ωZ =1

CSSRSSor in Hz:

fZ =1

2πCSSRSS


Page 11–7

2 break points in the CMRR response

CMRR dB( ) = Ad dB( )− Acm dB( )

Active Loaded MOS Differential Amplifier


Page 11–8

Cm is the total capacitance at the input node of the current mirror CL is the total capacitance at the output plus any load capacitance

Grounded output is used to calculate the transconductance Gm

Input and Output Capacitances •  The total capacitance at the input of the

current mirror is:

•  The output capacitance CL includes an actual load capacitance Cx

•  These capacitances primarily determine the dependence of the differential gain on frequency


Page 11–9

Cm =Cgd1 +Cdb1 +Cdb3 +Cgs3 +Cgs4

CL =Cgd2 +Cdb2 +Cgd 4 +Cdb4 +Cx

Differential Amplifier Transconductance


Page 11–10

Because of the output short circuit, CL will have no effect on Gm

Assuming that ro1 and ro3 are much larger than 1 gm3( )

Vg3 = −gmVid 2gm3 + sCm

Therefore, Q4 conducts a drain current

Id 4 = −gm4Vg3 =gm4gmVid 2gm3 + sCm

Since gm3 = gm4, this equation reduces to

Id 4 =gmVid 2

1+ sCm gm3

Differential Amplifier Transconductance (2)


–11

Now, at the output node the total output current through the short circuit isIo = Id 4 + Id2

=gmVid 2

1+ sCm gm3

+ gm Vid 2( )

So the transconductance Gm is

Gm ≡IoVid

= gm1+ s Cm

2gm3

1+ s Cm

gm3

At low frequencies, Gm is equal to gm. At higher frequencies, Gm has apole and zero:

fP2 =gm3

2πCm

, fz =2gm3

2πCm

The zero is at twice the frequency of the pole

Pole and Zero Frequencies


Page 11–12

Since Cm is approximately equal to Cgs2 +Cgs4 = 2Cgs

fP2 =gm3

2πCm

≅gm3

2π 2Cgs( )≅ fT 2

andfz ≅ fTthus the mirror pole and zero occur at very high frequencies.

Voltage Gain


Page 11–13

Since we know the transconductance, we can multiply it by the total impedance between the output node and ground to get the voltage gain

Vo =1

1Ro+ sCL

!

"

####

$

%

&&&&

Io

=GmRo

1+ sCLRo

!

"#

$

%&Vid

So

VoVid

= gmRo( )1+ s Cm

2gm3

1+ s Cm

gm3

'

(

))))

*

+

,,,,

11+ sCLRo

!

"#

$

%&

whereRo = ro2 || ro4

Therefore, we have an additionalpole with frequency fP1

fP1 =1

2πCLRoThis is usually the dominant pole,especially when a large load capacitanceis present.

Advanced Devices •  We will now investigate some advanced

device structures –  III-V semiconductors

•  HBT’s, HEMT’s – Advanced Si devices

•  Sub-10nm logic technologies – Carbon nanotube transistors

•  High frequency circuits


Page 11–14

III-V Semiconductors •  III-V semiconductors have a lattice

comprised of alternate group III and group V atoms from the periodic table –  e.g. GaAs, InP, GaN – These materials have higher electron mobility

than Si => higher frequency performance – There are still a total of 4 covalent bonds

around each atom (group III atom supplies 3 valence electrons, group V supplies 5 valence electrons)


Page 11–15

Comparison of Semiconductors


Page 11–16

[2, Figure 1]

Heterojunction Bipolar Transistors

•  Improved performance can be achieved with a GaAs/GaAlAs (or SiGe or InP/InGaAs) heterojunction between the base and emitter. –  i.e. the base and emitter are made from different

semiconductor materials. – Higher base doping → reduced rx’ – Reduced emitter doping → reduced Cπ –  ƒT over 100 GHz

EEET097 Electronic Circuits

Page 11–17


Page 11–18

GaAs HBT Structure

[1, Fig. 6-26]

•  Complexity is in the vertical structure of the semiconductor material.

•  Base to emitter spacing is critical (must watch shorting between the base and emitter)


Page 11–19

Alternate HBT Structures •  Si-Ge is very attractive at wireless frequencies

–  Si collector and base –  Ge emitter

•  See http://www.infineon.com/cms/en/product/rf/rf-transistors/channel.html?channel=ff80808112ab681d0112ab6b2b24074e

High Electron Mobility Transistor (HEMT)

•  Depletion mode device – VDS positive, VGS negative

•  Schottky diode gate –  reverse-biased metal-semiconductor junction

•  Extremely high electron mobility in the channel –  channel is a two-dimensional electron gas,

formed at a heterojunction between two different semiconductor materials


Page 11–20

21

GaAs HEMT Structure

Figure 6-45 Generic heterostructure of a depletion-mode HEMT.

n+ n+

Source Gate Drain

n-GaAlAsGaAlAs

2DEGGaAs

Semi-isolated GaAs

–d

0

x

y

Generic heterostructure of a depletion-mode HEMT [1, Fig. 6-45]


22

HEMT Operation •  The larger bandgap GaAlAs layer is doped

with n-type donors and the following GaAlAs and GaAs layer are left undoped.

•  Electrons minimise their energy by diffusing out of the GaAlAs into the lower potential GaAs where they form a 2-dimensional electron gas near the heterointerface.


23

HEMT Operation (2) •  Since the electrons and the donors are

spatially separated, ionised impurity scattering is avoided making it possible to obtain extremely high electron mobilities, comparable with pure bulk GaAs.


24

Pseudomorphic HEMTs •  HEMTs are primarily constructed of

heterostructures with matching lattice constants to avoid mechanical tension between layers.

•  Pseudomorphic HEMTs use mismatched lattices, e.g., with a larger InGaAs lattice compressed onto a smaller GaAs lattice. –  Improved performance is possible.


25

HEMT Features •  Major advantages of the HEMT structure

are: –  small gate to conducting channel separation

(~300Å) leading to extremely high transconductances,

–  a large current-carrying capability (~500mA/mm per interface),

–  a small source resistance, –  a small drain-source saturation voltage

(typically < 1V). EEET2097 Electronic Circuits

GaN HEMT Structure


Page 11–26

[2, Figure 4]

Source-connected field plate

Gate-connected field plate

Si-C offers better thermal conductivity to remove heat

AlGaN-GaN heterojunction

GaN has a large bandgap so it is very attractive for power devices

27

GaN HEMT Performance •  Cree CGH21240F for WCDMA, LTE and

WiMax applications [3] •  At 2.14 GHz:

– Gain = 15 dB – Psat = 215 W – VDS = 28 V –  IDS = 1 A – VDSmax = 120 V


Sub-10nm Logic Technology


Page 11–28

[4,Fig. 1]

Gate Length Trends


Page 11–29

Fig. 2. Transistor channel length was scaled down according to Dennard’s rules (0.72x per generation) till the turn of the century, corresponding to 350 nm node. Starting with 250 nm node, Intel accelerated gate length scaling, seen as deviation of the green dots from the Dennard line. From the 65 nm node channel length scaling slowed down due to power dissipation concerns, which is seen in flattening of the green dot line. To sustain Moore’s law in the form of continued reduction in packing density, the gate length needs to follow the Dennard line again. Thin silicon channel architecture, FinFET or UTB-SOI, enables the continued gate length scaling beyond 32 nm node as shown by the open green dots. By the end of the decade, at 5 nm node we will likely see the adoption of GAA architecture. [4]

Fin-FET and UTB-SOI


Page 11–30

Fig. 4. The two new channel architectures, FinFET and UTB-SOI, are compared with the current industry-standard of planar CMOS architecture. The FinFET architecture employs a “fin” of silicon surrounded by the gate on three of its sides, left right and top surfaces, making it a 3D transistor. UTB-SOI employs an ultra-thin silicon channel which lies below the gate dielectric layer, and sits on top of the buried oxide. Note that these cartoons are not to scale. Table 1 shows possible FinFET dimension evolution, where the “fin” in the FinFET architecture would be approximately half the gate length, and for the UTB-SOI architecture the channel thickness would be approximately one fifth of the gate length.

[4]

Fin-FET Dimension Evolution


Page 11–31

Xtrapolated Design Rules for FinFET Scaling from What is in Production Today

Nano-Scale Interconnects


Page 11–32

Fig. 9. (a) Modelled RC delay rising rapidly for conventional dual damascene based interconnects driven by rise in resistance. Disruptive interconnect architecture such as the one shown in schematic cross-section (b), would reduce significantly the rise of RC delay.

[4]

Carbon Nanotube Devices [5] •  Carbon nanotubes (CNT’s) have 1-

dimensional transport that leads to –  higher mobility –  higher current carrying capability –  low distortion due to a linear relationship

between drain current and gate-source voltage –  higher temperature stability and electrothermal

ruggedness


Page 11–33

CNT Structure


Page 11–34

Fig. 1. Sketch of (a) graphene nanoribbon and (b) carbon nanotube.

[5]

Material Properties •  Graphene is a single-atomic layer Carbon

(C) sheet –  It does not have a bandgap (metal-like)

•  Opening up a bandgap is possible by reducing the width of the sheet to a few nm, thus creating a graphene nanoribbon (GNR). –  significant reduction in mobility –  large variability in threshold voltage and

mobility


Page 11–35

Material Properties (2) •  Such effects can be circumvented by rolling

up a GNR into a CNT –  occurs “naturally” under certain (process)

conditions –  semiconducting CNTs with a bandgap of

around 0.88 eVnm/diameter can be obtained – For practical transistor applications typical

diameters are around 1.6 nm, yielding a bandgap of ≈ 0.55 eV


Page 11–36

CNT FET Structure


Page 11–37

Fig. 5. (a) Schematic cross-section of a top-gate multitube CNTFET. (b) Band diagram for VDS > VGS > 0. WF is the Fermi level of the S or D contact reservoir. Vbi = ΦbS,n −Wg/(2q) is the built-in voltage at the S contact. [5, Fig. 5]

CNT FET I/V Characteristics


Page 11–38

Fig. 8. Output characteristics (VGS/V = −2.5, −1.5, 0, 1.5, 3) of a CNTFET with only two semiconducting tubes. Comparison between measured data (symbols) and compact model (solid lines). [5, Fig. 8]

Predicted fT Performance


Page 11–39

Fig. 11. Intrinsic transit frequency projections versus channel length calculated from NEGF and BTE (at VGS = VDS = 0.5 V). The additional extrinsic projections are based on a scalable compact model. For the calculation of the extrinsic transit frequency fTx (with s:m = 8:1), the tube density and the contact resistance were changed according to the table (curve number). The filled points correspond to experimental data. [5, Fig. 11]

Wideband Distributed Amplifier •  100 kHz to 50 GHz operation •  Utilises GaAs HEMT-HBT cascode

–  Inductive peaking to improve the bandwidth of the gain stages

•  Averages 8.5 dB of gain across the operating band


Page 11–40

GaAs HEMT-HBT Cascode [6]


Page 11–41

Fig. 1. Cross section of the stacked HEMT–HBT technology provided by the WIN Semiconductors Corporation. Where E, B, and C are emitter, base, and collector of the HBT, and S, G, and D are the source, gate, and drain of the HEMT, respectively.

Cascode Stage


Page 11–42

Inductive Peaking Performance


Page 11–43

Distributed Amplifier Stage


Page 11–44

DA Stage Performance


Page 11–45

Distributed Amplifier


Page 11–46

DA Performance


Page 11–47

Distributed Amplifier Chip


Page 11–48

49

References [1] R. Ludwig and P. Bogdanov, RF Circuit Design: Theory and Applications,

2nd Ed., Pearson Education Inc., NJ, 2009. [2] David W. Runton et al., “History of GaN”, IEEE Microwave Magazine,

IMS Special Issue, pp. 82-93, May 2013. [3] Cree Semiconductor (http://www.cree.com/products/pdf/CGH21240F.pdf) [4] Klaus Schuegraf et al., “Semiconductor Logic Technology Innovation to

Achieve Sub-10 nm Manufacturing”, IEEE J. of the Electron Devices Society, Vol. 1, No. 3, pp. 66-75, March 2013.

[5] Michael Schröter et al., “Carbon Nanotube FET Technology for Radio-Frequency Electronics: State-of-the-Art Overview”, IEEE J. of the Electron Devices Society, Vol. 1, No. 1, pp. 9-20, Jan. 2013.

[6] H.-Y. Chang et al., “Design and Analysis of a DC–43.5-GHz Fully Integrated Distributed Amplifier Using GaAs HEMT–HBT Cascode Gain Stage”, IEEE Trans. Micr. Theory Tech., Vol. 59, No. 2, pp. 443-455, Feb. 2011.


eeet2097 lecture 11 2013(1)

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