7/23/2019 Embeddedsys Report 52

1/14

Presentation

Design Viterbi Decoder

Lecturer: PhD. Ngo Vu Duc

Students: Vu Manh Cuong

Hoang Manh Cuong

Tran Anh Duc

Nguyen Quang Truong

Embedded system

7/23/2019 Embeddedsys Report 52

2/14

Contents

1

Overvie o! Viter"i Decoder2

Viter"i A#gorith$3

%e!erences4

4

&ntroduction

7/23/2019 Embeddedsys Report 52

3/14

1.Introduction

The important of channel encoder/decoder in communicationsystem

7/23/2019 Embeddedsys Report 52

4/14

1.Introduction

Some kinds of encoder/decoder:Linear block codes:

Hamming codes

Parity codes

Reed Solomon codes

BCH code

.

Convolutional codes Viterbi codes

7/23/2019 Embeddedsys Report 52

5/14

2. Overview of Viterbi Decoder

Is a type of convolutional code

Can be represented as a convolution calculation of

polynomial code generation and the input signal

Structure:

7/23/2019 Embeddedsys Report 52

6/14

2. Overview of Viterbi Decoder

Some characteristic ofViterbi Decoder:

umber of !lipflop: m

o" of input bits: k

o" of output bits : nCode speed: # $ k/n

Constraint length:

L $ k%m&'(

7/23/2019 Embeddedsys Report 52

7/14

3. Viterbi Algorithm

In this pro)ect* +e +ill designa Viterbi decoder +ith m = 2,

k = 1, n = 2, L = 2and the

length of input signal is 8 bits

& Structure:

& State transition diagram of

the encoder

7/23/2019 Embeddedsys Report 52

8/14

3. Viterbi Algorithm

Viterbi ,lgorithm: -a.imum LikelihoodTrellis diagram:

7/23/2019 Embeddedsys Report 52

9/14

3. Viterbi Algorithm

ard+are implementation:

7/23/2019 Embeddedsys Report 52

10/14

3. Viterbi Algorithm

ard+are implementation:& 0ranch metric unit 0-1

7/23/2019 Embeddedsys Report 52

11/14

3. Viterbi Algorithm

ard+are implementation:& 2ath metric unit 2-1

,ccumulated metric of each state

is Da* Db* Dc and Dd

D' $ Da 3 Daa4 D5 $ Db 3 DbaDa%ne+( $ D'6D57D':D5

D8 $ Dc 3 Dcb4 D9 $ Dd 3 Ddb

Db%ne+( $ D86D97D8:D9

D $ Da 3 Dac4 D; $ Db 3 DbcDc%ne+( $ D6D;7D:D;

D< $ Dc 3 Dcd4 D= $ Dd 3 Ddd

Dd%ne+( $ D

7/23/2019 Embeddedsys Report 52

12/14

3. Viterbi Algorithm

ard+are implementation:& 2ath metric unit 2-1

Input bit>s corresponding to the

states

0ita%ne+( $ D'6D570ita3?:0itb3?0itb%ne+( $ D86D970itc3?:0itd3?

0itc%ne+( $ D6D;70ita3':0itb3'

0itd%ne+( $ D

7/23/2019 Embeddedsys Report 52

13/14

3. Viterbi Algorithm

ard+are implementation:& Traceback unit T01: restores an %almost( ma.imum&

likelihood path from the decisions made by 2-1 %the

minium accumulated metric(

7/23/2019 Embeddedsys Report 52

14/14

. !eferences

#eferences:L"Van de -eeberg* , Viterbi Decoder* @ctober 'A