high-speed analog-to-digital converters for modern
TRANSCRIPT
High-Speed Analog-to-Digital Converters for Modern Satellite Receivers :
Design Verification Test and Sensitivity Analysis
Ph.D. Dissertation ExamFebruary 06, 2008
Seokjin Kim
Analog & Mixed-Signal System Design Lab.Electrical and Computer EngineeringUniversity of Maryland, College Park
2
Acknowledgements
• Dr. Martin Peckerar (Chair/Advisor)
• Dr. Neil Goldsman• Dr. Pamela Abshire• Dr. Kristine Rosfjord• Dr. Aris Christou
• Dr. Keith Perkins (Naval Research Laboratory)
• VLSI/Wireless department at Hughes Network Systems
• Analog & Mixed-Signal System Design Laboratory
3
Agenda
• Motivation & objective• Contributions & publications• Overview of analog-to-digital converters (ADCs) • Design verification test (DVT) outline• High-speed ADC architecture: New result• ADC design verification test (DVT) software• ADC DVT methodology• Production test checklist
Automated test equipment (ATE)• ADC corner lot study as a sensitivity analysis• Conclusions
4
Motivation & Objective
• Motivation:– To provide a cost-effective test stand capable of evaluating high-speed
ADC systems in a modern satellite receiver– To help many of high-speed ADC design/test engineers in both industry
and academia
• Objective: to develop full production–ready cost effective design verification test methodology for a high-speed ADC
– Case study for a high-speed ADC:• Design-for-Test (DfT) enhanced approach• Testability
– Develop concurrent engineering design verification test (DVT) procedure– DVT program (test flow, test plan) – VTS suite– Cost-effective ATE solutions
5
Contribution• To provide detailed and generalized High-speed ADC testing methodology
– Improved methodology for dynamic performance testing of ADCs for satellite communications
• Verification tool development: ADC verification test software (VTS) Suite– provide enough background of High-speed ADC
ATE ready Technician level or entry-level engineer can run accurate ADC test
someone who is not familiar with ADC or RF testing could understand it
• Integrated Design-for-Test (DfT) concept as a part of process– Important case study for a high-speed ADC design
• RF design & measurement techniques– Socket design
• Prototype device characterization & production-ready– Device interface board (DIB) design for high-speed mixed-signal applications– Intermodulation and IP3
• First time high-speed ADC design parameters sensitivity analysis corner lot study– To determine the impact of process variations and to analyze the sensitivity of the ADCs to
critical process parameter variations– Manufacturing yield
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Related Publications
• Published:– Seokjin Kim, Radmil Elkis, and Martin Peckerar, “Device Verification Testing of High Speed
ADCs in Satellite Communications Systems,” in IEEE AUTOTESTCON (System Readiness Technology Conference), 2007
IEEE Instrumentation & Measurement Society (IMS)Best Student Paper Award
– Seokjin Kim, Radmil Elkis and Martin Peckerar, “Corner Lot Process Variation Effects on High Speed ADCs for Satellite Receivers,” in IEEE ISDRS, 2007
– Seokjin Kim and Martin Peckerar, “High Speed Analog-to-Digital Converter Design Verification Tests in Satellite Receivers,” in IEEE ISCIT, 2007
• Accepted for Publication:
– Seokjin Kim, Radmil Elkis, and Martin Peckerar, “Device Verification Testing of High Speed ADCs in Satellite Communication Systems,” in IEEE TIM, special-issue, 2008
– Seokjin Kim, Kwangsik Choi, Martin Peckerar and Aris Christou, “Line-spike Induced Failure in Integrated Circuit Bond-wires,” in IEEE IRPS, 2008
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Overview of ADCs
S. Rapuano, and et al., “ADC parameters and characteristics," Instrumentation & Measurement Magazine, IEEE, vol. 8, no. 5, pp. 44-54, 2005
ADC architectures, applications, resolution, and sampling rates
8
ADC Architectural Tradeoffs
Number of Bits(Resolution)
Integrating ADC
- ADC
SAR, Pipeline ADC
Flash ADC
Com
pone
nt M
atch
ing
Number of Bits(Resolution)
Flash ADCSAR ADCPipleline ADC
Integrating ADC- ADC
Number of Bits(Resolution)
Integrating ADC
SAR ADCPipeline ADC
- ADC
Flash ADC
Digital Therm
ometer C
ode
Decoder
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ADCs for Modern Satellite Communications
Typical satellite receiver
• Challenges for the ADC verification testing at high speed – Mixed-signal IC test
• Difficulty to apply traditional metrics to validate system-on-chip (SoC) solutions
Mixed-signal buffering interfaces
– Digital signal processing (DSP) based testing
– Design-for-test (DfT)
• Accurate sampling channel testing (for satellite tuner)
• High-speed ADC testing methodology for a modern satellite receiver– Static/Dynamic ADC testing– Test program
• Verification test software (VTS) suite
Error vector magnitude (EVM)and related quantities
10
Design Verification Process Outline
Capital expensive items:• Test programs• Test equipment• Rack & stack• Automated test equipment
(ATE)• Interfacing
HandlersLoad BoardContactor SocketWafer probingPackaging
• Calibration• Accuracy, repeatability, and
correlation• Design-for-Test (DfT) and
built-in-self-test (BIST)
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High-speed ADC Characterization: New ResultsOVER-RANGE
6-BITQUANTIZER
OVER-RANGE
6-BITQUANTIZER
1:2DEMULTIPLEXER
1:2DEMULTIPLEXER
I-OUT-A
I-OUT-B
Q-OUT-A
Q-OUT-B
OVERRANGEOUTPUT
I CHANNELINPUT
Q CHANNELINPUT
CLOCKINPUT
400 MHz800 MHz
DATAOUTPUTS
CLOCKOUTPUT
DIV2
OVERRANGECOMBINER
ADC top level function block Hughes Network System (Germantown, MD)
THAMES ASIC project
80-pin TQFNPackage
6-bit dual channelResolutionConditions
400 MHzOutput Data Rate
800 MSamples/ secSampling2’s complementary
CodeOutput Format
Digital 3 VAnalog 5 VLVDS 5 V
Supply
LVDS Output with Rload =100 Ω
Output Condition
800 mVpp
AnalogInput
Range
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High-speed ADC Architecture
• Flash type ADC for a speed (800 MS/s)• Fabricated in Atmel’s AT46000 BiCMOS technology• Two identical 6-bit ADCs on a chip
– Application to a modern satellite base-band receiver
Track/Hold
LVDSO/P
Drivers
LVDSO/P
Drivers
Track/Hold
LVDSO/P
Drivers
LVDSO/P
Drivers
LVDSO/P
Drivers
Bias
2
2
2
2 2
2
Rext
in_I+
in_I-
in_Q+
in_Q-
clk
clk
data_ready
over_range
Data Output A
Data Output B
Data Output B
Data Output A
VCC_5VI VCC_digI VCC_lvdsI
VCC_5VQ VCC_digQ VCC_lvdsQVCC_5V_lvdsQ
VCC_5V_lvdsI
data_ready
over_range
High Speed ADC Architecture – Thames (Designed by HNS)
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Design-for-Test Philosophy
High Speed ADC Architecture – Thames (Designed by HNS)
• Common input sampling clock • Demultiplexed (6:12) digital output
– ‘data_ready’ – lower speed data transfer
– ‘over-range’ – over flow• Two’s complement outputs
compliant with IEEE LVDS Std.1596.3-1996
• Temperature sensing and control• External bias setting resistor• Separated voltage supply and
ground pinouts for each analog, digital, buffer sections
‘data_ready’ & Latency
14
Design-for-Test Philosophy
‘over_range’:monitoring ADC input fullscale
Over driven input
‘over_range’ & input voltage
Under driven input
15
in_I+G
nd_l
vdsQ
Gnd
_lvd
sI
bit0A_I
bit3
A_I
bit4
B_I
Gnd_aI
bit5
B_I
bit5
A_I
Gnd
_dig
I
VC
C_l
vdsQ
data_readyclk
Gnd_aI
Dual 6-bit 800-Ms/S Flash ADC
bit0B_I
bit1A_I
bit1B_I
bit2
A_I
bit2
B_I
over_range
bit3
B_I
bit4
A_I
V CC_d
igI
V CC_l
vdsI
VC
C_d
igQ
bit5
B_Q
bit5
A_Q
bit3
B_Q
bit4
A_Q
bit3
A_Q
bit4
B_Q
bit0A_Q
bit0B_Q
bit1A_Q
bit1B_Q
VCC_5VQ
bit2
A_Q
bit2
B_Q
80-pin TQFP
Gnd_aQ
in_Q+
Gnd
_dig
Q
VCC_5V_lvdsQ
Gnd_aQ
VCC_5VI
1
2141
61
VCC_5V_lvdsIGnd_sub
Gnd_subGnd_ESD
bit5
A_I
bit5
B_I
bit4
A_I
bit4
B_I
bit3
B_I
bit3
A_I
bit2
B_I
bit2
A_I
bit1A_I
bit1B_I
bit0A_I
bit0B_I
over_rangedata_ready
bit0B_Q
bit0A_Q
bit1B_Q
bit1A_Q
bit2
B_Q
bit2
A_Q
bit3
B_Q
bit3
A_Q
bit5
A_Q
bit5
B_Q
bit4
A_Q
bit4
B_Q
clk
temp_I
Rext
temp_ctl
in_I-
in_Q-
Packaging:Thermally enhanced thin quad flat 80-pin package(0.5 mm pitch, 12 X 12 mm2 body)
Test Fixture - PackagingFabricated in Atmel’s AT46000 BiCMOS technology
Bare-die:3.2 x 3.2 mm2 84 pin-pad
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THERMAL LANDCOPPER PLANE
HNS high-speed ADC: Thames ASIC DIE
COPPER TRACE
COPPER TRACE
THERMAL LANDCOPPER PLANE
BOND WIRE
EXPOXY
EXPOSED PAD
GROUND PLANEAnalog Ground (AGND)Digital Ground (DGND)
POWER PLANE
6 x 6 ARRAY of THERMAL VIAS(Interface with socket thermal string)
Test Fixture - Packaging Thermal Issue
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Test Fixture & Handler
I input
CLK input
Q input
Mictor connector(low frequency evalution)
ADC socket400MHz data rateDifferential logic probe
Filter & MatchingBalun(single-to-differential driver)
LVDS Receiver
HNS high speed ADC verification test fixture
DUT handler
Loaded DUT on the socketwithout latch cover
Spring loaded 80-pin pogo pin Socket3-pin header
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RF Input to “Thames”
0o 0o
0o180o
0o 0o
0o180o
LPF
LPF
BPF
BPF
THAMESASIC
I+
I-
CLK+
CLK-
RF SignalGenerator
Port Imp. = 50
RF SignalGenerator
Port Imp. = 50
Test FixturePCB
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I/Q channel LPF
PortP2Num=2
CC3C=9.126246 pF
LL2
R=1e-12 OhmL=27.279356 nH
CC2C=15.71677 pF
LL1
R=1e-12 OhmL=27.279356 nH
CC1C=9.126245 pF
PortP1Num=1
Ideal design
Practical design
PortP2Num=2
CC3C=9. pF
LL2
R=1e-12 OhmL=27. nH
CC2C=15. pF
LL1
R=1e-12 OhmL=27. nH
CC1C=9. pF
PortP1Num=1
Ideal component values!
Available component values!
20
I & Q Channel LPF Characteristics
S22
S11
Mag
nitu
de, d
B
0.2 0.4 0.6 0.80.0 1.0
-35
-30
-25
-20
-15
-10
-5
-40
0
freq, GHz
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CLK BPF
LL2
R=1e-12 OhmL=21.823485 nH
CC4C=3.901478 pF
PortP2Num=2
CC5C=7.300996 pF
LL5
R=1e-12 OhmL=11.66195 nH
LL4
R=1e-12 OhmL=21.823485 nH
CC3C=12.573416 pF
LL3
R=1e-12 OhmL=6.771736 nH
CC2C=3.901478 pF
CC1C=7.300996 pF
LL1
R=1e-12 OhmL=11.66195 nH
PortP1Num=1
Ideal designLL2
R=1e-12 OhmL=22 nH
CC4C=3 pF
PortP2Num=2
CC5C=6.8 pF
LL5
R=1e-12 OhmL=10 nH
LL4
R=1e-12 OhmL=22 nH
CC3C=12 pF
LL3
R=1e-12 OhmL=6.8 nH
CC2C=3 pF
CC1C=6.8 pF
LL1
R=1e-12 OhmL=10 nH
PortP1Num=1
Practical design
Ideal component values!
Available component values!
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CLK BPF Characteristics
S22
S11
0.2 0.4 0.6 0.8 1.0 1.2 1.40.0 1.6
-20
-15
-10
-5
-25
0
freq, GHz
Mag
nitu
de, d
B
23
Time-domain Characteristics
6 84 10
-400
-200
0
200
400
-600
600
time, nsec
var(
"I-n
eg
"),
mV
var(
"I-p
os"
), m
V
0o 0o
0o180o
0o 0o
0o180o
LPF
LPF
BPF
BPF
THAMESASIC
I+
I-
CLK+
CLK-
RF SignalGenerator
Port Imp. = 50
RF SignalGenerator
Port Imp. = 50
Test FixturePCB
6 84 10
-400
-200
0
200
400
-600
600
time, nsec
var(
"CLK
-neg
"),
mV
var(
"CLK
-pos
"),
mV
I-pos
I-neg
CLK-pos
CLK-neg
24
Test Fixture - Device Interface board (DIB)
Keep symmetrically disposing the differential-analog-input subsystems
Balancing all parasitics
Routing high speed digital signal traces away from the sensitive analog traces, clock, and reference lines Minimize undesirable crosstalk
Optimizing routes for the clock and analog input Minimize unwanted signal skew and phase mismatch
Total DIB (PCB) thickness: ~ 64.4 milPCB material : FR-4 6 layer PCB(64.4x25.4/1000 ≈ 1.64 mm)
25
Test Rack (Test Bench)
Host Computer
Spectrum Analyzer
TemperatureChamber
Test Fixture
RF Balun
Digital Mutli-meter
Digital Logic Analyzer
Power Supply
26
DVT Configuration
Configuration for the HNS high speed ADC verification tests
800 MHz sate analysis function
27
High Speed ADC DVT Methodology• Test program: ADC verification software suite (VTS)
– Single-tone ADC tester– Two-tone ADC tester
• Fast Fourier transform based• Auto test equipment (ATE)
– Post processing parameter extraction performance analysis
• Static/Dynamic ADC test– Static
• Ramp-based method to determine the ADC output transition levels• Time consuming• Can not verify a real ADC performance for modern satellite receiver application.
– Dynamic• Critical ADC parameters for the receiver• Only obtained by under dynamic drive conditions• Fast Fourier transform module as a foundation of dynamic ADC testing
• High quality, high volume, low-cost production test applicationsfor a modern satellite receiver
28
Verification Test Software (VTS) Suite
Features:• Integrated coherent sampling calculator• Integrated ideal ADC simulator• Integrated windowing function for the input signal • Fast ADC function parameter extractions
ADC Dynamic Performance
Signal-to-Noise Ratio (SNR)Signal-to-noise and distortion ratio (SINAD) Effective number of bit (ENOB)Spurious free dynamic range (SFDR)Total harmonic distortions (THD)Code-width and offset
• Differential nonlinearity (DNL)• Integral nonlinearity (INL)
Inter-modulation distortion (IMD) & 3rd orderIntercept point (IP3) and two-tone SFDR
Uniqueness:• Full input channel sampling diagnosis
• Handling ADC input signal frequency leakages• VTS can be extended to characterizing the full input channel
sampling.• Sampling signal windowing function & Leakage handling
- Hanning, Hamming, Blackman, Kaiser and etc. - Adding cost effective ATE setup for input signal generator for higher resolution ADCs (> 8bits)
• Matlab GUI for easy program access and handling• Advanced mixed-signal testing features are mostly
integrated to this VTS suite so that any of test engineer can run the testing and verification.
29
How VTS Suite Works?
Coherent Calculator&
Test tone setup
Manual or Labview BasedATE approach
30
ADC DVT with a Single-tone
Code density test Linearity test
Code error testSine wave reconstruction test
Power spectrum test
31
Fast Fourier Transform – Mixed-signal Test
Full-scale RMS Signal Level
RMS Noise Level (DC to )
SNR (SINAD)
FFT Processing Gain
Sign
al L
evel
(dB
)
Frequency ( f )
FFT Noise Floor
sample
sample
fN
⎛ ⎞⎜ ⎟⎜ ⎟⎝ ⎠
2samplef
2sample sample
sample
f fN
⎛ ⎞−⎜ ⎟⎜ ⎟
⎝ ⎠
1010 log2
sampleN⎛ ⎞= ⎜ ⎟
⎝ ⎠
27dB for Nsample = 102430dB for Nsample = 204833dB for Nsample = 409640dB for Nsample = 16384
Example)
f
SINAD = ENOB x 6.02 + 1.76
0 (DC)
Power spectrum test
32
VTS data capture & FFT Enhancement
• Conventional Mixed-signal FFT– Capture node voltage– Convert to dBV unit
after carefully consider measuring VRMS
Drawback:• VRMS is may not easy to
monitor under the load impedance is unknown.
• Thesis approach– Just capture quantized
samples– Directly, process the
quantized decimated signal (no-voltage conversion)
• No-additional binary digitized signal to VRMS Conversion
– Normalized to input signal after FFT
– Calculate all dynamic parameters
33
Spectral Leakage and Harmonics
Ideal sine wave No leakage !!No Harmonics !!
Mini-me, CorruptTest tones and fixture!
I will do a windowing!Groovy, Baby!
34
Coherent Sampling and FFT
35
Non-coherent Sampling and FFT
36
Handle Leakages by Windowing
• Strong interfering frequency component from the test tone Blackman or Hanning
• Strong interfering frequency component closed to the test tone Blackman
• Interest frequency band contains 2 or more signals close to each other – Increase spectral resolution
– Narrow main lobe Rectangular or Hamming
37
ADC DVT with a Single-tone SinewaveADC Input Power & Bandwidth Test
single-tone sine wave sampling at 800 MS/s
Signal-to-noise-and-distortion vs. input power Effective-number-of-bit vs. input power Spurious-free-dynamic-range vs. input power
Effective resolution bandwidth – SINAD vs. Analog input frequency
Is this enough for verify the design and its system applications for communication?
38
System Non-linearity & Distortion
39
Amplifier Power Plot – Pin vs. Pout
y = x + b1
y
x
y = 3x + b3
Amplifier Linearity!
T/H Amps. & Comparators...
40
ADC DVT with 2-tone Signal
0
5
10
15
20
25
30
35
40
45
-45 -35 -25 -15 -5
Pin [dBFS]
SFD
R [d
Bc]
0
5
10
15
20
25
30
35
40
0 5 10 15 20 25 30 35 40 45 50
Pin [dBm]
Ana
log
equi
vale
nt P
out [
dBm
]
Fundamental IMD3 IMD3-extapolateIMD3-L-extract Linear (Fundamental) Linear (IMD3-extapolate)Linear (IMD3-L-extract)
ADC hard limitBeyond input FS
two-tone sine wave sampling at 800 MS/s
Slope 3Slope 1
41
Production Tests
High-speed ADC – wafer & final production test list
Continuity & IDDQ testing failed die
Wafer MapBlack squares are Continuity & IDDQ testing failed dies
42
IDDQ Test – Leakage Current
Fault-free Leakage current between output and GND
Leakage current between output and VDD
Digital IDDQ
Part of Go/NoGo Test
43
ESD diode leakage Current
VDD 1 BUS VDD2 BUSVSS1 BUS VSS2 BUS
VSS_ESD BUS
SEAL RING
PADVSS1 PAD
I/O-1PADVDD1
PADVSS
PADVDD2
PADI/O-2
PADVSS1
DP3DP3DP3DP3 DN2
DP2DP2
DN2
Power Clamp
Process Design Kit (PDK)recommended ESD protection
Providing p-cell libraries
44
Summary of Test Results
0.350.130.290.330.280.260.280.21DNLMAX[LSB]
1.762.011.341.850.980.860.880.45INLMAX[LSB]
0.4-0.5-0.3-1.0-0.9-1.8-1.0-2.2Offset [LSB]
-24.56-25.27-25.41-26.13-28.87-29.63-38.18-41.89THD [dB]
32.9533.1133.7233.6634.9134.8335.8135.68SNR [dB]
23.9625.5624.8025.3727.7228.4333.5834.55SINAD [dB]
3.813.823.954.084.434.605.405.62ENOB [Bits]
QIQIQIQIChannel
250 MHz200 MHz100 MHz10 MHzFrequency
• Measurement range are targeting within the application signal bandwidth from 10 MHz ~ 250MHz
• DUT (HNS high speed ADC) operates mostly linearly under the input power level below 5 dBFS
• Code error test is useful to determine the presence of the timing error
• Testing in the temperature extremes at 250 MHz (ENOB at -40 oC: 4.99 [Bits], ENOB at +80 oC : 3.35 [Bits])
45
Sensitivity Analysis of High-speed ADC
• Definition of “corner lot”a wafer fabrication where the process is deliberately skewed to producea certain wafer, so that ASIC performance can be physically evaluated at process extremes
• Temperature, process parameters, etc.
Design Matureness and process stability
• Hypothesis :THAMES ADC consists of major two subcomponent devices – passive & active
Passive – resistors Active – BJT gain (β) and emitter area sizeADC performances are affected by over-all passive and active component behavior!
• Corner study test description:– ADC Functional DC tests and dynamic performance tests– Numerous testing and statistical data analysis
46
Corner Lot Splits
LTL UTL
Measurement Result
MeanAT46000 BiCMOS Technology
47
High-speed ADC Yield
DUT-to-DUT mean and standard deviation determine yield
LTL: lower test limitUTL: upper test limit
48
Process Stability & Design Matureness
CenteringVariability
Conclusion
ConsistantConsistent
Stable
InconsistentConsistentUnstable
DriftingConsistentUnstable
ConsistentInconsistent
Unstable
InconsistentInconsistent
Unstable
Statistical MeasurementGaussian distribution
49
Process Capability, Cp
LSL USL
Gau
ssia
nM
easu
rem
ent
PD
F, f(
x)
Measurement Result
Mean
6-σ quality standard low defect rates ( < 3.4 defect parts per million)
6pUSL LSLC
σ−
=
USL : upper specification limitLSL : lower specification limit
THAMES ASIC: Cp > 4 Marginal rating!
50
Statistical Measurement ExampleLot 1
Lot 2
Lot 3
Lot 4
Lot 5
Lot 6
Lot 7
Lot 8
Lot 9Vin_R
F(I-)
bia
s vo
ltage
mea
sure
men
t
51
ENOB for Each Lot Split
10MHz ENOB Average
4.80
4.90
5.00
5.10
5.20
5.30
5.40
5.50
5.60
5.70
5.80
5.90
Lot 1 Lot 2 Lot 3 Lot 4 Lot 5 Lot 6 Lot 7 Lot 8 Lot 9
Corner Lot Number
ENO
B
I-channel Q-channel
100MHz ENOB Average
3.60
3.80
4.00
4.20
4.40
4.60
4.80
5.00
Lot 1 Lot 2 Lot 3 Lot 4 Lot 5 Lot 6 Lot 7 Lot 8 Lot 9
Lot variation
ENO
B
I-channel Q-channel
200MHz ENOB
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
Lot 1 Lot 2 Lot 3 Lot 4 Lot 5 Lot 6 Lot 7 Lot 8 Lot 9
Lot variation
ENO
B
I-channel Q-channel
250MHz ENOB
0.00
0.50
1.00
1.50
2.00
2.50
3.00
3.50
4.00
4.50
5.00
Lot 1 Lot 2 Lot 3 Lot 4 Lot 5 Lot 6 Lot 7 Lot 8 Lot 9
Lot variation
ENO
B
I-channel Q-channel
52
Summary
• Statistical process control corner lot study– Evaluate the quality of the process for high-speed ADC
manufacturing– ADC test and measurement equipment effect included– Stability of high-speed ADC manufacturing process
• ENOB Corner lot study result:– Lot 6 split has the best performance
• Normal value (μ) of passive components • UTL of BJT-β (high gain) • LTL of BJT emitter size (low parasitic junction C)
Linearity of the active component effect !!
53
Conclusions
Achievements:• Enhancements due to DfT:
– Testability– Calibration and on-bench debugging– Cost effectiveness of testing in manufacturing.
• A step-by-step sequence of operations for dynamic performancetesting of high speed ADC (dual channel, 6-bit, 800 MS/s)
• Test methodology for reducing test costs and overcoming test hardware limitations
August 14, 2007
Actual ADC mounted onSpaceway indoor receiver
• Verification tool development – VTS suite
• High-speed ADC design parameter sensitivity Corner lot study
• Production test ready ( approach to ATE )
54
THANK YOU
&
Questions?
55