high speed layout analog

高速模拟集成电路的版图优化

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Layout Optimization in High Speed Analog Integrated Circuit


Yuanjun Liang

ABSTRACT Layout parasitics can significantly affect the performance of analog integrated circuits (ICs), especially in high speed circuits’ bandwidth. This paper identifies what parasitics impact on the high speed circuits; presents some optimizes methods in layout to reduce the parasitics affection; illustrates a high speed limiting amplifier in layout optimization.KEYWORDS High speed analog integrated circuits (ICs); IC layout; parasitics; limiting amplifier

摘要模拟集成电路的性能很容易受到寄生参数的影响而变差，带宽是高速模拟集成电路最重要的指标之一，而带宽也最易受到寄生电阻和电容的影响。本文分析了寄生参数产生的来源，提出了优化电路版图，减小寄生参数的方法。最后给出了一个高速的限幅放大器的实例。关键词高速模拟集成电路；版图；寄生参数；限幅放大器

I Introduction

Performance of analog ICs is significantly affected by layout parasitics, including both device and

interconnects parasitics. Layout parasitics impact on circuit performances like gain, bandwidth, phase margin, etc. In high speed circuit, such as optical communication circuit, bandwidth is one of the most important factors because of intersymbol interference (ISI) [1]. Ignoring these parasitic effects during circuit optimization, but after layout, parasitics may result in failure for the target circuits. To achieve the desired specifications, this paper discusses how to constrain parasitics in the optimization of analog IC layouts. This includes the following two major aspects: 1) identifying the parasitic-sensitive parts of the circuits and which parasitics mainly affects the performance of circuit, mostly parasitic capacitance and resistor impact on the bandwidth of high speed circuit; 2) determination of geometric of circuit due to parasitics, symmetry, matching, relative placement, proximity, device/wiring alignment, and design rules.

The rest of this paper is organized as follows. In Section II, the parasitics of layout is formulated and modeled. In Section III, the mainly parasitics works on in high speed circuit are identified. Section IV gives an example of parasitics optimization in high speed circuit. Section V shows the experimental results. Finally, the conclusions are drawn in Section VI.

II Parasitics in Layout

Parasitics of analog ICs layout includes both device and interconnect parasitics.

1DeviceParasitics Some parasitics from devices are mainly determined by their structures. For MOSFET transistor, the number of fingers indicates overall area and perimeter of drain and source, which, in turn, determine drain-to-bulk and source-to-bulk capacitances. These values can be approximated based on geometry and finger number of the transistor. Fig 1 shows a transistor layout and its extracted parasitic model.

Fig.1. Layout of MOSFET and its parasitic model

f :number of figuresW :figure widthL :channel lengthd :diffusion distance

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Vol. 3 No.3 / Mar. 2009

Rg :poly gate resistanceCgd :gate-drain capacitanceCgs :gate-source capacitanceCdb :drain-bulk capacitanceCsb :source-bulk capacitanceThe gate resistance Rg is calculated based on [2]. The gate to source and drain capacitance Cgs and Cgd are determined only by W*L, has nothing to do with layout. The diffusion to bulk capacitances, Cdb and Csb, are approximated in terms of areas and perimeters of the drain and source (indicated as As, Ad, Ps, and Pd). Since the drain and source areas of MOS transistors are not specifically assigned in the layout, to simplify the equation for any number of fingers, the approximate areas and perimeters can be calculated as

Ad =As = wd(f +1)/(2f) (1)

Pd =Ps = d(f +1 ) + wf (2)

The values of parasitics in passive devices can be formulated in a couple of ways. If the device is selected from a design library, its parasitic values are already known based on the equivalent circuit structure of that device. Otherwise, parasitics can be expressed in geometric formulas of resistance, capacitance, and inductance [3]. Besides parasitics of devices themselves, matching between device parasitics are also crucial in some sensitive circuits. Matching those parasitics can be achieved by selecting identical device structure and imposing device-matching constraints.

2 MOSFETConnectedLayoutFig 2 shows a connected layout of a MOSFET. Besides the device parasitics considered in 1, other geometries gate and drain and source connection in the layout have to be also included in the parasitic calculation.

The gate and source/drain connection also have their parasitic resistance and capacitance. Fig 3 shows the equal resistance net of gate connection

Where ρ is the sheet resistance per unit square of poly gate, When the gate figure is more than 10, the resistance

of the gate can be expressed as follow

(3)

From (3), R is a fixed value when figure added, to reduce R, reduce width and increase figures.

The capacitance of gate-connection capacitance can be calculated as follows [4]

(4)

Ca is substrate capacitance per unit area, Csw is sidewall substrate capacitance per unit length.

For the metal drain/source interconnects in Fig 2, the R can be neglected because metal’s sheet resistance per unit square is very small with salicide technology which is widely used in fabricate process, it is about 0.08 ohm per unit square. The mainly parasitics is the capacitance between metal and substrate, the can be calculated using the following formula

(5)

Where is the capacitance per unit square of metal, and Stot is the total area of metal

(6)

3InterconnectParasiticsInterconnect parasitics consist of wire resistance, wire substrate capacitance, and coupling (or called crosstalk) capacitance between wires. Those parasitics can be calculated as

R =ρ× (length/width) (7)

Csub=ca×(length×width)+csw×(2×length) (8)

Ccoup =cc×(length/distance) (9)

Where cc is coupling capacitance per unit length. Also the R of the interconnection wire can be neglected. The mainly parasites is capacitance of interconnection wire [5]

Fig.3. Equal resistance net of gate connectionFig.2. Layout of MOSFET with gate/source/drain connection


37

VDD

MN1 MN2

R

ID

R

MN3 MN

R

ID

R

ID1

MN5 MN6VIN

VOUTNegative feedback

name valueM1~M4 36u/0.18uM5~M6 15u/0.18u

ID 6mAID1 0.6mAR 150ohm

Gives the detailed calculation method.

III Parasitics Affects High Speed Circuit

In high speed circuit, bandwidth is one of the most important factors and very sensitive to parasitic

resistance and capacitance due to Low-Pass filter phenomenon [6].

Fig 4 is a simple RC Low-Pass filter, if the RC time constant is too big, when a random binary data comes in vin, the output vout, as illustrated in Fig 4 (b), for a single ONE followed by a ZERO, the output does not close to V0, but for two consecutive ONEs, it does. A similar effect occurs for ZEROs as well. This phenomenon is undesirable because it makes decision hard in the fowling circuit.

To reduce this, both parasitic resistance and capacitance need to reduce.

Fig.4. (a) Effect of low pass filter (b)Random data through the low pass filter

Power integrity is another problem in layout, in most circuit power lines need run large DC current, if the power line parasitic resistance becomes obviously big, there is DC voltage land on power lines, reduce power on the core circuit, this affect circuit performance, so this need to reduce parasitic resistance.

Parasitic resistance and capacitance has such serious affection on high speed analog ICs, especially on the signal path that these parasitics need to be reduced as small as possible.

1): To lower parasitic resistance, from (3), R3 and R1, R2 should be reduced. For a given total gate width, use more figures to get a shorter width of every single figure width, this lower R1, which is the main parasitic resistance compare to R1 and R2. To reduce R1, reduce the distance between active region of MOSFET and gate connection d2, the minimum value of d2 may be restricted by design rule of certain PDK (process design kit). R2 can be lower by using metal connect each figure instead of poly. Increasing contact number between poly and metal also reduces R2.

2): To lower parasitic capacitance, from (4) ~ (6), figures f must be reduced as small as it can be, this conflicts with 1). Compromise is needed here; figures

can not be too much or too little. If parasitic resistance affects more than capacitance, then increase the figures, and it does in the reverse way when parasitic capacitance affects more.

3): for interconnection wire, its parasitic resistance is so low that can be ignored. Try best to reduce its parasitic capacitance [6]

IV LA Example

This section illustrates an example in high speed circuit. High-speed limiting amplifier (LA) [1] plays

a critical role in various communications. It amplifies the weak signal to deliver a large output swing for the succeeding data recovery circuits. Fig 5 shows the block diagram of a typical optical communication receiver.

Fig. �. an optical communication receiver

In optical receiver system, LA’s bandwidth needs achieve data rate to get optimized signal quality and noise figure. In conventional LA circuits, the architecture with cascaded gain stages is widely used to achieve a high gain and a broad bandwidth simultaneously. A cascade of identical gain cells, each having a bandwidth BW, exhibits an overall bandwidth of

(10)

Where BWtot is the bandwidth of the unit gain cells, m is equal to 1 for first-order stages and 2 for second-order stages

Taking BWtot=5 GHz and n=5 as an example, the BWcell bandwidth must exceed 13, 8, and 6.8 GHz for m= 1, 2, and 3, respectively.

For power dissipation consideration, second-order LA is selected to achieve high bandwidth, the gain cell of LA architecture of the circuits is as follow,

Fig. 6. gain cell of limiting amplifier

VDD

MN1 MN2

R

ID

R

MN3 MN

R

ID

R

ID1

MN5 MN6VIN




VDD

MN1 MN2

R

ID

R

MN3 MN

R

ID

R

ID1

MN5 MN6VIN




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Vol. 3 No.3 / Mar. 2009

Using negative feedback to increase the bandwidth, for BWtot=5 GHz and n=5, BWcell bandwidth is about 8GHz, based on SMIC 0.18 Mixed Signal process design kit, using Cadence Spectre as simulation tool, the parameter of each MOSFET is in Table 1 The negative feedback is very sensitive of parasitic resistance and capacitance, considering symmetry, matching, relative placement, proximity; the following layout is used in Fig 7. To reduce parasitics, MOSFET M1~M6’s figure f is variable. The next section will illustrates result.

V Expetimental Result

After layout, the postsimulation gives the result, the bandwidth changes with the value of figure

parameter f changes

From Fig 8, f=12 is an optimized value for layout, f=12, -3dB bandwidth is 7.5GHz. When f=3, the bandwidth is only 4.4GHz, nearly 4 GHz lower than presimulation result (8GHz), f=3 the figure width is 12um, which brings significant large parasitic resistance, this reduce bandwidth obviously. Figure numbers increases, figure width decreases and parasitic resistance decreases, so the bandwidth changes from 4.4GHz to 7.5GHz, but when f=18, the bandwidth doesn’t rise up, this is because parasitic capacitance affects more than parasitic resistance.

VI Conclusion

Bandwidth is a critical parameter in high speed analog ICs, layout parasitic capacitance and resistance

have significant impact on it. This paper presents some

optimization methods to reduce parasitic capacitance and resistance in high speed analog ICs, and also points out that when reducing these parasitics, compromise is necessarily needed.

REFERENCES[1] S. Galal and B. Razavi. 10-Gb/s limiting amplifier and laser/

modulator driver in 0.18um CMOS technology.

[2] B. Razavi, Design of Analog CMOS Integrated Circuits. New York:McGraw-Hill, 2001.

[3] C. De Ranter, G. Van der Plas, M. Steyaert, et al. CYCLONE: Automated design and layout of RF LC-oscillators. IEEE Trans. Comput.-Aided Design Integr. Circuits Syst., vol. 21, no. 10, pp. 1161–1170, Oct. 2002.

[4] Lihong Zhang, Jangkrajarng, N.,Bhattacharya, et al. Parasitic-Aware Optimization and Retargeting of Analog Layouts: A Symbolic-Template Approach Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on Volume 27, Issue 5, May 2008 Page(s):791 - 802.

[5] T. Sakurai. Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSI’s. IEEE Trans. Electron Devices, vol. 40, no. 1, pp. 118–124, Jan. 1993.

[6] B. Razavi , Des ign of in tegra ted c i rcui t s for opt ica l communication. New York: McGraw-Hill, 2003.

作者简介

梁远军博士研究生。2006年获电子科技大学微电子学与固体电子学学士学位。目前研究方向为模拟电路设计及系统级封装仿真。

VDD

MN1 MN2

R

ID

R

MN3 MN

R

ID

R

ID1

MN5 MN6VIN




Fig.8. Bandwidth of LA gain cell versus with MOSFET figures

Table 1 Parameter of LA

Fig.7. layout of LA gain cell

high speed layout analog

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