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Богданов и партнеры

Богданов и партнеры 1

How to Tame a Gorilla ProgramCritical Path 2.0 case study at SanDisk

ProjectPro Corp.www.ProjectProCorp.com

� President ProjectPro Corp.

� Specializes in Microsoft Project and Project Server

Presenter Intro: Eric Uyttewaal, PMP

� BS, EngineeringMS, Business Administration

� Author “Forecast Scheduling with Microsoft Project 2010” & “Dynamic Scheduling with Microsoft Office Project 2003”

� Formerly: Executive Director at IIL as developer and manager of the Orange, Blue, Black Belt certification curriculum

� Email: [email protected]

� Tel: 613-692-7778



Presenter Intro: Al Rusnak, PMP

� ASIC Program Manager at SanDisk®

� Specializing in Scheduling and Risk Analysis

� Lead scheduler on mission-critical programs

� Degrees:

� BS, Electrical Engineering

� MS, Electrical Engineering

� Email: [email protected]

� Tel: 408-801-1613

What Situation Are You In?

Single, Isolated Project

Master- orSubproject

No Resource-loading A B

Resources & Workload-leveled C D



AssignmentsTeam Members

What is a ‘Program’?

StrategyExecutives

ProgramsProgram Managers

ProjectsProject Managers

PortfoliosPortfolio Managers

The Challenge of Scheduling Programs



Drowning in the Data?

The SanDisk Situation: As-Is and As-Needed

� As-Is:

– “System” is not linked to show interaction between schedules

– Manual syncing of dates

– Schedules are often suspected of being out-of-date

– Resource availability drives schedules

– “System” is labor-intensive

– Critical Path 1.0 technology

� As-Needed:

– See complete CP across resource-leveled projects in program

– Find that CP in an easy way: Critical Path 2.0 technology

– Optimize the CP

– Critical Path 2.0 technology



The Program Was Considered to Be “In Control” When (Verbatim)

� The program schedule has at least ten major milestones (ten sub networks)

� All subproject schedules are dynamic models that forecast the subprojects

– “Forecast Scheduling with Microsoft Project 2010 ” checklist

� We have a detailed Critical Path to the next two major milestones

� We have 90% confidence level (simulation) the next 2 major milestones would be completed on time

� We have a high-level Critical Path (deliverables only) for entire program that forecasts on-time completion

1 of 2

The Program Was Considered to Be “In Control” When (Visually) 2 of 2

?? % on time????

90% probability on time








90% on time!!!



Our Reasons to Divide the Program into Multiple Subprojects

� Delegate to a scheduler closer to the work

� More than 2,000 tasks in the program

� Multiple people need to update the master schedule

� People are in different countries, in different time zones and speak different languages

Consequences of Multiple Subproject Schedules

� Multiple schedulers have to adhere to scheduling guidelines for the program

� Dependencies between schedules and a Critical Path that runs across schedules

� Sharing resources across subprojects, perhaps even across programs



Why Re-integrating the Subproject Schedules?

Integrated Master Schedule

Subprojects with cross-project dependencies

1. Identify and optimize the Critical Path into next milestone(s)2. Determine appropriate buffers (deadlines) for handoffs3. Report accurate forecasts on the program as a whole

Integrated Master Schedule (IMS) and Program Critical Path

Subproject A Subproject B Subproject C

Integrated Master Schedule (IMS)



Options for Managing the Dependencies between Subprojects

1. Do Not Model Them- Coordinate dates manually in regular meetings!- no Critical Path

2. Model them using Deliverables feature- no Critical Path

3. Model them using Links-between-Projects feature- Links lost, duplicated or slow

4. Model them using PPMS add-in(ProjectPro Program Management Solution)+ Critical Path, links protected

PPMS Example Program “Write Book”



PPMS: Identifying the Handoffs

Provider Project: ‘Publishing’ Receiver Project: ‘Authoring’

OutlinePublisher hands ‘Outline’ to Authors

Task Name Handoff

Outline‘Outline’ received from publisher by Authors

Task Name Handoff

PPMS Excel Dashboard - Lists all Handoffs (Links between Subprojects)

Dashboard Handoffs Program ‘Write Book’



Demo PPMS

How the IMS is Generated

� Create project files at function level

� Identify all cross-project milestones in .MPP’s

� Copy cross-project dependencies to .XLS file

� Create cross-project links with PPMS

� Level workloads at the program level

� Identify Resource-Critical Path with CCP

� Optimize Resource-Critical Path

� Simulate to get high-confidence date (project buffer)



Dealing with Shared Resources

� Model with Generic Resources first!

� Optimize the IMS:

1. Adding idle resources to the most-Critical Path(s)

2. Moving resources from non-Critical to Critical Paths

3. Continue until resourcing is (perfectly) balanced

How Leveling Affects the Critical Path 1.0

Harry 9 D

Harry 6 D

write X

write Y

Harry 9 D

leveling

Harry 9 D

Harry 6 DHarry 6 D

write X

write Y

Before leveling:

After leveling:



How Leveling Affects the Critical Path 1.0

Harry 9 D

Harry 6 D

write X

write Y

Harry 9 D

leveling

Harry 9 D

Harry 6 DHarry 6 D

write X

write Y

Before leveling:

After leveling:

Resource Dependencies Differ from Logical Dependencies

A logical dependency imposes the sequence:

Harry

Harry

Write X

Write Y

Harry

Harry

Write X

Write Y

Write

Print

OR

A resource dependency is a relationship between two activities where the sequence can be switched. The relationship is the sharing of the same resource:

Source: Forecast Scheduling with Microsoft Project 2010



Hunting for the Critical Path in an IMS

� Demo CCP in IMS

ID Handoff Codes Schedule Code

Blocks Name Resource Names DurationStart Finish Total Slack

77 Start AS Start PM 0 days 1/2/12 1/2/12 106.13 days

39 Start SY Start 0 days 1/2/12 1/2/12 96.13 days

274 AS Blk5 L3 - FE View s, IO, Preliminary IP IO 0 days 6/29/12 6/29/12 40 days

276 AS Blk5 L3 - BE View s, IO, Preliminary IP IO 0 days 6/29/12 6/29/12 40 days

282 AS Blk5 Top Integration for Subsystem Design 3 days 6/29/12 7/3/12 40 days

290 AS Blk5 Top Integration Design 1 day 7/4/12 7/4/12 346 days

328 AS Blk1 Alpha Release, Final Spec Design 0 days 7/14/12 7/14/12 21 days

344 AS Blk1 Top Integration for Subsystem Design 4 days 7/16/12 7/19/12 21 days

346 AS Blk1 BIST Setup DFT 2 days 7/20/12 7/23/12 21 days

347 AS Blk1 BIST Analysis DFT 3 days 7/24/12 7/26/12 21 days

348 AS Blk1 RTL vs. BIST RTL Formal AnalysisDFT 2 days 7/27/12 7/30/12 21 days

349 AS Blk1 Preliminary RTL w ith BIST inserted completeDesign 0 days 7/30/12 7/30/12 21 days

432 AS MS L3 - Preliminary RTL w ith BIST InsertedDesign 0 days 7/30/12 7/30/12 21 days

575 AS Top Top Integration Design 2 days 7/31/12 8/1/12 21 days

576 AS Top Preliminary RTL Design CompleteDesign 0 days 8/1/12 8/1/12 21 days

763 AS Top RTL Verif ication, Preliminary Verif ication 24 days 8/2/12 9/4/12 35 days

764 AS Top RTL Verif ication, Trial Verif ication 39 days 9/5/12 10/29/12 35 days

770 AS Top RTL Verif ication, Final, High PriorityVerif ication[200%] 43 days 10/30/12 12/27/12 40 days

771 AS Top RTL Verif ication, Final, Low PriorityVerif ication[300%] 48 days 10/30/12 1/3/13 35 days

772 AS Top Complete RTL Verification Verif ication 0 days 1/3/13 1/3/13 35 days

704 AS Top Final Layout Complete PD 0 days 1/22/13 1/22/13 22 days

705 AS Top Tapeout, Base Layers PD 0 days 1/22/13 1/22/13 22 days

905 AS P0 GDSII into JDV Process 4 days 1/23/13 1/28/13 22 days

906 AS P0 JDV, Base layers Process 3 days 1/29/13 1/31/13 22 days

907 AS P0 Mask Generation, Base layer, 1st maskProcess 7 edays 1/31/13 2/7/13 32.63 edays

908 AS P0 Minesw eeper, Metal Layers Process 4 edays 2/7/13 2/11/13 32.63 edays

909 AS P0 Wafer Fab, P0, FE Process Fab[1] 15 edays 2/11/13 2/26/13 32.63 edays

910 AS P0 Wafer Fab, P0, BE Process Fab[1] 15 edays 2/26/13 3/13/13 32.63 edays

911 AS P0 Shipping ef fort at Fab Process 3 days 3/14/13 3/18/13 22 days

20 WaferOutP0 AS Wafer Out, Rev P0 (Assumes SHL cycle time)Process 0 days 3/18/13 3/18/13 22 days

14 WaferOutP0 PK Wafer Out, P0 0 days 3/18/13 3/18/13 22 days

53 PK Assembly SDSS (PK) 10 days 3/19/13 4/1/13 22 days

54 PK Ship to US Package Designer 2 days 4/2/13 4/3/13 22 days

20 EVTPartsP0Pack PK EVT Parts, P0 0 days 4/3/13 4/3/13 22 days

55 PK Assembled 256 BGA Parts delivered 0 days 4/3/13 4/3/13 22 days

832 EVTPartsP0Pack AS Ship P0 Pkg Ship [0.1],Pkg 1 day 4/4/13 4/4/13 22 days

833 AS Test (No testing for EVT parts)PE 0 days 4/4/13 4/4/13 22 days

834 AS EVT (Blind Build) Parts availablePE 0 days 4/4/13 4/4/13 22 days

947 AS Parts for Fast Chaz Test (ASIC) 0 days 4/4/13 4/4/13 22 days

949 AS Ship Parts to SDIL for IP validationPE 2 days 4/5/13 4/8/13 22 days

950 AS Fast Chaz PLM SD 10 days 4/9/13 4/22/13 22 days

951 AS SDIL Fast Chaz completed PLM SD 0 days 4/22/13 4/22/13 22 days

971 AS Fast Chaz completed Characterization 0 days 4/22/13 4/22/13 22 days

973 AS Design Updates IP 2 w ks 4/23/13 5/6/13 4.4 w ks

744 AS Generate Split Hex File / Translate ROM Memory / IP QAIP 0.5 days 5/24/13 5/24/13 8 days

745 AS Translate ROM Memory IP 0.5 days 5/24/13 5/24/13 8 days

746 AS Layout w ith ROM change and ECOsPD 4 days 5/27/13 5/30/13 8 days

747 AS Review DRC and Generate POSPD 1 day 5/31/13 5/31/13 8 days

748 AS Metal Layer Tapeout PD 0 days 5/31/13 5/31/13 8 days

737 AS Scan pattern generation and re-simulationDFT[50%] 5 days 6/3/13 6/7/13 8 days

753 AS Scan, Full set of test vector generation / simulationDFT 15 days 6/10/13 6/28/13 8 days

799 AS DFT Vectors completed (milestone)DFT 0 days 6/28/13 6/28/13 8 days

801 AS Test Program release ef fort for EVT, release ATest (ASIC) 15 days 7/1/13 7/19/13 8 days

802 AS Test Vectors Released, Final TestTest (ASIC) 0 days 7/19/13 7/19/13 8 days

877 AS Test PE[50%] 3 days 7/22/13 7/24/13 8 days

67 DVTPartsA AS Rev A DVT Parts Test (ASIC) 0 days 7/24/13 7/24/13 8 days

878 AS P1 DVT Parts available PE 0 days 7/24/13 7/24/13 8 days

12 DVTPartsA FW DVT Parts, Rev A 0 days 7/24/13 7/24/13 8 days

140 FW Unit Test Resource5 2 days 7/25/13 7/26/13 8 days

147 FW Read ID Resource5 2 days 7/29/13 7/30/13 10 days

148 FW Read Device Parameters Resource5 2 days 7/31/13 8/1/13 8 days

149 FW Get Debug Data Resource5 2 days 8/2/13 8/5/13 6 days

177 FW Bench Test Resource12 3 days 8/6/13 8/8/13 6 days

178 FW Unit Test (Get config commands)Resource12 2 days 8/9/13 8/12/13 6 days

25 FWRelease FW FW Release, System 0 days 8/12/13 8/12/13 6 days

11FWRelease QU FW Release, System 0 days 8/12/13 8/12/13 6 days

29 QU Dow n Load Code System Engineer (QU) 2 days 8/13/13 8/14/13 6 days

38 QU Test w ith Supply #1 Host System Engineer (QU) 5 days 8/22/13 8/28/13 46 days






44 QU Compatibility Testing Complete System Engineer (QU) 0 days 10/2/13 10/2/13 21 days

30 QU Test at Room Temperature System Engineer (QU) 5 days 10/3/13 10/9/13 16 days

31 QU Test at High Temperature System Engineer (QU) 5 days 10/10/13 10/16/13 11 days

32 QU Test at Low Temperature System Engineer (QU) 5 days 10/17/13 10/23/13 6 days

102 CompatComplete SY Compatibility Testing Complete System Engineer (SY) 0 days 10/23/13 10/23/13 6 days

104 SystemQualCompleteSY L3 - System Qual Complete System Engineer (SY) 0 days 10/23/13 10/23/13 6 days

14 CompatComplete QU Compatibility Testing Complete 0 days 10/23/13 10/23/13 6 days

18 SystemQualCompleteQU System Qual Complete 0 days 10/23/13 10/23/13 6 days

45 QU System Qual Complete, Rev A System Engineer (QU) 0 days 10/23/13 10/23/13 6 days

Buffer 128.1 d with task 274

No Predecessor

SNET Constraint: Jun 29

SNET Constraint: Jun 29

Res. dep. of Design, Buffe r 7 d w ith assignment De sign on task 328

FNET Constraint: Jul 14

Weekend on calendar 'Standard'

Res. dep. of Ve rification

Buffer 14 d with assignment Verification on task 7 70

Buffer 15 eh with task 911

Elapsed duration on pred. task 910

Res. dep. of IP


Res. dep. of Resource5

Res. dep. of Resource5

Weekend on calendar 'Standard', Res. dep. of System Engineer (QU)







Weekend on calendar 'Standard', Res. dep. of Sys tem Engineer (QU)

Weekend on calendar 'Standard', Res. dep. of System Enginee r (QU)

S T M F T S W S T M F T S W S T M F T S W S T M F T S W S T M F T S WAug 7, '11 Oct 30, '11 Jan 22, '12 Apr 15, '12 Jul 8, '12 Sep 30, '12 Dec 23, '12 Mar 17, '13 Jun 9, '13 Sep 1, '13 Nov 24, '13 Feb 16, '14 May 11, '14 Aug 3, '14 Oct 26, '14 Jan 18, '15 Apr 12, '15

IMS Critical Path into Next Major MilestoneWorkload-Leveled



Critical Path Handoffs (PPMS)ID Handoff Codes Name Schedule Code Resource Names Duration Start Early Finish

681 Place and Route and Final Timing closure AS PD 10 days 12/25/12 1/7/13

698 BIST Verif ication, Gate AS DFT 5 days 1/3/13 1/9/13

703 Compressed / Non-compressed, 1st 10 patterns clean AS DFT 5 days 1/10/13 1/16/13

704 Final Layout Complete AS PD 0 days 1/16/13 1/16/13

705 Tapeout, Base Layers AS PD 0 days 1/16/13 1/16/13

905 GDSII into JDV AS Process 3 days 1/17/13 1/21/13

906 JDV, Base layers AS Process 3 days 1/22/13 1/24/13

907 Mask Generation, Base layer, 1st mask AS Process 7 edays 1/24/13 1/31/13

908 Minesw eeper, Metal Layers AS Process 4 edays 1/31/13 2/4/13

909 Wafer Fab, P0, FE AS Process Fab[1] 15 edays 2/4/13 2/19/13

910 Wafer Fab, P0, BE AS Process Fab[1] 15 edays 2/19/13 3/6/13

911 Shipping ef fort at Fab AS Process 3 days 3/7/13 3/11/13

20 WaferOutP0 Wafer Out, Rev P0 (Assumes SHL cycle time) AS Process 0 days 3/11/13 3/11/13

14 WaferOutP0 Waf er Out, P0 PK 0 days 3/11/13 3/11/13

53 Assembly PK SDSS (PK) 10 days 3/12/13 3/25/13

54 Ship to US PK Package Designer 2 days 3/26/13 3/27/13

20 EVTPartsP0Pack EVT Parts, P0 PK 0 days 3/27/13 3/27/13

55 Assembled 256 BGA Parts delivered PK 0 days 3/27/13 3/27/13

832 EVTPartsP0Pack Ship P0 AS Pkg Ship [0.1],Pkg 1 day 3/28/13 3/28/13

833 Test (No testing for EVT parts) AS PE 0 days 3/28/13 3/28/13

834 EVT (Blind Build) Parts available AS PE 0 days 3/28/13 3/28/13

947 Parts for Fast Chaz AS Test (ASIC) 0 days 3/28/13 3/28/13

949 Ship Parts to SDIL for IP validation AS PE 2 days 3/29/13 4/1/13

950 Fast Chaz AS PLM SD 10 days 4/2/13 4/15/13

951 SDIL Fast Chaz completed AS PLM SD 0 days 4/15/13 4/15/13

971 Fast Chaz completed AS Characterization 0 days 4/15/13 4/15/13

973 Design Updates AS IP 2 w ks 4/16/13 4/29/13

744 Generate Split Hex File / Translate ROM Memory / IP QA AS IP 0.5 days 4/30/13 4/30/13

745 Translate ROM Memory AS IP 0.5 days 4/30/13 4/30/13

746 Layout w ith ROM change and ECOs AS PD 4 days 5/1/13 5/6/13

747 Review DRC and Generate POS AS PD 1 day 5/7/13 5/7/13

748 Metal Layer Tapeout AS PD 0 days 5/7/13 5/7/13

736 BIST / ROM signature regeneration AS DFT[50%] 2 days 5/8/13 5/9/13

737 Scan pattern generation and re-s imulation AS DFT[50%] 5 days 5/8/13 5/14/13

796 Start Rev A test vector effort AS Verif ication 5 days 5/8/13 5/14/13

754 BIST Final test vector and LVDB generation AS DFT 3 days 5/10/13 5/14/13

753 Scan, Full set of test vector generation / simulation AS DFT 15 days 5/15/13 6/4/13

797 Develop J750 Test Vectors AS Verif ication 15 days 5/15/13 6/4/13

798 Special Functional Vectors AS Verif ication 15 days 5/15/13 6/4/13

799 DFT Vectors completed (milestone) AS DFT 0 days 6/4/13 6/4/13

801 Test Program release effort for EVT, release A AS Test (ASIC) 15 days 6/5/13 6/25/13

802 Test Vectors Released, Final Test AS Test (ASIC) 0 days 6/25/13 6/25/13

877 Test AS PE[50%] 3 days 6/26/13 6/28/13

67 DVTPartsA Rev A DVT Parts AS Test (ASIC) 0 days 6/28/13 6/28/13

878 P1 DVT Parts available AS PE 0 days 6/28/13 6/28/13

12 DVTPartsA DVT Parts, Rev A FW 0 days 6/28/13 6/28/13

140 Unit Test FW Resource5 2 days 7/1/13 7/2/13

147 Read ID FW Resource5 2 days 7/3/13 7/4/13

148 Read Device Parameters FW Resource5 2 days 7/5/13 7/8/13

Res. dep. of DFT w ith task 698

Buffer 15 eh w ith task 911

Elapsed duration on pred. task 910

Res. dep. of IP w ith task 973

Res. dep. of DFT w ith task 754


Res. dep. of Resource5 w ith task 147

T M F T S W S T M F T S W S T M F T S W S T M F T S W S T MNov 27, '11 Jan 22, '12 Mar 18, '12 May 13, '12 Jul 8, '12 Sep 2, '12 Oct 28, '12 Dec 23, '12 Feb 17, '13 Apr 14, '13 Jun 9, '13 Aug 4, '13 Sep 29, '13 Nov 24, '13

Critical Handoff Milestones

65 handoffs, but only 4 critical handoffs:



Critical Path End Date

ID Handoff Codes Name Schedule Code Resource Names Duration Start Early Finish

149 Get Debug Data FW Resource5 2 days 7/9/13 7/10/13

177 Bench Test FW Resource12 3 days 7/11/13 7/15/13

178 Unit Test (Get conf ig commands) FW Resource12 2 days 7/16/13 7/17/13

25 FWRelease FW Release, System FW 0 days 7/17/13 7/17/13

11FWRelease FW Release, System QU 0 days 7/17/13 7/17/13

29 Dow n Load Code QU System Engineer (QU) 2 days 7/18/13 7/19/13

38 Test w ith Supply #1 Host QU System Engineer (QU) 5 days 7/22/13 7/26/13


30 Test at Room Temperature QU System Engineer (QU) 5 days 8/5/13 8/9/13

31 Test at High Temperature QU System Engineer (QU) 5 days 8/12/13 8/16/13

32 Test at Low Temperature QU System Engineer (QU) 5 days 8/19/13 8/23/13





18 SystemQualComplete System Qual Complete QU 0 days 9/20/13 9/20/13

44 Compatibility Testing Complete QU System Engineer (QU) 0 days 9/20/13 9/20/13

45 System Qual Complete, Rev A QU System Engineer (QU) 0 days 9/20/13 9/20/13

Res. dep. of Resource5 with task 148

Weekend on calendar 'Standard', Res. dep. of System Engineer (QU) with task 29

Weekend on calendar 'Standard', Res. dep. of System Engineer (QU) w ith task 38








T M F T S W S T M F T S W S T M F T S W S T M F T S W S TNov 27, '11 Jan 22, '12 Mar 18, '12 May 13, '12 Jul 8, '12 Sep 2, '12 Oct 28, '12 Dec 23, '12 Feb 17, '13 Apr 14, '13 Jun 9, '13 Aug 4, '13 Sep 29, '13

Accumulated Leveling Delay = 72 days !!

NamePre-leveled

FinishPost-leveled

Finish

System Qual Complete, Rev. A 10 Jul 13 20 Sep 13

Critical Path Analysis

MS Project 1 CCP 2

Unleveled Critical Path Yes Yes

Workload-Leveled Critical Path No Yes

Elapsed durations (ed) No Yes

Multiple Calendars No Yes

Logical Dependencies Yes Yes

Resource Dependencies No Yes

Most-Critical Path No Yes

Longest-Path No Yes

1 Critical Path 1.0 compliant2 Critical Path 2.0 compliant



Tools Used

Tool Supplier

Microsoft Project 2010 Microsoft Corp.

PPMS – to Link & Unlink schedules ProjectPro Corp.

CCP – for Critical Path analysis ProjectPro Corp.

Monte Carlo Simulation Al Rusnak

Roadmap for the Pilot Program

� Forecast Scheduling and Forecasting Programs training

� Review schedules to make sure guidelines are followed

� ProjectPro provides software licenses:

– ProjectPro Program Management Solution (PPMS)

– Complete Critical Paths (CCP)

� Create the Integrated Master Schedule (IMS)

� Identify/optimize Critical Path of next major milestones

� Do this for four consecutive weeks (=CSF)

� Support from ProjectPro during the entire program



Program Schedule Process

1. Generate Project Schedules

2. Add handoff Milestones and Codes

3. Update Project Schedules and submit to repository

4. Integrate Project Schedules to Program (PPMS)

5. Find Resource-Critical Path and Optimize (CCP)

6. Des-integrate: standalone Project Schedules (PPMS)

7. Update Handoff Milestone Dates

Determining the High-Confidence Date for the Program

� Task Duration Estimates:

– 50% Confidence durations

– 90% Confidence durations

� MS Project Forecasts Finish Date (FF)

– Based on 50% confidence durations

� High-Confidence Forecast Finish Date (HCFF)

– Including 90% confidence durations in Monte Carlo simulation

– HCFF - FF = Program Buffer

� Only 1 buffer = Program Buffer



Bin Frequency Cumulative %

10/25/13 0 0.00%

10/29/13 2 0.20%

11/02/13 1 0.30%

11/06/13 1 0.40%

11/10/13 4 0.80%

11/14/13 9 1.70%

11/18/13 7 2.40%

11/22/13 35 5.90%

11/26/13 26 8.50%

11/30/13 61 14.60%

12/04/13 48 19.40%

12/08/13 76 27.00%

12/12/13 72 34.20%

12/16/13 59 40.10%

12/20/13 136 53.70%

12/24/13 65 60.20%

12/28/13 129 73.10%

01/01/14 58 78.90%

01/05/14 59 84.80%

01/09/14 50 89.80%

01/13/14 25 92.30%

01/17/14 34 95.70%

01/21/14 14 97.10%

01/25/14 12 98.30%

01/29/14 3 98.60%

02/02/14 4 99.00%

02/06/14 4 99.40%

02/10/14 0 99.40%

Time Simulation Results: Statistical Analysis - Resource leveled

25166445 System Qual Complete, Rev A

Mean 12/19/13

Standard Error .5496

Median 12/19/13

Mode 01/06/14

Standard Deviation 17.3814

Sample Variance 302.1142

Kurtosis .9349

Skewness 0.273146532

Range 145.3097222

Minimum 10/25/13

Maximum 03/19/14

Sum 41627042.5

Count 1000

Largest(1) 03/19/14

Smallest(1) 10/25/13

Confidence Level(95.0%) 1.0786

Time Simulation Results:Frequency and Cumulative Histogram



System Qual Complete, Rev. A

� Unleveled, forecast: 10 Jul 2013� Leveled, forecast: 20 Sep 2013� High Confidence: 09 Jan 2014

� Program Duration: 542 Calendar Days� Leveling Delay: +72 Calendar Days� Program Buffer: +85 Work Days

� Critical Handoffs 4 out of 65

Time Simulation Results – OverviewProof of Concept Schedules

Cost Simulation Results:Frequency and Cumulative Histogram



Cost Simulation Results on Subproject Level

Differences between Single Project Schedule and Subproject Schedule (that is part of IMS)

Single Project Subproject

• Complete Network Logic

• (Often) one Critical Path

• No external dependencies

• Multiple ending points in network

• Multiple Critical Paths

• Many external dependencies ---�



Differences Single Project versus IMS schedule

Single Project Integrated Master Schedule (IMS)

Network logicProject schedule has one ending point in its network logic

Subproject schedules have multiple ending points, but IMS has one.

Cross-project dependencies

None Many

Critical Paths of interest

One Multiple, often ten or more

Critical activities

Each schedule has critical activities

Some subproject schedules have program-critical activities, othershave none

Resource dependencies

FewMany (for product-development programs in first-to-market companies)

Situations and the Tools You Need

Single, Isolated Project

Master withSubprojects

No Resources Critical Path 1.0/2.0MS ProjectCCP recommended

Critical Path 1.0/2.0MS Project + PPMS + CCP

Resources & Workload-leveled

Critical Path 2.0MS Project + CCP

Critical Path 2.0MS Project + PPMS + CCP

CCP = Complete Critical Paths from ProjectProCorp.comPPMS = ProjectPro Program Management Solution from ProjectProCorp.com



Program Forecast Report: Buffer Consumption

Key Benefits of This Approach for SanDisk

� Provides complete Critical Paths in workload-leveled programs:

– Real visibility on the dynamics in the program

– Shows the criticality of the resources (functions)

� Allows to optimize resource needs and allocations

� Allows to recover from slippages (what-if scenarios!)

� Keeps all schedules standalone:

– schedules open fast, working offline, easy updating

� Allows project-specific resource pools or shared pool

� Provides high-confidence forecasts for product release dates



Integrated Master Schedule: Summary

� Multiple subproject files can be linked

� The real Resource-Critical Path can be identified

� Schedule delays can be decreased or resolved

� A 90%-probable commit-date can be calculated at the program level

� The program can be forecasted continuously!

Our Recommendations

1. Achieve agreement among stakeholders on when program is considered “in control.”

2. The more subproject schedules, the better

3. Protect unity of data at all cost!

4. Address differences in scheduling styles

5. Create autonomous subproject teams

6. Make resource names unique across the program

7. Use generic resources first to optimize the program as a whole (Time-to-Market!)

8. Use Critical Path 2.0 and compliant tools (CCP + PPMS)!

9. Standardize the WBS for sub schedules (see next slide)



Standardized Levels of the WBS

� Level 0 – Subprojects (=major component)

– Nouns (without verbs): e.g., ASIC, Firmware, Parts, Test Software, Reliability, Tested Parts

� Level 1 – Subcomponents

– Nouns (without verbs): e.g., for ASIC: Subsystems, Top Design

� Level 2 – Function

– Nouns (without verbs): e.g., for ASIC: Logic Design, Physical Design, FPGA Design, Documentation, Verification, Test Preparation, Package, Foundry, and Design Validation

� Level 3 – Tangible Deliverables

– Nouns (without verbs): e.g., for ASIC: Preliminary, Trial and Final RTL; Preliminary, Trial and Final Synthesis and Layout; RTL, Gate Level Verification and multiple FPGA releases.

� Lowest Level – Activities

– Use verbs (present/imperative tense)

References

1. Uyttewaal, E. (2010). Forecast scheduling with Microsoft Project 2010, Canada: ProjectPro.

2. PMI (2008). Standard for Program Management —Second edition, PMI, USA

3. PMI (2011). Practice standard for scheduling—Second edition.Newtown Square, PA: Author.

4. DCMA (2009). DCMA 14 Point Assessment materials, DCMA, USA (http://guidebook.dcma.mil/79/Online_Version_IMP-IMS_11_21_09.pptx)

5. National Defense and Industry Association (2012). Planning and Scheduling Excellence Guide (PASEG), NDIA, USA.

6. U.S Government Accountability Office (2012). General best practices for project schedules—exposure draft, GAO, USA. Retrieved from http://www.gao.gov/products/GAO-12-120G



Thank You for Attending Our Presentation!

Eric Uyttewaal, [email protected]

613-692-7778

Al Rusnak, [email protected]: 408-801-1613

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