Design of an Ultra-wideband Low Noise Amplifier in 0.13µm CMOS

Yanxin Wang, Jon. S. Duster, Kevin T. Kornegay School of Electrical and Computer Engineering

Cornell University Ithaca, NY 14850 yw86@cornell.edu

Abstract—A low noise amplifier (LNA) in 0.13µm CMOS for ultra-wideband (UWB) front-ends is presented. The LNA has a peak gain of 11.3 dB and a 3.0 – 10.7 GHz –3 dB bandwidth. Its broadband matching is better than -10 dB for S11 and -15 dB for S22. Its lowest noise figure (NF) is 2.2 dB and the average NF is 3 dB. The LNA achieves NFmin performance over the entire bandwidth by using a power-constrained simultaneous noise and input matching concept. It consumes only 4.8mW with a 1.2 V supply for the amplifier core and 1.6 mW in the output buffer. A comparison with recently published UWB LNA’s shows this design has the best overall performance among both CMOS and SiGe designs.

I. INTRODUCTION Since the FCC ruling in February 2002 that opened up

the 7500 MHz spectrum for ultra-wideband (UWB) radio, there has been a significant amount of research and development activity. The motivation for this activity is the vast potential benefit that UWB technology can provide that includes low power, high data rate, low cost, and reduced interference, all of which are crucial for applications such as wireless video conferencing, wireless projector, or multimedia content downloading.

The IEEE 802.15.3 High Rate Task Group 3a is chartered to draft a new standard for high-rate wireless personal area network (WPAN). The most current proposal for such a standard has target data transmission rates from 22 Mbps to 1320 Mbps with 2 individual bands of 3.1 – 4.85 GHz and 6.2 – 9.7 GHz [1]. To support the high end of the data rates, the radio frond-end must be able to provide a simple and cost effective solution to cover a bandwidth close to that allocated by the FCC. Uniform performance specifications must be satisfied across a large bandwidth. Due to the many possible mobile UWB applications, low power consumption is also highly desirable.

In this paper an UWB LNA implemented in 0.13µm CMOS is presented. Advanced CMOS technology makes it possible to integrate low-power, low-cost digital signal

processing units on the same die, thus reducing cost. The LNA has a flat gain in the band of interest with 3dB roll-offs at 3.0 GHz and 10.7 GHz. The noise figure (NF) has a minimum at 2.2 dB and averages about 3 dB across the entire band. The amplifier consumes only 4.8 mW while the output buffer consumes only 1.2 mW, both from a 1.2 V supply, which leaves more room for optimization in the succeeding stages of the system. In the following sections, an efficient design methodology is described that reduces design complexity without sacrificing performance.

II. CIRCUIT DESIGN

A. Overview The LNA circuit can be divided into three modules –

input matching network, amplifier, and output buffer. The design goal is to localize optimization issues specific to each module. For the amplifier, gain, noise and power must be optimized while providing a simple RLC model for input matching. The goal of the matching network is to minimize input return loss without adding much noise. The output buffer is chosen to match a 50 Ω load to facilitate testing in this case. But it can be easily adapted to match higher impedance used for a mixer, with the limitation being the characteristic impedance attainable for transmission lines.

B. Amplifier Design Fig. 1(a) shows the simplified schematic of the amplifier.

The circuit uses a cascode topology to provide good isolation between the input and output, which significantly relaxes input broadband matching constraints. The concept of power-constrained simultaneous noise and input match (PCSNIM) is used here [2]. From [2], the optimal source impedance Zopt for noise matching in the circuit shown in Fig. 1(a) is

gsgsopt sC

mCcfZ 1)],,,,,(Re[ ⋅−= ωαδγ , (1)

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Figure 2. Real part of simulated Zin data.

where γ is a constant associated with channel noise current, δ is a constant associated with gate-induced noise current, α is the ratio of drain-source conductance over the same conductance under zero drain-source voltage, c is a correlation coefficient of gate-induced noise current and channel noise current, Cgs is gate-source capacitance, and m is an empirical constant, close to 1. The input impedance Zin for the circuit in Fig. 1(a) is 1/(jωCgs), which does not have a real part and obviously does not meet the requirement of simultaneous noise and input match where

inopt ZZ =* . (2)

In order to achieve PCSNIM, the circuit shown in Fig. 1(a) must be modified. The circuit in Fig. 1(b) with inductive degeneration and an extra matching capacitor Cext from gate-source, proves to be an excellent solution for PCSNIM without adding more noise. Zopt for the circuit in Fig. 1(b) can be approximated as

st

extgsopt sLsC

CCcfZ −−= 1)],,,,,,(Re[ ωαδγ , (3)

where Ct = Cgs + Cext. Zin then becomes

t

sm

tsin C

LgsC

sLZ ++= 1 . (4)

At this point it becomes evident that the imaginary parts of Zopt and Zin cancel out and the real parts can be optimized enabling a simultaneous noise and input matching to be achieved, where the optimization variables are Ls, Cext, and device size. Since the minimum noise figure, NFmin, is a function of power dissipation [3], the size of M1 must be relatively large. The size of the common-gate transistor M2 is chosen such that the noise it contributes to the system is balanced with its intrinsic capacitance, which can degrade the gain. At the load an inductor is used to boost gain at higher frequencies and to achieve flat frequency response.

Optimization of the amplifier yields the following parameters: W/L of M1 = 120µm/0.13µm, W/L of M2 = 40µm/0.13µm, Ls = 416 pH, Cext = 76 fF, Ld = 2.723 nH, ID = 4 mA.

C. Broadband Input Matching Network Design After the amplifier with optimized parameters is in

place, a broadband input matching network is required to generate good input return loss performance across the entire bandwidth without adding noise. Resistive and active matching are possible solutions but they introduce additional noise. Passive reactive matching networks, albeit large in size due to spiral inductors, are still the best solution for high performance.

From (4) the matching network is expected to match a series RLC load. However, (4) is a simplified equation aimed at qualitative circuit analysis and the accuracy of using an RLC model as the load has to be verified numerically using a circuit simulator with realistic device models. By running an S-parameter analysis in Cadence Spectre, S11 can be obtained and later converted to Zin for use in Mathcad. To compare the accuracy of the original Zin equation with the simulated data, a curve fitting function is used in Mathcad, which defines the unknown function as

RCj

LjZt

sin ++='

1')(ω

ωω , (5)

where Ls’, Ct’, and R are the unknown coefficients. Fig. 2 shows the plot of the real part of Zin data used to extract R. In the plot R is centered around 50 Ω and is not strongly dependent on ω. Fig. 3 shows the plot of the imaginary part of simulated Zin data and the new Zin with calculated coefficients, which resembles the simulation data very closely. The curve fitting function returns Ls’ = -0.109 nH and Ct’ = 300 fF. A negative inductance is observed from simulation plot suggesting that the deviation from the predicted value is caused by gate-drain capacitance (Cgd) of M1, the loading effect from M2, and limited Q of the passive components. Even though the coefficients are different from the predicted values, Zin(ω) still preserves the predicted series RLC model and thus simplifies broadband matching network design.

Figure 1. (a) Common cascode circuit. (b) Cascode topology with Ls

and Cext as PCSNIM components.

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Figure 3. Simulated and curve fitted imaginary Zin.

Figure 4. Chebyshev 3rd order bandpass matching network.

The matching network is designed with Genesys from Eagleware. Since inductor in series can cancel the negative Ls’, the model is simplified to an RC load. A Chebyshev third order band-pass filter is chosen and numerically optimized by the tool. The resulting matching network is shown in Fig. 4.

D. Output Buffer Design The output buffer needs to provide a 50 Ω match over

the entire bandwidth. A simple solution is a source follower where the output impedance is approximately 1/gm. To match a 50 Ω load, gm needs to be 20 mΩ-1. The size of the source follower is decided by the choice of gm and DC bias points. A transistor of W/L = 60µm/0.13µm is used for the source follower with ID = 1.52mA.

III. SIMULATION RESULTS The UWB LNA circuit was taped out using IBM 0.13µm

8RF CMOS technology. Since the chip has not come back, data from simulation with layout parasitics are presented. The layout is presented in Fig. 5. The die is 0.9mm x 1mm including 12 bond-pads. The layout has been optimized to reduce any parasitic feedback through the substrate. The amplifier consumes 4.8 mW DC power and the output buffer consumes 1.6 mW, using a 1.2 V supply.

Fig. 6 displays the input and output return loss from 1 GHz to 12 GHz. For the bandwidth in consideration (3.1 GHz – 10.6 GHz denoted by markers M1 and M2), S11 is below –10 dB for most of the frequencies, and S22 is always below –15 dB. Fig. 7 shows the gain of the LNA to be 11 dB and it is relatively flat across the entire band. Fig. 8

shows the NF and NFmin plotted together. NF closely follows NFmin across the entire bandwidth and only begins to deviate at higher frequencies, which confirms the validity of the simplified analytical noise and input matching calculations. Fig. 9 indicates that the stability factor, K, is larger than 30 for the whole band. A cascode topology proves to be effective in reducing feedback from output port to input port, thus enhancing stability.

Figure 5. LNA layout.

Figure 6. S11 and S22 of the LNA. M1 and M2 denote 3.1 GHz and 10.6 GHz respectively.

Figure 7. S21 of the LNA.

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Figure 8. NF and NFmin of the LNA.

Figure 9. Simulated stability factor K.

TABLE 1. COMPARISON WITH RECENTLY PUBLISHED RESULTS.

Ref. This work [4] [5] [6] [7]

S21(dB) 11 10 10 10 17

BW(GHz) 3.0–10.7 2.3-9.2 2.7-13 3.4-6.9 3.1-4.8

NFmin(dB) 2.2 4.0 2.1 4.5 3.9

PDC(mW) 4.8 9 19 3.5 21

IIP3(dBm) -8.2 -6.7* N/A N/A N/A

P1dBin(dBm) -17 -15* N/A -10# N/A

Technology CMOS CMOS SiGe SiGe CMOS

Min. Dimension 0.13um 0.18um N/A N/A 0.18um

* Measured at 6 GHz. # Measured at 5 GHz.

IIP3 and the 1dB compression point are simulated using Xpedion’s GoldenGate simulator. For the mid-band frequency of 6.85 GHz, IIP3 is –8.2 dBm and P1dB at input is –17 dBm. Table 1 summarizes the performance of the LNA along with results from recently published papers.

IV. CONCLUSION Design of an UWB LNA in 0.13µm CMOS process is

presented. The PCSNIM concept is used to achieve excellent noise performance. A numerically derived RLC model is used to determine the broadband matching network implemented as a Chebyshev band-pass filter. The LNA has a peak gain of 11.3 dB with -3dB bandwidth of 7.7 GHz (3.0 – 10.7 GHz). Input return loss is better than –10 dB over most of the bandwidth and output return loss is better than –15 dB for the entire bandwidth. NF has a minimum of 2.2 dB and the average NF is 3 dB. IIP3 is –8.2 dBm and P1dBin is –17 dBm at 6.85 GHz. DC power consumption is 4.8 mW for the amplifier and 1.6 mW for the output buffer with 1.2 V supply. Even though the LNA is designed in a more advanced technology, its performance compared to other designs is superior enough to show that technology advantage is fully utilized.

ACKNOWLEDGMENT The authors wish to thank MOSIS Education Program

and IBM for providing foundry access. The authors also wish to thank other members of CBCRL at Cornell University for their support.

REFERENCES

[1] http://www.ieee802.org/15/pub/TG3a.html [2] T. K. Nguyen, C. H. Kim, G. J. Ihm, M. S. Yang, and S. G. Lee,

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[3] D. K. Shaeffer and T. H. Lee, “A 1.5V, 1.5 GHz CMOS low noise amplifier,” IEEE J. Solid-State Circuits, vol. 32, pp. 745-758, May 1997.

[4] A. Bevilacqua, and A. M. Niknejad, “An ultra-wideband CMOS LNA for 3.1 to 10.6GHz wireless receivers,” IEEE Int’l Solid-State Circuits Conference Dig. Tech. Papers, pp. 382-391, Feb. 2004.

[5] B. Shi and M. Y.W. Chia, “Design of a SiGe low-noise amplifier for 3.1-10.6 GHz ultra-wideband radio,” Proc. Int’l. Symp. Circuits and Systems, vol. 1, pp. I-101 - I-104, May 2004.

[6] D. Barras, F. Ellinger, H. Jackel, and W. Hirt, “A low supply voltage SiGe LNA for ultra-wideband frontends,” IEEE Microwave and Wireless Components Letters, accepted for future publication, 2004.

[7] S. Vishwakarma, S. Jung, and Y. Joo, “Ultra wideband CMOS low noise amplifier with active input matching,” Joint with Conf. Ultrawide Band Sys. Tech. and Int’l. Workshop on UWB Systems, pp. 415 – 419, May 2004.

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