1-4244-1468-7/07/$25.00 ©2007 IEEE 275

Impact of Negative Bias Temperature Instabilities on Lifetime in p-channel Power VDMOSFETs

Ninoslav Stojadinović1, Danijel Danković1, Ivica Manić1, Vojkan Davidović1, Snežana Djorić-Veljković2, Snežana Golubović1

Abstract – Negative bias temperature instabilities (NBTI) are

commonly observed in p-channel metal-oxide-semiconductor (MOS) devices when exposed to negative gate voltages at elevated temperatures. We present a brief overview of NBT stress-induced threshold voltage instabilities in p-channel vertical double-diffused MOS field-effect transistors (VDMOSFETs). NBT stress-induced threshold voltage shifts are fitted using different models to estimate the device lifetime and to discuss the impacts of stress conditions, failure criterion, extrapolation model, and intermittent annealing on lifetime projection. The stretched exponential equation is found to provide excellent fit to experimental data for the later stress phases and thus allows an accurate estimation of device lifetime for the lowest stress voltage applied, which justifies the use of this or some other suitable fitting equation. The realistic failure criterion for devices and experimental conditions used in our studies is found to fall in the 100 - 150 mV range. The lifetime estimates are found to strongly depend on the model used for extrapolation to normal operating conditions. The 1/VG model is shown to provide much faster output since it appears to allow the use of higher stress voltages while still yielding rather accurate lifetime estimates. Intermittent annealing does not seem to have any significant impact on device lifetime.

Keywords – NBTI, VDMOSFET, threshold voltage, lifetime.

I. INTRODUCTION

Negative bias temperature instabilities (NBTI) have been found to occur mostly in p-channel MOSFETs operated at elevated temperatures (100 - 250 oC) under negative gate oxide fields in the range 2 - 6 MV/cm [1-7]. NBTI are manifested as the decrease in device transconductance (gm) and absolute drain current (IDsat) and the increase in device threshold voltage (VT) and absolute “off” current (Ioff) [3]. The phenomenon had been known for many years, but only recently has been recognised as a serious reliability issue in state-of-the-art MOS integrated circuits. Several factors have conspired to bring NBTI to the attention of device and circuit designers: first, operating voltages have not been reduced as rapidly as gate oxide thickness, resulting in higher fields and increased chip temperatures, which both enhance the NBTI; second, threshold voltage scaling has not kept pace with operating voltage, which has resulted in larger percentage

1 Ninoslav Stojadinović, Danijel Danković, Ivica Manić, Vojkan

Davidović, and Snežana Golubović are with the Faculty of Electronic Engineering, University of Niš, Aleksandra Medvedeva 14, 18000 Niš, Serbia, E-mail: nstojadinovic@elfak.ni.ac.yu

2Snežana Djorić-Veljković is with the Faculty of Civil Engineering and Architecture, University of Niš, Aleksandra Medvedeva 14, 18000 Niš, Serbia.

degradation of drain current for the same ∆VT; and third, the addition of nitrogen into the thinned gate oxides for leakage reduction has had the side effect of increasing NBTI [2].

Regarding the device electrical parameters, NBT stress-induced threshold voltage shifts are most critical and can put serious limit to a lifetime of p-channel devices with gate oxide thinner than 3.5 nm [5]. Several models of microscopic mechanisms responsible for the observed VT shifts have been proposed [1-7], but this topic is beyond the scope of this paper and will not be discussed. However, it is important to offer a brief answers to a couple of basic questions that could arise so far, such as: (i) Why the NBTI are of greater concern in p-channel devices compared to n-channel ones? (ii) Why the negative bias causes more considerable degradation than positive bias? The bias temperature stress-induced VT shifts are generally known to be the consequence of underlying buildup of interface traps and oxide-trapped charge due to stress-initiated electrochemical processes involving oxide and interface defects, holes and/or electrons, and variety of species associated with presence of hydrogen as the most common impurity in MOS devices. An interface trap is an interfacial trivalent Si atom with an unsaturated (unpaired) valence electron at the SiO2/Si interface. Unsaturated Si atoms are additionally found in SiO2 itself, along with other oxide defects, the most important being the oxygen vacancies. Both oxygen vacancies and unsaturated Si atoms in the oxide are concentrated mostly near the interface and they both act as the trapping centres responsible for buildup of oxide-trapped charge. Interface traps readily exchange charge (electrons or holes) with the substrate and they introduce either positive or negative net charge at interface, which depends on gate bias: the net charge in interface traps is negative in n-channel devices, which are normally biased with positive gate voltage, but is positive in p-channel devices as they require negative gate bias to be turned on. On the other hand, the charge found trapped in the centers in the oxide is generally positive in both n- and p- channel MOS transistors and cannot be quickly removed by altering the gate bias polarity [8]. Therefore, absolute values of VT shifts due to stress-induced oxide-trapped charge and interface traps in n- and p-channel MOS transistors, respectively, can be expressed as [8−10]:

ox

itn

ox

otnTn C

NqCNqV ∆

−∆

=∆ , (1)

ox

itp

ox

otpTp C

NqCNq

V∆

+∆

=∆ , (2)

where q denotes elementary charge, Cox is gate oxide capacitance per unit area, while ∆Not and ∆Nit are area

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densities of oxide-trapped charge and interface traps, respectively. Similar amounts of oxide-trapped charge and interface trap generation occur in both n- and p-channel devices [2], but above consideration clearly shows that the net effect on threshold voltage, ∆VT, must be greater for p-channel devices, because in this case the positive oxide charge and positive interface charge are additive. As for the question (ii), it seems well established that holes are necessary for BTI degradation [1-7], which provides a straight answer since only negative gate bias can provide holes at the SiO2/Si interface. Moreover, this is an additional reason why the greatest impact of NBTI occurs in p-channel transistors since only those devices experience a uniform negative gate bias condition during typical CMOS circuit operation.

There has recently been an explosion of publications on NBTI [1-7]. However, in spite of very extensive studies in recent years, microscopic mechanisms are still not fully understood, and technology optimization to minimize NBTI is difficult task. Therefore, accurate lifetime models are needed to make good prediction of device reliable operation.

Gate oxide in nanometre scale technologies is continuously being thinned down, but there is still high interest in ultra-thick oxides owing to widespread use of MOS technologies for the realisation of power devices. Power VDMOSFET is an attractive device for application in high-frequency switching power supplies owing to its superior switching characteristics which enable operation in a megahertz frequency range [11, 12]. High-frequency operation allows the use of small-size passive components (transformers, coils, capacitors) and thus enables the reduction of overall weight and volume, making the power VDMOSFETs especially suited for application in power supply units for communication satellites. Also, power VDMOSFETs are widely used as the fast switching devices in home appliances and automotive, industrial and military electronics [13]. Degradation of power MOS devices under various stresses (irradiation, high field, temperature, and even hot carrier) has been subject of extensive research (for example, see [14] and references cited therein), but very few authors seem to have addressed the NBTI in these devices [13, 15−18]. However, increased electric fields and elevated chip temperatures are frequently approached during the routine operation of power devices in automotive and industrial applications [13] so the investigations of NBTI in power MOSFETs are of importance as well.

In this paper, we analyse the NBT stress-induced threshold voltage shifts in commercial p-channel power VDMOSFETs and apply different models for fitting the experimental data and estimating the device lifetime. The impacts of stress conditions, failure criterion, extrapolation model, and intermittent annealing on lifetime projection will be discussed in details as well.

II. STRESS-INDUCED THRESHOLD VOLTAGE SHIFTS

Devices used in this study were commercial p-channel power VDMOSFETs IRF9520, encapsulated into the TO-220 plastic cases, with current and voltage ratings of 6.8 A and 100 V, respectively. Devices were built in standard Si-gate technology with 100 nm thick gate oxide, and had the

threshold voltage VT = -3 V. A set of devices were stressed up to 2000 hours by applying negative voltages in the range 30 – 45 V to the gate, with drain and source terminals grounded, at temperatures ranging from 125 to 175 oC. A conventional methodology, based on periodic stops during the stress to measure the device transfer I-V characteristics, was applied to characterize the NBTI effects. Threshold voltage values were estimated from the above-threshold transfer characteristics as the intersections of extrapolated linear region of GSD VI − curves with VGS - axis.

Typical transfer I-V characteristics of p-channel power VDMOSFETs during the NBT stressing are shown in Fig. 1. As can be seen, the characteristics are being shifted along the VGS axis towards the higher VGS voltages, which is the consequence of stress-induced buildup of oxide-trapped charge. The shifts are more significant in the early phase of stressing and gradually become smaller with tendency to saturate as the stressing advances. At the same time, the slope of the curves slightly decreases, indicating that interface traps are being generated as well.

-3.8 -3.6 -3.4 -3.2 -3.0

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0.10

NBT stress time (h)

I D(A

)

VGS(V)

pre

0.5 3 7 21 68 211 402 664 1144 1478 1646

Fig. 1. ID-VGS curves observed in p-channel VDMOSFETs during the

NBT stressing at VG = - 40 V and T = 150 oC

In line with observed shift of transfer characteristics along the voltage axis, NBT stressing was found to cause significant VT shifts. Two characteristic sets of data, for IRF9520 devices stressed at different temperatures with - 40 V and with different stress voltages at 150 oC, are shown in Figs. 2 and 3, respectively. Apparently, more pronounced shifts are obtained at higher temperatures (Fig. 2) and/or stress voltages (Fig. 3). The ∆VT time dependencies have been found to follow the tn power law, with three distinct phases (as indicated by the dashed lines), which can be clearly distinguished depending on the value of parameter n [16−18]. In the first (early) phase, n strongly depends on both stress bias and temperature, varying from 1.14 to 0.4. In the second phase, n is almost independent on bias and temperature, and ∆VT follows the well-known t0.25 law [1−4, 13, 14, 16-19]. The second phase begins earlier in devices stressed at higher voltages and/or temperatures so the first phase might even disappear if more severe stress conditions had been applied. Finally, in the third phase, n becomes bias and temperature dependent again and

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0.1 1 10 100 100010-3

10-2

10-1

100

t0.57-0.43

t0.14

t0.25

T(oC)

∆VT(

V)

Stress time (hours)

VG=-40V

125 150 175

Fig. 2. Threshold voltage shifts in p-channel VDMOSFETs during

the NBT with VG = - 40 V stressing at different temperatures.

0.1 1 10 100 100010-3

10-2

10-1

100

t1.14-0.57

t0.14

VG(V)

T=150oC

∆VT(V

)

Stress time (hours)

-30 -35 -40 -45

t0.25

Fig. 3. Threshold voltage shifts in p-channel VDMOSFETs during

the NBT stressing with different gate voltages at T = 150 oC.

gradually decreases from 0.25 to 0.14, while ∆VT tends to saturate. The ∆VT in saturation after near 2000 hours of stressing was found to vary from about 4.4 % (125 oC, - 30 V) to 19.8 % (175 oC, - 45 V) [16].

Applying the approach described in [4] to our above results, the following dependence of ∆VT on stress field (E), time (t), and temperature (T) in the second phase was derived:

)/24.0exp(04.3)/exp( 25.005.2 kTtEkTEtAEV anm

T −=−=∆ , (3)

where A is a constant, Ea is activation energy, and k is the Boltzmann constant. Similar empirical expressions can be derived for ∆VT in the first and third phases, and those three expressions can be used to calculate threshold voltage shifts for random negative stress voltages in the range 30 – 45 V at random stress temperatures ranging from 125 to 175 oC.

III. EXPERIMENTAL LIFETIME ESTIMATION

Our goal was to estimate the lifetime of investigated p-channel power VDMOSFETs under normal operating conditions. Various parameters, such as threshold voltage, transconductance, or drain current, can be used as a

degradation monitor [20, 21]. We will use the threshold voltage, which is widely accepted as a well-suited parameter, so the device lifetime for practical operation will be estimated from experimental results for the NBT stress-induced ∆VT. As illustrated in Fig. 4, the experimental lifetime is defined as the stress time required for ∆VT to reach the predetermined failure criterion (FC). Experimental values of the lifetime are first extracted and then used to plot the lifetime vs. gate voltage dependence as in the inset graph, and this plot is then used for extrapolation to a normal operating voltage.

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102

103

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107

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t3t4

t2 t1

Life

time

(s)

-VG(V)

125oC

10 year

t4t3t1VG(V)

T=125oC

∆VT(

V)

Stress time (hours)

-30 -35 -40 -45

t2

FC ∆VT=100mV

Fig. 4. Extraction of experimental results for lifetime estimation.

A proper choice of failure criterion, which will be discussed in more details later, is very important. For example, it can be seen in Fig. 4 that, if the value of FC was higher then about 120 mV, we could not get experimental lifetime for devices stressed with the lowest voltage (- 30 V) at 125 oC since in this case ∆VT did not reach 120 mV even after 2000 hours of stressing. This means that duration of the experiment was too short to achieve ∆VT as high as FC so in that case the stress time would have to be extended to exceed the device lifetime at given combination of stress bias and temperature. However, this might require the stressing to be done beyond any reasonable time limits so in such cases it is more convenient to use an adequate fitting model capable to provide reliable prediction of ∆VT on the basis of available data. The simplest way is to use regular exponential model [22−24]:

)]/exp(1[)( max τtVtV T −−∆=∆ , (4)

where ∆VTmax is the saturation level of threshold voltage shift and τ is the characteristic time constant. However, as shown in Fig. 5, this model (dotted line) in our case yields very poor agreement with experimental data and significantly underestimates ∆VT in saturation. Since the ∆VT time dependencies in our devices exhibit the discontinuities manifested as three distinct stress phases (Figs. 2 and 3), better agreement with experimental data is expected from the modified version of the above model, which is known as a 2-tau exponential model and is given by [22, 23]:

)]/exp(1[)]/exp(1[)( 2211 ττ tVtVtV −−∆+−−∆=∆ , (5)

278

The fitting parameters τ1 and τ2 in Eq. (5) represent the time constants closely related to transitions from early to the second stress phase and from the second phase to saturation, respectively, and ∆V1 and ∆V2 are related to corresponding VT shifts. This model is suitable for processes which has two distinct mechanisms operating one after the other with 100τ1 < τ2. As can be seen in Fig. 5, this model (dashed line) yields fairly good agreement with experimental data. However, this model is very sensitive to small fluctuations in experimental data, the fit appears “wavy” in the second stress phase, and also tends to exaggerate saturation, especially in devices stressed under the least severe conditions (- 30 V, 125 oC), which experimental data (diamonds in Fig. 5) do not seem to justify. Practically, point of transition from the second phase to saturation obtained by the model seems misplaced.

0.1 1 10 100 100010-3

10-2

10-1

100

stretched exponential model2-tau exponential modelexponential model

∆VT=150 mV∆VT=100 mV

experimental

fitting

T(oC)

∆VT(V

)

Stress time (hours)

-45 175 -30 125

VG(V)

Fig. 5. Fitting the NBT stress-induced VT shifts by various models.

Symbols denote measured data and lines are the fits.

Trying to resolve the problem, we have also considered the so-called stretched exponential (SE) model, given by [25, 26]:

)])/(exp(1[)( maxβτ oTT tVtV −−⋅∆=∆ , (6)

where ∆VTmax, τo, and β are the fitting parameters. The SE model predicts ∆VT would saturate and reach its maximum value ∆VTmax in saturation only after a prolonged stressing so the ∆VTmax can be taken as a measure of ∆VT at ten year device lifetime. Parameter β is defined as a measure of distribution width, and τo represents a characteristic time constant of the distribution [25, 26]. This model is suited for processes that, either have two or more distinct mechanisms each with its own τ, or have a single mechanism with statistically distributed values of τ [27].

As can be seen in Fig. 5, the SE model (solid line) yields very poor agreement with our experimental data in the early phase of stressing, especially for lower stress voltages. However, the fitting curves are smooth and this disagreement tends to decrease with voltage and/or temperature increase. Moreover, the model is in excellent agreement with experimental data in the second stress phase and in saturation, which is of greatest practical importance since we need

reliable prediction for ∆VT at prolonged stress time to estimate device lifetime. Figure 5 also shows that stress times at which the transitions from early to second phase occur, earlier determined on the basis of parameter n in tn power law, correspond to the points at which the SE curves begin to agree well with experimental data, thus confirming previously established early-to-second phase transition [16, 17].

The values of parameter β in SE fit of our experimental results obtained on VDMOSFETs are found to vary in the range 0.35∼0.39 independently on stress conditions, while τo decreases with increasing stress bias and temperature, which all is in good agreement with findings reported in [25, 26]. The values of threshold voltage shifts in saturation, ∆VTmax, are listed in Table I. As expected, these values, which represent a measure of ∆VT at ten year device lifetime, increase with both NBT stress voltage and temperature.

TABLE I

VALUES OF ∆VTmax IN THE STRETCHED EXPONENTIAL FIT OF DATA OBTAINED ON NBT STRESSED P-CHANNEL POWER VDMOSFETS

VG (V) ∆VTmax (V) -30 -35 -40 -45

125 0.1858 0.2518 0.3109 0.4169

150 0.2073 0.3241 0.4074 0.5563

T (o C

)

175 0.3188 0.3319 0.4584 0.5694

IV. LIFETIME PROJECTION

A. Choice of failure criterion

As already indicated in Fig. 5, we define two different failure criteria as the threshold voltage shifts of 100 mV (3.33 %) and 150 mV (5 %), respectively, which are used to project the device lifetime under normal gate bias conditions. Lifetime estimation for both FC, done by standard linear extrapolation assuming maximum operating gate voltage VG = - 20 V, is illustrated in Fig. 6, while the values of extrapolated lifetime are listed in Table II. Obviously, the projected lifetime strongly depends on the choice of FC.

The tendency of threshold voltage shift to saturate results into extended device lifetime, especially if higher FC (150 mV) is applied. As can be seen in Fig. 5, in the case of the lowest stress voltage the 150 mV FC line only intersects with SE fitting curve but not with experimental data since the duration of experiment appeared shorter than the lifetime at given temperature. However, lower stress voltages are closer to actual operating voltages and are expected to provide more realistic lifetime projection. In this case, the fact that SE model successfully predicts threshold voltage shift in saturation enabled us to estimate lifetime by using the results obtained by fitting instead of the missing experimental ones. If the chosen FC was too high (e.g. 700 mV), its value would fall far above both experimental and fitting curves in Fig. 5, which would result into device lifetime tending infinity. Alternatively, too low FC (below 30 mV) could lead to rather

279

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1010

10 year

Life

time

(s)

-VG(V)

125oC 150oC 175oC

∆VT=100mV (3.33%)

(a)

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101

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109

1010

∆VT=150mV (5%)

Life

time

(s)

-VG(V)

125oC 150oC 175oC

10 year

(b)

Fig. 6. Linear extrapolation of the device lifetime for two different FC: a) ∆VT =100 mV; b) ∆VT =150 mV.

TABLE II

LIFETIME PROJECTIONS FOR OPERATING VOLTAGE VG = - 20 V

Lifetime (days) ∆VT =100 mV ∆VT =150 mV

125 oC 391.07 5792.10

150 oC 30.67 289.86

175 oC 9.25 48.06

significant underestimation of device lifetime as the FC value would fall in the early phase of stressing.

Thus, it appears that most reliable lifetime estimate can be obtained by choosing the FC value within the range of threshold voltage shifts observed in the second and saturation phases of device stressing. The correct choice of FC could be verified by considering the values of ten year operation voltage, which is defined as the maximum gate voltage that allows ten years of device operation with VT shift below the given FC. As can be seen in Table III, which shows the data taken from Fig. 6, the values of ten year operation voltage in most cases are under the maximum operating gate bias voltage (-20 V), except in the case of 150 mV FC at 125o C stress

TABLE III VALUES OF TEN YEAR OPERATION VOLTAGE

Maximum VG (V) ∆VT =100 mV ∆VT =150 mV

125 oC -13 -21

150 oC -3 -12

175 oC -5

temperature. Alternatively, table indicates that in the case of 100 mV FC the devices at 175o C cannot approach 10 years of operation even without any gate bias, which does not seem to make sense. Thus, the realistic FC for the devices and experimental conditions used in our study appears to fall in the 100 - 150 mV range, which yields the ten year operation voltage in the range between 0 and -20 V that corresponds to normal operation voltages.

B. Influence of stress voltage range

Another factor that may affect the value of lifetime estimate is the range of stress voltages used for extrapolation [15]. Its effects on uncertainties of both lifetime projection and ten year operation voltage in the case of VDMOS devices stressed at 150 oC are illustrated in Fig. 7. As can be seen, estimated lifetime may vary for almost one order of magnitude, while the maximum allowed VG varies for about 8 V.

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Extrapolationuncertainty of VG

lower VG range

higher VG range

Experiment

150oC ∆VT=150mV (5%)

Life

time

(s)

-VG(V)

full VG range

uncertainty of lifetime

10 year

Fig. 7. Uncertainties of lifetime and ten year operation voltage due to

different ranges of stress voltages used for extrapolation.

A schematic drawing shown in Fig. 8 provides further evidence that device lifetime obtained by extrapolating the experimental data to normal operating conditions may strongly depend on the choice of both stress voltage range and FC. As can be seen, experimental values of the lifetime determined for a given FC fall in the early and saturation phases for devices stressed with the highest and lowest voltages, respectively. As a result, both these experimental values are higher (for ∆t2 and ∆t1, respectively) than if they were found in the second phase, thus causing the deviation from the linear dependence in the extrapolation plot shown as an inset graph in Fig. 8. Further consequence is that the use of

280

Fig. 8. Schematic illustration to explain the influence of FC and

stress voltage range on lifetime estimate.

higher stress voltage range for extrapolation to normal bias conditions tends to underestimate the lifetime, while the use of lower stress voltage range appears to overestimate it. Both contribute to uncertainties shown in Figs. 7 and 8, but more realistic lifetime estimates can be expected if the lower stress voltage range, closer to actual operating bias voltage, is used for extrapolation. However, in that case the duration of the experiment could be too long, and most appropriate solution is to use an expression, such as the SE equation, that provides good fit to experimental data in the low stress voltage range.

C. Choice of extrapolation model

Estimated lifetime may depend on the model (i.e. the mathematical function) used for extrapolation as well [28, 29]. The standard model, based on linear extrapolation, has already been used in Figs. 6 and 7. In addition, for extrapolation along the voltage axis we also use the “VG” and “1/VG” models, which are given by following expressions, respectively:

)exp( GVBA ⋅−⋅=τ , (7)

)/exp( GVBA ⋅=τ , (8)

as well as the “power-law” model for extrapolation along the electric field axis:

pEC −⋅=τ . (9)

In the expressions above, τ is the lifetime, VG and E are the stress voltage and corresponding electric field, respectively, while A, B, C, and p are the fitting parameters. These models are based on the experience of different researchers, and it is simple to show, for example, that power-law model can be derived from empirical Eq. (3) by rearranging it:

)/exp(/1//1 nkTEVEAt an

Tnmn ∆= − (10)

and defining new parameters, C and p, as follows:

)/exp(/1/1 nkTEVAC an

Tn∆= , (11)

nmp /= (12)

where t becomes lifetimeτ, and ∆VT takes the value of FC.

The uncertainties of both device lifetime and ten year operation voltage in the case of p-channel VDMOSFETs stressed at 150 oC, as obtained using different models for extrapolation, are shown in Fig. 9. As can be seen, each model yields different results, and the lifetime estimates obtained using different models may vary for more than two orders of magnitude, while the ten year operation voltage varies for about 10 V. The VG and especially standard model yield lower values of both lifetime and ten year operation voltage, and these models do not seem to provide good fit to our experimental data. The VG model curve shows disagreement with experimental data obtained at higher stress voltages, which is in line with expectation on more realistic estimates if the lower stress voltage range, closer to actual operating voltage, is used for extrapolation. Alternatively, the power-law model provides better fit to our experimental data, but still shows certain disagreement at higher voltage end, while the 1/VG model appears to fit our experimental results almost perfectly over the full range of stress voltages applied. Thus, the lifetime and ten year operation voltage estimates obtained by the 1/VG model appear to be the least affected by the choice of stress voltage range.

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10101 2 3 4 5 6 7

1/VG model

E(MV/cm)

Extrapolation

uncertainty of VG power-law model

VG model

Experiment

150oC ∆VT=150mV (5%)

Life

time

(s)

-VG(V)

standard model

uncertainty of lifetime

10 year

Fig. 9. Device lifetime and ten year operation voltage uncertainties

due to different models used for extrapolation.

The above considerations may have important consequences on investigations of NBTI related degradation and lifetime prediction in power VDMOSFETs and other devices exhibiting the saturation of threshold voltage shift over an extended period of NBT stressing. Namely, it appears that lifetime estimates obtained by power-law, VG and standard models would approach those obtained by 1/VG model if lower voltages are used for device stressing. However, this could require very long time to perform the experiment. On the other hand, the 1/VG model could provide much faster output since it appears to allow the use of higher stress voltages while still being capable to yield rather accurate lifetime estimates.

V. IMPACT OF INTERMITTENT ANNEALING

The recovery and annealing of NBTI have received an increased attention recently [1, 30−32], and we also have tried

281

to get new insight into the NBTI phenomena by subjecting the devices to a sequence of NBT stress and bias annealing steps. Detailed experiments, with different stress and recovery conditions, have been performed to assess the impact of annealing phase on lifetime. Herewith we will present the results obtained on a set of IRF9520 devices which have been subjected to a sequence of three interchanging NBT stress and bias annealing steps as follows: one week of NBT stressing with three different gate voltages (-35, -40, and -45 V) at T = 150o C was followed by one week of positive gate bias annealing (VG = +10 V) also at 150o C, and then the devices were NBT stressed again for one week.

As can be seen in Fig. 10, the increase of threshold voltage during the initial stressing was most significant in devices stressed at VG = -45 V. Threshold voltage shifts decreased in all devices during the subsequent positive bias annealing, but increased again on repeated NBT stressing. Most significant decrease was also observed in devices stressed previously with VG = -45 V, but the increase during the next stressing again was the highest in these devices.

10-1 100 101 10210-1 100 101 102

0.01

0.1

10-1 100 101 102

VG(V)

anneal

Anneal time (h)

+10 +10 +10

∆VT (V

)

Stress time (h)

-45 -40 -35

1st stressT=150oC

VG(V)

FC:150mv

VG(V)

2nd stress

Stress time (h)

-45 -40 -35

Fig. 10. Threshold voltage shifts during the full sequence of NBT

stresses and positive bias annealing at T=150 oC

To assess the impact of intermittent annealing step on lifetime projection more closely, Fig. 11 shows the motion of VT shift over the full 3-step stress/anneal/stress sequence in linear scale. As can be seen, significant recovery of threshold voltage during annealing occurs only in an early stage of the anneal step, and ∆VT did not fall below 100 mV. So, we can conclude that there is a non-reversible component of threshold voltage shifts, which results from the portion of stress-induced oxide-trapped charge and interface traps that can not be annealed.

Judging from the above data, the failure criteria that would yield reasonable lifetime projection appear to fall in the range 100-200 mV. Lifetime estimates for both continuously stressed devices and those subjected to above 3-step stress/anneal/stress sequence, obtained by using the power-law model, are shown in Fig. 12. As can be seen, the two curves overlap in the semi-log plot, yielding practically the same lifetime estimates. The dashed line shows estimation of the difference between the two lifetime projections, yielding ∆τ < 105 s, i.e. less than 2 days, which is negligible in comparison with 10-year lifetime expectation. Therefore, the

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0.30160 140 120 100 80 60 40 20 0

Stress,

Anneal time (h)

Stress time (h)

1st stress 2nd stress

Anneal, VG=+10VT=150oC

∆VT(

V)

VG=-40V

Fig. 11. Threshold voltage shifts during the sequence of NBT

stresses and positive bias annealing.

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τ

∆VT=150mV (5%)

Life

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(s)

-VG(V)

continuous stress stress/anneal sequence

difference

10 year

power-law modelFC

∆τ

Fig. 12. Lifetime in continuously and sequentially stressed devices.

intermittent annealing did not have any apparent impact on device lifetime, which could have been expected since ∆VT at the end of sequence approached ∆VT observed in continuously stressed devices.

VI. CONCLUSION

The NBT stress-induced threshold voltage instabilities in commercial p-channel power VDMOSFETs, as well as the implications of NBTI related degradation on device lifetime have been reviewed. NBT stress-induced threshold voltage shifts have been fitted using different models to estimate the device lifetime and to discuss the impacts of stress conditions, failure criterion, extrapolation model, and intermittent annealing on lifetime projection. Excellent agreement between the stretched exponential fit and experimental data found in later stress phases allowed for an accurate estimation of device lifetime for the lowest stress voltage applied, which justified the need for using the stretched exponential or some other suitable fit. The realistic failure criterion for devices and experimental conditions used in our study was found to fall in the 100 - 150 mV range. Estimated values of device lifetime were found to strongly depend on the model used for

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extrapolation to normal operating conditions. The 1/VG model was shown to provide faster output since it appeared to allow the use of higher stress voltages while still being capable to yield rather accurate lifetime estimates. Intermittent annealing did not have any apparent impact on device lifetime.

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