An Adaptive Test for Parametric FaultsBased on Statistical Timing Information

Michihiro Shintani∗, Takumi Uezono†, Tomoyuki Takahashi†, Hiroyuki Ueyama†1,Takashi Sato‡, Kazumi Hatayama∗, Takashi Aikyo∗, and Kazuya Masu†

∗Semiconductor Technology Academic Research Center17-2, Shin Yokohama 3-chome,Kohoku-ku,Yokohama 222-0033 JapanEmail: {shintani.michihiro, hatayama.kazumi, aikyo.takashi}@starc.or.jp

†Integrated Research Institute, Tokyo Institute of Technology4259-R2-17 Nagatsuta, Midori-ku, Yokohama 226-8503 Japan

Email: {uezono, masu}@lsi.pi.titech.ac.jp, {ueyama.h.aa, takahashi.t.ay}@m.titech.ac.jp‡Department of Communications and Computer Engineering, Kyoto University

Yoshida-hon-machi, Sakyo, Kyoto, 606-8501 JapanE-mail:takashi@i.kyoto-u.ac.jp

Abstract—The continuing miniaturization of LSI dimensionis causing the increase of process-related variations which sig-nificantly affects not only its design turn around time but alsoits manufacturing yield. Statistical static timing analysis (SSTA)is expected as a promising way to estimate the performance ofcircuits more accurately considering delay variations. However,LSIs designed using SSTA may have higher probability ofparametric faults than the ones designed with deterministictiming analysis. In order to test these parametric faults,effective extraction techniques of critical paths are needed.In this paper, we discuss a general trend between the delay

margin of LSIs designed by SSTA and their parametric faultratio. Then we propose an adaptive test flow for parametricfaults using statistical static timing information, and a conceptof parametric fault coverage. Experimental results demonstratethe effectiveness of our approach.

Keywords-parametric fault, path-delay test, SSTA

I. INTRODUCTION

The advance of very deep sub-micron (VDSM) processtechnology has enabled the realization of large-scale andhigh performance LSIs. Meanwhile, their performance isaffected by VDSM issues, such as crosstalk noises, powersupply noises and delay variations. To overcome theseproblems, SSTA has been proposed and is expected as aneffective timing sign-off method [1]. However, from theviewpoint of LSI testing, SSTA may increase the risk ofsuffering from parametric faults. If a critical path of a circuitcontains a small delay defect [2], its delay may exceed thesystem clock period of the circuit and result in a timing fault.In general, for detecting such a fault, it is necessary to testa critical path that has the smallest timing slack. However,critical paths may vary with process-conditions [6]. In orderto screen such parametric faults, it is necessary to extractcritical paths considering process variations.

1He is presently with Sony Co., Ltd.

Recently, various test methods for small delay defectshave been proposed [3]-[11]. Sato et al. proposed a testpattern generation method which propagates fault effect ona longer path and defined a statistical delay quality level(SDQL) based on a statistical delay quality model (SDQM)as a measure of delay test quality [3]. Uzzaman et al.evaluated a faster than at-speed testing method by SDQL[4]. Iyenger et al. utilized SSTA information to test the pathswhich has high probability of causing parametric faults [5],[6]. In [7]-[9], several authors proposed test quality measureseach of which utilizes the probability density function (PDF)of path delay. Park et al. introduced an idea of statisticsto delay fault coverage and proposed statistical delay faultcoverage (SDFC) [7]. Yilmaz et al. evaluated the delay testquality of each test pattern based on PDF, and proposeda method to select a set of test patterns for screeningsmall delay defects [8], and proposed a method to selecta set of test patterns more effectively by adding the layoutinformation to PDF [9]. Furthermore, Liou et al. proposeda test method using sensitivity of paths [10], Callegari et al.proposed a methodology to detect critical paths effectively[11], and Mitra et al. proposed a method to utilize a processmonitor embedded on chip to detect small delay defects [12].It is known that the number of test patterns for small delay

faults is very large. In order to reduce the test cost, adaptivetest methods have been proposed. Benner et al. showed thatan adaptive test process reduces test-time without loss oftest-quality [13], and Madge et al. combined an adaptive testmethod and an outlier screening method effectively [14]. Butthey did not have any concern about SSTA.The objective of our work is to establish a novel test

method to screen parametric faults which will become morecommonplace when SSTA is widely accepted as a sign-off timing analysis. To accomplish this objective, our testflow extracts a set of appropreate critical paths dependingon process conditions which are measured by a sensor circuit

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embedded on chip or on wafer. In design phase, critical pathsare clustered corresponding to process conditions, and ATPGgenerates test patterns for the paths of all clusters. Moreover,we propose a concept of parametric fault coverage, andevaluate the effectiveness of our adaptive test flow byexperiments.The rest of this paper is organized as follows. Section II

describes a motivational analysis of our work. The proposedadaptive test flow is presented in Section III and the conceptof the parametric delay fault coverage is defined in SectionIV. Experimental results are given in Section V and weconclude this paper and discuss future works in Section VI.

II. MOTIVATIONA. Relationship between SSTA and Parametric Faults

Static Timing Analysis (STA) has been widely used as amethod to estimate circuit delay. In an STA, the worst casemodel, in which parameters of all devices on a chip deviateto the directions to make delay larger, is commonly usedto estimate the worst path-delay [15]. However, since theprobability of such a worst case is quite low, the estimateddelay would be too pessimistic. In order to estimate a delayfor the realistic worst condition where the delay wouldreally happen, an SSTA approach, which deals with delayvariations statistically has been studied intensively [1]. Thebasic idea of SSTA is to represent delay using stochasticvariables representing random and correlated componentsof the variation sources and to calculate statistical circuitdelays. However, if SSTA is applied, extra design margins,which has been implicitly added in STA analysis, can begreatly reduced. As a result, parametric faults may morelikely to occur.Let us consider a simple sample path which consists of

n logic cells as shown in Fig. 1 as an example. In Fig.1, μi and σi are the mean and the standard deviation ofthe delay of i-th cell, respectively. When we use 3-sigmaworst-case analysis by STA, the sign-off timing Tsta isΣi(μi + 3σi). If the delays of all cell elements have nocorrelation with each other, the delay distribution of thispath is given by N(Σiμi, Σiσ

2i ), where N(μ, σ2) expresses

a normal distribution with mean μ and standard deviation σ.The 3σ point of this distribution, Tssta, is Σiμi +3

√Σiσ2

i .This means that, for the same path, Tssta has a larger timingmargin than Tsta. When there exists a large slack in thecircuit, designers tend to downsize cells to reduce chip sizeand power consumption.

Figure 1. A sample path

Figure 2. The changes of path distributions

We executed an experiment to examine how the path-delaydistribution changes when a cell is replaced. The target pathconsists of randomly selected 25 cells from 90 nm standardlogic cell library. Off-path inputs of logic cells are tied toVDD or GND so that the path is sensitized.The change of the path-delay distribution is shown in

Fig. 2. The vertical axis shows the probability density ofthe path delay and the horizontal axis shows the pathdelay. ”STA S.O.” of Fig. 2 shows a system clock cycle,Tsta. The left-most distribution ”iteration = 0” indicatesthe initial setting. Cells are downsized maintaining thetiming constraints of the path. In Fig. 2, the number ofcell replacement or iteration is 5. It can be seen that theprobability of the occurrence of parametric faults increasesby each replacement, if this path is signed-off by the sametiming constraint as STA Tsta. This is because both the meanand the variation of the distribution increase by using lowersize and lower drivability cells.We here conclude that it is a general concern that the

circuit signed-off by SSTA may have a higher probabilityof suffering from parametric faults.B. Influence of Process Variations on Path DelayAs a preliminary survey, we checked how the ranking of

path delay would be varied according to process parametersby using SPICE simulation. Target of our survey is 1000paths each of which consists of randomly selected 25 cellsfor 65 nm standard logic cell library. In Fig. 3, the horizontalaxis shows path ID number and the vertical axis shows theranking of the path. The path of small ranking number haslarge path delay, i.e. the 1st in the ranking is the path withthe largest delay. Fig. 3 indicates the changes between theranking of each path delay for the cases of (ΔVthn,ΔVthp)= (40mV, 0mV) and (ΔVthn,ΔVthp) = (−40mV, −40mV).The line length shows the change of the ranking. That is,the longer line means that the path has larger change in theranking. It can be seen that about 96% of the paths havechanged their ranking though the amount of the changesvaries from path to path. In conventional test methods, the

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100

200

300

400

500

600

700

800

900

1000

0 100 200 300 400 500 600 700 800 900 1000

dela

y ra

nkin

g

path ID

Figure 3. The ranking changes of the path delays in 2 process conditions(ΔVthp=40mV, ΔVthn=0mV)–(ΔVthp=−40mV,ΔVthn=−40mV)

same set of delay tests which is generated deterministic (orsingle-corner) static timing, are used. However, in reality,paths that are critical at one process corner may not becritical elsewhere in the process space.

III. OVERVIEW OF PROPOSED ADAPTIVE TEST FLOWConsidering the results in the previous section, we pro-

pose an adaptive test flow. Our approach improves thequality of delay test by adaptively changing the set of test-paths for each chip, lot or wafer. In order to select criticalpaths effectively, our flow utilizes sensitivity parameters ofeach path and process parameters. The overview of theadaptive test flow is shown in Fig. 4. The proposed flowconsists of two phases.In design phase, sensitivity parameters are extracted from

SSTA. In the SSTA, path delay is calculated by the followingequation.

d = μd +∑

SpiΔpi + rnd (1)

where d is delay of a path, μd is the mean of the delay, Δpi

is the i-th process variation element, Spi is the sensitivityparameter of pi and can be extracted from SSTA, and rndis the random variable for random variation which followsa normal distribution with mean 0 and standard deviationσrnd. The path clusters corresponding process parametersare formed according to the sensitivity parameters. TheATPG generates test patterns corresponding to all pathclusters. Here, the cluster is a path group sharing the samecritical path candidates. In Fig. 4, ATPG generates five testpattern sets, that is, a common pattern used for all processconditions, an FF pattern used only for the case of fast-fast condition where pMOS (nMOS) transistor is fast (fast),an FS pattern used only for the case of fast-slow conditionwhere pMOS (nMOS) transistor is fast (slow), and so on.In test phase, process parameters of a chip, ΔVthp and

ΔVthn are measured as process characteristics. Here, ΔVthp

(ΔVthn) is the deviation from the typical value of thresh-old voltage of pMOS (nMOS) transistor. According to theobtained process parameters, we can decide the paths to betested and can test the chip using corresponding test patternsets. Although we only consider ΔVthp and ΔVthn and pi

Figure 4. The overview of the adaptive test flowfor process parameters here, other paramters such as thegate length of transister, L, can be also handled similarly. Inthis paper, we assume that there are no measurement errorsand also assume that we can use sensor circuits which canaccurately extract ΔVthp and ΔVthn[16], [17].Using the process parameters extracted from the sensor

circuits or test devices on scribe lines, the first and thesecond terms of Eq.(1) are determined. The systematiccomponents of path delay are revealed, and so we canchoose critical paths more accurately. Consequently, moreappropriate test patterns can be selected from test patternscorresponding to the process conditions. For example, if wefind a chip is fast-fast by process parameters extracted fromthe chip, we test the chip using the common and the FFpatterns.

IV. PARAMETRIC FAULT COVERAGE

In this section, we introduce a fault coverage for para-metric faults. We discuss the basic idea of parametric delayfault coverage (Subsection IV-A) and apply this idea to ouradaptive test flow (Subsection IV-B).

A. Basic Idea of Parametric Fault CoverageOur parametric fault coverage utilizes the PDF of the path

delay as in [7]-[9]. The path delay is calculated in the formof Eq. (1). Here, we supposeDPj is the delay of the j-th pathPj in the circuit (1 < j < N). N is the number of paths inthe circuit. The system clock period of the design is denotedby Tsys. Then the probability of having no parametric fault

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on the path j is represented as follows.

P{DPj ≤ Tsys} (2)

The probability that there is no parametric fault in any pathsin a circuit is expressed as follows.

P{DP1 ≤ Tsys, DP2 ≤ Tsys, · · · , DPN ≤ Tsys} (3)

where, P{DP1 ≤ Tsys, DP2 ≤ Tsys, · · · , DPN ≤ Tsys}is the joint probability of P{DP1 ≤ Tsys}, P{DP2 ≤Tsys}, · · · , P{DPN

≤ Tsys}. We approximate the jointprobability using statistical max operation as done in SSTA.Then, we can obtain probability of no parametric fault inthe circuit as follows.

P{max(DP1 , DP2 , · · · , DPN) ≤ Tsys}

= P{maxj(DPj ) ≤ Tsys} (4)

Therefore, the probability of having the parametric fault,pfall, is expressed as follows.

pfall = 1− P{maxj(DPj ) ≤ Tsys}= P{maxj(DPj ) > Tsys} (5)

On the other hand, given a set of test-paths which are in agiven test patter ST , the probability of the occurrence of theparametric fault on the test-paths, pftested, is as follows.

pftested = P{maxPj∈ST(DPj ) > Tsys} (6)

Therefore, we can define the parametric fault coverage ofthe circuit, pfc, as follows

pfc =P{maxPj∈ST (DPj ) > Tsys}

P{maxj(DPj) > Tsys} × 100 [%]

=pftested

pfall(7)

where pfall is given by SSTA tool. Since PT is the setof test-paths, denominator of Eq. (7) varies depending onthe number of paths in PT . Fig. 5 shows the concept ofthe pfc. The pfc is defined as the ratio of the probabilityof parametric faults for all paths and the probability ofparametric faults for test-paths.In order to achieve high pfc, we should test the paths

having a small slack margin and a large standard deviationor increase the number of test-paths. For example, we shouldtest paths in the order that a path have smaller (Tsys−μ)

σ . Ifthis value is small, the probability that the delay of the pathexceeds Tsys is high.

B. Application to Adaptive TestIn the proposed adaptive test flow, the systematic element

of path delay variation is estimated by measuring embeddedsensor circuits. Therefore path delay DPj varies from chipto chip, and pfall and pftested also vary from chip to chip.Given pf ′all and pf ′tested are pfall and pftested after the

Figure 5. The concept of the pfc

measurement, pfc′ which is the parametric fault coverageafter the measurement is given by Eq. (7).

pfc′ =P{maxPj∈ST

(D′Pj) > Tsys}

P{maxj(D′Pj) > Tsys} × 100 [%]

=pf ′tested

pf ′all

(8)

The pfc′ becomes more accurate than the pfc, becausethe calculation of the systematic component of the pfc isupdated based on the measurement results.Here, pfc′ can be only recaluculated after manufacturing

chips and measuring the sensor circuit. This indicates thatit is difficult to modify the circuit for the improvement ofthe pfc′. From the practical point of view, it is desirableto maximize the parametric fault coverage over all possibleconditions. Therefore, we consider the parametric fault cov-erage as the expectation in all the process space. Supposethat the probability of being ΔVthp = x and ΔVthn = yis Prob(x, y), pf ′all of this process condition is pf ′all(x, y),pf ′tested of this process condition is pf ′tested(x, y). Conse-quently, the expectation PFC over all process domains isgiven as follows.

PFC =

∫all x

∫all y

pf ′tested(x, y) · Prob(x, y) dydx∫

all x

∫all y

pf ′all(x, y) · Prob(x, y) dydx(9)

However, computation of Eq. (9) is difficult because theintegrand has to be represented as continuous function. Inthis paper, we use a discrete approximation for Eq. (9). Therange of ΔVthp is divided equally into m regions, the stepsize is assumed to be Δx. Similarly, the range of ΔVthn

is divided equally in n regions, the step size is assumedto be Δy. We calculate pfc′ for each representing processcondition, and calculated PFC as follows.

PFC =

∑i

∑j pf ′tested(i, j) · Prob(i, j) ·ΔxΔy

∑i

∑j pf ′all(i, j) · Prob(i, j) ·ΔxΔy

(10)

Although the pfc′ is a metric for a single process condition,PFC covers all process condition. So, we can estimate thetest quality for all chips before manufacturing. Although weuse 2 paramters, ΔVthp and ΔVthn, in this discussion, wecan also use other process parameters which indicate processcondition.

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0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9

0 200 400 600 800 1000

pfc’

The number of tested paths

pf_{all} = 3.22e-2

oursconv.

Figure 6. The relationship between pfc′ andthe number of test-paths

in (ΔVthp, ΔVthn) = (−80mV,80mV)

0

0.1

0.2

0.3

0.4

0.5

0.6

0 200 400 600 800 1000

pfc’

The number of tested paths

pf_{all} = 1.79e-3

oursconv.

Figure 7. The relationship between pfc′ andthe number of test-paths

in (ΔVthp, ΔVthn) = (0mV,0mV)

0

0.1

0.2

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0.4

0.5

0.6

0 200 400 600 800 1000

pfc’

The number of tested paths

pf_{all} = 7.52e-4

oursconv.

Figure 8. The relationship between pfc′ andthe number of test-paths

in (ΔVthp, ΔVthn) = (80mV,−80mV)

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Figure 9. The comparison of cumulative pfc′ for 1000 test-paths of ours and that of conv.

V. EXPERIMENTAL RESULTSA. Overview of experimentsIn this section, we present experimental results obtained

for our benchmark circuit STARC03 [3]. We compare ourcritical path test method with a conventional one. In bothcases, we suppose critical path tests are done for the worst1000 paths.1) Paths are tested in order of path delay size for thetypical condition (conv.)

2) Paths are tested in the order of the probability of theparametric fault corresponding to the process condi-tion (ours)

In general, it is expected that the proposed adaptive testis effective in the test cost reduction and the improvementof the test quality. We quantitatively evaluate the test costreduction and the improvement of the test quality for abovetest cases.Our experiment is on the fastest clock domain,

CLK A, of STARC03. Tsys of the clock domain isset to 3.4 ns and the number of paths is 17355. Syn-opsys Prime Time is used for extracting these paths.Targeted process conditions are 25 with all combina-tion of ΔVthp=(−80mV,−40mV,0mV,40mV,80mV) andΔVthn=(−80mV,−40mV,0mV,40mV,80mV). To get thetypical path delay corresponding to each process condition,we ran HSPICE simulation in these 25 conditions. Here, weassume σrnd = C√

num, where C is a constant value and

num is the number of cells in a path, considering that therandom variation of path delay becomes smaller for longerpath. We set C = 1, the delay of the longest path of CLK Acorresponds nearly 3σ point in the worst condition.We ran 250000 Monte Carlo simulations to obtain accu-

rate estimation of the statistical max operation. Paths areeasily clustered using (Tsys−μ)

σrnd, where μ is the average of

the path delay. There are 25 clusters corresponding to allprocess conditions. 1 cluster has 1000 paths in the order ofsmall (Tsys−μ)

σrndof them in each process condition.

In this experiment, we assume the ATPG can generate testpatterns for all paths. Also, we assume a correlation ρpath

between paths is 0.

B. ResultsFigs. 6-8 show how the pfc′ increases with the number of

test-paths. These figures are corresponding to the conditions(ΔVthp,ΔVthn)=(−80mV,80mV),(0mV,0mV),(80mV,−80mV), respectively. Similar results are obtainedfor the other process conditions, but they are omitted. Ineach of Figs. 6-8, the horizontal axis expresses the numberof test-paths, the vertical axis expresses the pfc′, the solidline expresses the results for proposed test flow (ours) andthe dashed line expresses the result for conventional testflow (conv.). (ΔVthp, ΔVthn)=(80mV,−80mV) is the fast-fast condition, so very few parametric fault are expected inthis condition. Consequently, the dashed line is always 0in Fig. 8. From these results, we can find that pfc′ always

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Table ITHE JOINT PROBABILITY OF ΔVthp AND ΔVthn

ΔVthn(mV)−80 −40 0 40 80

−80 2.8e-08 8.1e-07 2.5e-06 8.1e-07 2.8e-08−40 8.1e-07 2.4e-05 7.3e-05 2.4e-05 8.1e-07

ΔVthp 0 2.5e-06 7.3e-05 2.2e-04 7.3e-05 2.5e-06(mV) 40 8.1e-07 2.4e-05 7.3e-05 2.4e-05 8.1e-07

80 2.8e-08 8.1e-07 2.5e-06 8.1e-07 2.8e-08

Table IITHE COMPARISON OF PFC OF OURS AND THAT OF CONV.

ours conv.PFC 61.6 14.7

rises more steeply for our test flow than conventional test-path selection. This indicates that our test flow can achievehigher pfc′ with smaller number of test-paths. It can beconcluded that our test flow can reduce the test costs.Also we can see that higher cumulative pfc′ is obtained

over all the process conditions. In Fig. 6, the pfc′ of oursis 88.7%, the pfc′ of conv. is 66.2% at 1000 paths. Fig. 9shows the comparison between the cumulative pfc′ of ourtest flow and that of conventional test flow in all processconditions. The average pfc′ of ours is 63.8%, while thatof conv. is 17.3% in all process conditions. Our test flowcan achieve higher pfc′. In other words, our test flowcan improve test quality. From above results, the proposedadaptive test flow can test parametric faults more effectivelythan the conventional test flow.Next, we show the result for PFC. We assume both

ΔVthp and ΔVthn are N(0mV, ( 803 )2mV), and their joint

probability Prob is given as shown in Table I for eachprocess condition. Also, we assume there is no correlationbetween ΔVthp and ΔVthn. For example, Prob(80,−80) inthe case where ΔVthp = 80mV and ΔVthn = −80 mV is2.8e-08% in Table I. We can calculate PFC using TableI and Eq. (10). Table II shows the comparison of PFCbetween our proposed flow and the conventional test flow.From this table, PFC of our proposed flow is 4 timesas high as that of conventional test flow. The PFC ofconventional flow becomes small because it consideres onlyone process condition, while that PFC of our proposed flowis high, because our proposed flow considers all processconditions.

VI. CONCLUSIONIn this paper, we proposed an adaptive test flow utilizing

process conditions which are measured by a sensor circuitembedded on a chip or on a wafer. Our flow can test theparametric fault effectively. In design phase, the criticalpaths are clustered corresponding to process conditions, andATPG generates test patterns for the paths of all clusters.Moreover, we proposed a concept of parametric fault cov-erage, and evaluated the effectiveness of our adaptive testflow in experiments. From the results, we can find that theproposed test flow is more effective than conventional testflow in test cost reduction and test quality improvement.Especially, the proposed test coverage metric PFC of the

proposed test flow is about 4 times as high as that ofconventional flow.As future works, an effective path clustering method

and a smaller sensor circuit should be developed for moreeffective test cost reduction and test quality improvement.Experiments from the following 3 points are also importantfuture works.1) Evaluation using critical path ATPG2) Evaluation of correlation between path delays3) Evaluation of correlation between parameters

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