High Level Simulations of Real-Time Built-in Self-Test of S-D A/D Converters

Drago Strle, Janez Trontelj University of Ljubljana, EE department

Ljubljana, Slovenia drago.strle@fe.uni-lj.si

Abstract— In this paper we discuss a possibility to simplify modeling and simulation of testing strategy of high-resolution SD modulators. The methodology could be used for production as well as for real time built-in self-tests. We show that a pseudo-random signal is a good option for a signal source and that test method leads to efficient and cost-effective testing that can also be used for real time built-in self-tests. The method is theoretically analyzed and verified using Matlab simulations. The models of DUT (device under test) and reference digital circuits are simulated and the difference is demonstrated with simple area-efficient algorithm/hardware.

Keywords- Simulation of Built-in-self- test, real time test of mixed-signal circuits, Simulation of efficient test of mixed-signal circuits

I. INTRODUCTION Continuous advances in IC processing technologies offer a

possibility to produce integrated circuits with increased complexity and performance for almost the same or even reduced cost. Testing technology has not advanced at the same rate and the consequence is increased test time and associated cost, which could be as high as 30% of the total cost of the device [1].

Design and test of digital integrated circuits have been highly automated, while design and test of analog and mixed-signal circuit lag behind. The development cycle is prolonged and the quality of the test is problematic. Sometimes fail-safe reasons dictate the use of a BIST operating in real time in parallel with the function; in that case, the tester is not available, which complicates the problem even further. Companies have developed many ad hoc methods to tackle the problem of efficient testing of analog and mixed-signal circuits. To optimize test time, several strategies have been used ([2], [3], [4], [5], [6]). Many applications require high resolution A/D and/or D/A converters operating at high frequency (like S-D converters) and testing such embedded modules requires expensive tester hardware and a long test time for production testing, therefore more cost-efficient alternatives are necessary. One possible method is described in [7]. If a module is used in a fail-safe electronic system, then real time monitoring of its performances are necessary; in that case, precision signals and test hardware are not available. The best choice for precision and efficient signal generator is a Pseudo-Random Signal (PRS), which is simple to generate, requires very small silicon area and can be tested during digital tests.

The rest of the paper is organized as follows. In section II basic idea for efficient testing of high-resolution DS modulators is presented. In section III, the theoretical basis of pseudo-random tests is discussed. Section IV presents possible classification algorithm implementation, while section V presents one example. In section VI we discuss the efficiency of presented approach and provide suggestions for further work.

II. TESTING OF SD A/D CONVERTER Basic idea of efficient testing of a SD modulator is

presented in Figure 1. The DUT (analog modulator) and PRS source in the grey box are integrated on the same silicon. PRS generator is used as a dither to prevent limit cycles [10] and to linearize the quantizer. It must have a sufficiently long period and approx. white PDF (probability density function). Coefficients

dithak and

pak are implemented by a simple one or

multi-bit S-C D/A converters, using reference voltage of the modulator. They are therefore very accurate and linear for 1-bit. If multi-bit internal DAC (digital-to-analog converter) is anticipated, a suitable DEM (dynamic element matching) technique could be used instead [11]. In parallel to the analog modulator, a digital modulator is running. At first, inputs are connected to zero ( 0aU = ) and PRS is disconnected from the inputs, so noise transfer function (NTF) is measured. During the second test, signal PRS is connected to both inputs through coefficient pak , pdk and dither inputs, while input signal is disconnected; STF is tested in this way. Both modulators have exactly the same structure and equal coefficients; digital modulator is built with digital hardware having sufficiently long word-lengths so that the quantization noise due to fixed-point arithmetic is negligible. If only efficient production testing is anticipated then the digital modulator together with classification block is implemented outside the ASIC, possibly in software. If BIST is anticipated, the digital modulator and classification module must be implemented on-chip together with the analog modulator. Using modern short-channel 65nm CMOS technology the area of the digital modulator is estimated to be only about 50% of the area of the analog modulator. It is assumed that digital part is thoroughly tested using ATPG patterns. Both bit-streams and PRS signal are monitored with a classification block, which decides if the difference fits within the limits. Process parameters, matching, temperature and ageing change the behavior of the analog modulator, while digital modulator remains unchanged. If this

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arrangement is used, the production test-time could be shortened and an expensive tester not needed.

Figure 1. Block diagram of basic idea

III. THEORY OF PRS TESTING

Applying pseudo-random signal (PRS) with approx. white spectrum and Gaussian PDF to the inputs of two LTI (linear-time-invariant) systems (Figure 2, [8], [9]) running in parallel provides the opportunity to test the LTI systems. Noise [ ]x n is shaped by two generally different deterministic transfer functions with responses [ ]1h k and [ ]2h k . The responses are exactly the same for nominal transfer functions and if circuit noise is not present. Let us say that [ ]1h n corresponds to

analog discrete time system and [ ]2h n corresponds to digital

discrete time system that is always nominal. [ ]1h n deviates from nominal because of catastrophic faults (short or open circuits, etc.) and/or parametric faults (spread of parameters owing to process parameter changes, matching, etc). In addition, we assume that quantization noise of [ ]2h k is negligible. Cross-correlations between input signal and corresponding responses are proportional to the impulse-responses (1) and (2). Here we used basic relations for discrete time convolution and cross-correlation of time shifted noise sources 0,0.

[ ] [ ] [ ]1

2 21 1

0xy x x

km h m h kσ μ

∞

=

Φ = + ∑ (1)

[ ] [ ] [ ]2

2 22 2

0xy x x

km h m h kσ μ

∞

=

Φ = + ∑ (2)

Figure 2. Principle of testing a LTI system

Cross-correlations are thus proportional to impulse responses if mean value 2

xμ of a PRS noise is very small, or in other words if the PRS sequence is long enough. The difference of cross-correlations of LTI1 and LTI2 is proportional to the difference of impulse responses according to (3) because 2

xμ approaches 0 for a very long PRS sequence.

[ ] [ ] [ ]

[ ] [ ]{ }1 2 1 2,

21 2

xy xy

x

m m m

h m h mσΦ ΦΔ = Φ − Φ ≅

≅ − (3)

In an ideal case, both responses are the same and the difference is equal to zero. We can assume that for catastrophic faults it would be very easy to detect the difference, while for parametric faults the difference is small. We have to determine margins and how many samples of difference according to (3) must be calculated to have high probability of detecting faulty devices and low probability of misclassifications. The digital modulator and the analog modulator have equal nominal impulse responses [ ] [ ]2h n h n= , while real impulse response

is: [ ] [ ] [ ]1h n h n nε= + . The difference of cross-correlations is

proportional to the difference [ ]mε of both impulse responses and thus proportional to the difference of cross-correlations defined in (4).

[ ] [ ]2xm mσ εΔ ≅ (4)

The calculation efficiency could be improved by subtracting both responses first and then calculating cross correlation between difference [ ] [ ] [ ]1 2y n y n y n= − and [ ]x n . In that case, we get the same result as before given in (3). According to [13] it is sufficient to know 1p q+ + values of

( )h n to be able to calculate exact coefficients of transfer function having q zeroes and p poles. We thus need at least

1p q+ + cross-correlation coefficients to be able to estimate the differences between two LTI systems. Because the expectation operator cannot be calculated from the definition, we can use (for ergodic random signals) the time-average operation that is equal to (5) [13]:

[ ] [ ]{ }

[ ] [ ]0

1limN

N n

E x n y n m

x n y n mN→∞ =

+ =

= +∑ (5)

For sufficiently large N the estimate of mean of cross-correlation is equal to the cross-correlation according to [13]:

[ ]{ } [ ], ,x y x yE m mΦ ≅ Φ . This fact provides the opportunity for efficient calculation of cross-correlation coefficients.

Since SD modulators are non-linear systems the theoretical background described earlier could be used only if the modulator is linearized, which is achieved by adding an appropriate dither signal. In this way, eventual limit-cycles are decorrelated [10].

The modulators can be modeled according to (6) and (7), similar as in [12].

n⎡ ⎤⎣ ⎦x [ ] ( ){ }1

11h H zn −= Z

[ ] ( ){ }2

12h H zn −= Z

[ ] [ ] [ ]1 10k

y n x n k h k∞

== −∑

[ ] [ ] [ ]2 20k

y n x n k h k∞

=

= −∑

286

( ) ( ) ( ) ( ) ( ) ( ) ( )a a a a aY z STF z U z R z NTF z Q z P z⎡ ⎤ ⎡ ⎤= + + +⎣ ⎦ ⎣ ⎦ (6)

( ) ( ) ( ) ( ) ( ) ( )d d d d dY z STF z U z NTF z Q z P z⎡ ⎤= + +⎣ ⎦

(7)

Indexes a and d stand for “analog” and “digital” modulator respectively, ( )R z represents input-referred circuit noise of

analog modulator and ( )P z represents pseudo-random noise used for dither and test. Quantization noise for analog and digital modulators are assumed different, ( ) ( )a dQ z Q z≠ , because internal states might be different even if applied input signals are the same. At first, input signals are set to zero (

[ ] 0au n = , [ ] 0du n = ), so ( )aNTF z is measured. Cross-correlations between dither input and outputs are calculated according to (8) and (9) assuming that dither input [ ]p n is not

correlated to random circuit noise [ ]r k , quantization noise

[ ]aq k or [ ]dq k :

[ ] [ ] [ ]1

2 2,

0a xpp y xp a a

km ntf m ntf kσ μ

∞

=

Φ = + ∑ (8)

[ ] [ ] [ ]1

2 2,

0d xpp y xp d d

k

m ntf m ntf kσ μ∞

=

Φ = + ∑ (9)

For sufficiently long PRS sequence 2 0xpμ ⇒ the difference of cross-correlations become proportional to noise-transfer function difference: [ ] [ ]

, 1 , 1

2,p ya p yd xp ntfm mσ εΦ ΦΔ = , where

[ ] [ ] [ ]ntf a dm ntf m ntf mε = − . For test 2, PRS signal is connected to both inputs and to both dither inputs, so the following cross-correlations are calculated according to (10) and (11) :

[ ] [ ] [ ]{ }2, 2 ...p ya xp a am stf m ntf mσΦ = + + (10)

[ ] [ ] [ ]{ }2, 2 ...p yd xp d dm stf m ntf mσΦ = + + (11)

The difference of cross-correlations is proportional to the sum of differences of noise and signal transfer functions:

[ ] [ ] [ ]{ }, 2 , 2

2,p ya p yd xp ntf stfm m mσ ε εΦ ΦΔ ≅ + .

IV. CLASSIFICATION IMPLEMENTATION Efficient classification circuit can be implemented according to Figure 3. The average is replaced by first order low pass filter. PRS signal is delayed instead of [ ]y n to simplify the hardware using p q+ bit shift register. In addition, for one-bit modulators the bit-streams ( )ay n and ( )dy n are 1 bit wide, so the result of subtraction is within {±2}, and the multiplication circuitry is very simple. Each product ( )iv n is then LP-filtered. It requires a small portion of FPGA and/or little silicon area. If needed, a higher order digital-averaging filter can be used. The digital comparator then decides if results are within the limits.

Figure. 3. Possible classification circuit

How many samples do we need for reliable classification,

how many correlation coefficients are sufficient, what time do we need for the test, what is the probability of classifying correctly? The answers to these questions are not simple and are still under considerations. Available time and hardware resources are limited. In addition, the accuracy of a decision and its speed conflict with each other. Thus, appropriate selection of conflicting parameters (time, accuracy of classification, hardware resources available) must be optimized for particular applications. For example, accurate decision needs more time and/or higher order averaging process; fast decision usually leads to poor accuracy of classification.

V. EXAMPLE A fifth-order, single-loop, discrete-time modulator with

one-bit quantizer and feed-forward structure to reduce power consumption is used as an example. Over-sampling frequency is 32MHz and the band of interest is up to 400kHz. Internal signals are not possible to measure because of power consumption limitation (internal S-C stages have unit capacitances from 0.5pF down to 50fF). To verify presented methodology we built Simulink model for the modulator using floating-point arithmetic and classification circuit model using fixed-point arithmetic; we did not use VHDL-AMS modeling because Matlab model provides an order of magnitude shorter execution time compared to VHDL-AMS. For DUT (analog modulator) the most important analog performances, such as kT/C noise and op-amp non-idealities (A0 (open loop gain) , GBW (gain-bandwidth-product), noise, 1/f noise, offset, slew-rate, non-linearity etc.) are modeled. In addition, important parameters for the quantizer (offset, hysteresis, noise, latency, etc.) are included. Capacitor ratios can be perturbed according to the matching properties of the technology and size of unit capacitor. The classification circuit in our example calculates in real time eleven cross-correlation coefficient differences [ ]0ε through [ ]10ε using first order moving average filters. The results after the initial 2ms transient can be compared with the limits. We have run several simulations, trying to imitate different problems of analog modulator. A summary of

( )0 nε( ) ( )( ) ( )0

1

1o on n

v n

ε αεα

= −

+ −( )0v n

( )1v n

( )p qv n+

( ) ( )( ) ( )

1

1p q p q

p q

n n

v n

ε αε

α+ +

+

= −

+ −

( )1 nε

( )p q nε +

α

α

287

simulation results are presented on Figure 4. for NTF ([ ]

, 1 , 1,p ya p ydmΦ ΦΔ ) and on Figure 5. for STF ( [ ]

, 2 , 2,p ya p ydmΦ ΦΔ ).

The following conditions were simulated:

a) nominal circuit with no kT/C noise, no op-amp noise, and ideal op-amp characteristics (results marked with circles and text “Typical results” on Figure 4 and 5),

b) real op-amp characteristics inside allowed ranges,

c) allowed kT/C and op-amp noise,

d) the same as (c) with kT/C 10 times bigger (out of specs),

e) the same as (c) but slew-rate of the first op-amp 2 times lower than minimum allowed according to system level simulations,

f) the same as (c) but one capacitor changed by 30%,

g) linearity limit of the 1st amplifier reduced to 0.4V from 0.5V, so the opamp enters nonlinear range before,

h) Monte-Carlo simulation with capacitor ratios changes up to. 3 5%σ = .

On both figures, cross-correlation coefficients are plotted for different experiments. In both cases, some of the results are out of the limits (the limits are marked with squares with dot inside; they were defined through extensive Matlab simulations taking into considerations that some non-idealities are allowed according to the specifications).

VI. CONCLUSIONS In this article a possibility for efficient testing of high

resolution S-D modulators have been investigated. The basic idea and the theory behind have been explored. A block diagram of efficient testing has been presented together with possible implementation of classification circuitry. The aim of presented test methodology is to improve the efficiency of testing high-resolution converters, to reduce the price of production testing and to pave the way for real time BIST for such embedded modules.

Figure. 4. Monte Carlo simulation results: Cross-corr. differences for NTF

test: [ ], 1 , 1,p ya p yd

mΦ ΦΔ

Figure. 5. Monte Carlo simulation results: Cross-corr. differences for STF

test: [ ], 2 , 2,p ya p yd

mΦ ΦΔ

The investigation is far from finished and will be directed towards optimization of classification algorithms depending on test time and hardware available, required accuracy and speed of decisions, etc. BIST still needs switching between normal operation mode and test mode.

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