ieee journal of solid-state circuits, vol. 41, no. 11 ...ccharles/ece6730/lectures/lecture23.pdfat...

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006 2481

A Low-Power Dual-Band Triple-ModeWLAN CMOS Transceiver

Tadashi Maeda, Member, IEEE, Noriaki Matsuno, Shinichi Hori, Tomoyuki Yamase, Member, IEEE,Takashi Tokairin, Kiyoshi Yanagisawa, Hitoshi Yano, Robert Walkington, Keiichi Numata, Nobuhide Yoshida,

Yuji Takahashi, and Hikaru Hida, Member, IEEE

Abstract—This paper describes a 0.18- m CMOS direct-con-version dual-band triple-mode wireless LAN transceiver. Thetransceiver has a concurrent dual-band low-noise amplifierfor low power consumption with a low noise figure, a singlewidely tunable low-pass filter based on a triode-biased MOSFETtransconductor for multi-mode operation with low power con-sumption, a DC-offset compensation circuit with an adaptiveactivating feedback loop to achieve a fast response time withlow power consumption, and a ��-based low-phase-noise frac-tional-N frequency synthesizer with a switched-resonator voltagecontrolled oscillator to cover the entire frequency range for theIEEE WLAN standards. The transceiver covers both 2.4–2.5 and4.9–5.95 GHz and has extremely low power consumption (78 mAin receive mode, 76 mA in transmit mode—both at 2.4/5.2 GHz).A system noise figure of 3.5/4.2 dB, a sensitivity of 93/ 94 dBmfor a 6-Mb/s OFDM signal, and an error vector magnitude of3.2/3.4% were obtained at 2.4/5.2 GHz, respectively.

Index Terms—Complementary metal-oxide semiconductor(CMOS) transceiver, dual-band, frequency synthesizer, IEEE802.11a/b/g, low-noise amplifier (LNA), low-pass filter (LPF), or-thogonal frequency division multiplexing (OFDM), triple-mode,voltage controlled oscillator (VCO), wireless LAN (WLAN).

I. INTRODUCTION

THE IEEE802.11b standard 2.4-GHz band wireless LAN(WLAN) has been extensively incorporated into battery-

driven mobile devices, such as cell phones and PDAs, and isused throughout the world in corporate offices, at hot spots suchas in airports and railway stations, and also in home networks.Recently, even faster 11a (5-GHz band) and 11g (2.4-GHz band)standard WLAN products based on orthogonal frequency divi-sion multiplexing (OFDM) have been released, raising expecta-tions for further market expansion. In contrast to 2.4-GHz bandWLAN, which uses the same frequency band as microwaveovens and medical equipment, 5-GHz band WLAN representedby the 11a standard causes little radio interference and can beused at a speed sufficiently high to transmit high-definition TVsignals.

Although dual-band CMOS transceivers used in IEEE802.11a/b/g WLAN systems have been extensively developed[1]–[5], demands for even lower power consumption andmulti-standard transceiving have been increasing for portable

Manuscript received February 24, 2006; revised July 10, 2006.The authors are with the System Devices Research Laboratories, NEC Cor-

poration, Kawasaki, Kanagawa 211-8666, Japan (e-mail: [email protected]).

Digital Object Identifier 10.1109/JSSC.2006.883323

Fig. 1. Transceiver block diagram.

applications like future multi-functional cellular phones witha longer battery life. Using the conventional dual-band archi-tecture, which has a separate radio-frequency (RF) front-endfor each frequency band, increases the footprint. Moreover,achieving a higher data rate by means of higher order mod-ulation, a wider bandwidth, space-time diversity, and so onrequires a lower phase noise and/or a higher signal-to-noiseratio.

This paper describes a direct-conversion dual-band triple-mode WLAN CMOS transceiver with a low noise figure andlow power consumption. Section II describes the transmitter andreceiver architectures. Section III describes the circuit imple-mentation, particularly the key technical features for achieving:1) a concurrent-conjugate-matching dual-band, low-noiseamplifier (LNA) for low power consumption with a lownoise figure; 2) a single, widely tunable, low-pass filter (LPF)based on an adaptive DC-current-control circuit, triode-biasedMOSFET (ADTM) transconductor for multi-mode operationwith low power consumption; 3) a DC-offset compensationcircuit with an adaptive activating feedback loop (AAFL) toachieve a fast response time with low power consumption; and4) a -based low-phase-noise fractional-N frequency synthe-sizer with a switched resonator, voltage-controlled oscillator(VCO) to cover the entire frequency range for the IEEE WLANstandards. Section IV presents some of the measured results,and Section V concludes the paper with a brief summary.

0018-9200/$20.00 © 2006 IEEE

2482 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 11, NOVEMBER 2006

Fig. 2. Schematic diagram of dual-band LNA.

II. ARCHITECTURE

As shown in Fig. 1, both the receiver and transmitter use di-rect conversion and have fully differential signal paths. The re-ceive path consists of a concurrent dual-band LNA followed bya direct down conversion mixer (MIX) and an analog base-bandblock. The base-band block consists of two programmable gainamplifiers (PGAs) with fast DC-offset compensation circuits,fourth-order Butterworth LPFs based on adaptive DC-currentcontrol, and a triode-biased (ADTM) transconductor.

A previously reported 5-GHz band LNA topology [6] wasmodified and used to implement the dual-band design. Aconcurrent dual-band matching scheme is used to providedual-band operation without increasing the circuit area. The2.4- and 5-GHz band signals are amplified by simply changingthe capacitor combination of the LNA matching circuit, whichdoes not increase the chip area. Since low insertion-loss passiveswitches are commercially available, RF filters and off-chippassive switches combination can be used to avoid interferencewithout significantly increasing noise figure.

The signal is then directly down-converted to base-band sig-nals through a pair of mixer and amplified by the PGA witha fast DC-offset cancellation loop. The base-band signals arelow-pass filtered with a widely tunable LPF designed for mul-tiple-channel-bandwidth systems (such as those compliant withthe latest Japanese standard and with channel bandwidths of5, 10, and 20 MHz). To reduce the effect of flicker noise, allthe analog base-band circuits use pMOS transistors as inputdevices. This is because flicker noise in pMOS transistors istypically one to two orders of magnitude lower than that innMOS transistors. Finally, the signal is converted into a dig-ital bit stream by a 10-bit 80-MHz analog-to-digital converter(ADC) of our companion base-band chip.

The transmit path is composed of low-pass filters, double-balanced modulators (MODs), and separate driver amplifiers(DAs) with envelope detectors for the 2.4- and 5-GHz bands,respectively.

The DAs convert the differential signals into single-endedones for use with off-chip power amplifiers (PAs). Using off-chip high-efficiency PAs leads to a reduction in overall systempower. The base-band signal from the 10-bit 80-MHz digital-to-analog converter (DAC) of the companion base-band chip islow-pass filtered by the LPFs, which are identical to those inthe receive path, and up-converted to RF signals through corre-sponding single-sideband doubly balanced mixers.

Due to the direct-conversion scheme of the transceiver, thefractional-N frequency synthesizer has to generate the in-phaseand quadrature local oscillator (LO) signals for the 2.4- and5-GHz bands at the same frequency as the transmitter and/orreceiver signal carriers. A conventional configuration, in gen-eral, has a single-band VCO with a frequency two-thirds thatof the 5-GHz LO to avoid pulling by the transmitter circuit [7],and the desired frequencies are generated using many dividersand/or mixers. This configuration thus consumes much powerand has a narrow frequency tuning range.

Our transceiver has a dual-band VCO with an oscillationfrequency twice that of the desired LO frequency. This con-figuration generates the desired I/Q signals by using only onedivider and does not require additional mixers, selectors, and/ordividers. The dual-band VCO, however, should be capable ofwide- and high-frequency oscillation to cover the entire WLANfrequency range. The oscillation frequency is 9.8 to 11.9 GHzfor the 5-GHz band and 4.8 to 5.0 GHz for the 2.4-GHz band.A switched resonator with a back-gate impedance-controlledMOS switch reduces parasitic capacitance, which interfereswith the required performance.

Moreover, to achieve a low-phase-noise local signal evenat narrow frequency bandwidths of 5, 10, and 20 MHz, a

-based frequency synthesizer architecture is used.

III. CIRCUIT IMPLEMENTATION

A. Receiver

The dual-band LNA consists of a fully balanced, two-stagecascaded amplifier (LNA1, LNA2) with a concurrent-conju-

MAEDA et al.: A LOW-POWER DUAL-BAND TRIPLE-MODE WLAN CMOS TRANSCEIVER 2483

Fig. 3. Simulated results for LNA1 with constant NF circles in terms of sourceimpedance.

gate-matching circuit, a dual-band LC resonator switch, and anattenuator (Fig. 2).

In the first stage LNA (LNA1), wide-frequency-band charac-teristics are achieved by using a low-pass input-matching cir-cuit; high linearity with high common-mode noise immunityis achieved by using a tail resonator. Fig. 3 shows simulatedconstant noise figure (NF) circles at 2.48 and 5.2 GHz in termsof source impedance, where the source impedance seen fromLNA1 was swept from 2.4 through 5.95 GHz. This figure showsthat a NF below 2.5 dB can be obtained in the 2.4- and 5-GHzbands. The two circles are large enough for small increments ofNF. This means that variations in matching network impedancedue to component tolerances in production will not degrade theNF drastically.

At high input power, LNA2 turns off by means of thedual-band LC resonator passive switch and the signal bypassesthrough the attenuator, thus this leads to large third-orderinput-referred intercept (IIP3). The switch configuration copeswith the low-impedance state created by the input and outputcapacitances of LNA2 when it is in the off state. When LNA2turns off in the 5-GHz band, switches S1, S2, S3, and S4 areon, and S5, S6, S7, and S8 are off. The inductances for L5–L6and L7–L8 were chosen to resonate with input capacitancesand output capacitances of the LNA2 at the 5-GHz band,respectively. The result is high impedance for the LNA2 inputand output. In the 2.4-GHz band, switches S1, S2, S3, and S4are off, and S5, S6, S7, and S8 are on. This results in resonancefor the parallel-connected inductors and capacitors (L1–L4,C1–C4) and in a stable high impedance state. Consequently,the signal is not transmitted to LNA2 in the off state for eitherband.

Under this condition, LNA total power consumption is smallby turning off LNA2.

At low input power levels, a large power gain is requiredto achieve a low receiver NF for both the 2.4- and 5-GHzbands. Under this condition, all switches (S1–S8) are off.The output-matching circuits of LNA1 are parallel resonantcircuits of Lo1-Co1 and Lo2-Co2; the input-matching circuitsof LNA2 are series resonant circuits of L1-Ci1, and L2-Ci2.Here, Co1 and Co2 are the parasitic capacitances for the LNA1

Fig. 4. Simulated constant available-gain circles at 2.4 and 5.2 GHz in termsof LNA1 output impedance.

output nodes, Ci1 and Ci2 are the parasitic capacitances for theLNA2 input nodes. When the parameters of the parallel- andseries-connected LC circuits are set at the following equations:

The reactance of the LNA1 output matching circuitand that of the LNA2 input matching

circuit have the same value withopposite signs at the both frequencies, where and are theangular frequencies of 2.4 and 5.2 GHz, respectively, isthe inductance of Lo1 and Lo2, is the output capacitanceof LNA1, is the inductance of L1 and L2, and is theinput capacitance of LNA2. Thus, the impedances of the twobands are matched by using this configuration without any othercomponents. Since there is no active device between LNA1 andLNA2, this configuration minimizes noise figure [6].

Although the linearity of the receiver under this conditionis dominated by the IIP3 of LNA2, LNA2 does not consumelarge amounts of power to achieve high IIP3. This is becausethe output power under these conditions is low.

Fig. 4 shows a Smith chart with the loci of these matchingcircuit impedances against frequency and the constant avail-able-gain circles at 2.4 and 5.2 GHz in terms of LNA1 outputimpedance. It shows that this circuit has conjugate matchingat 2.4 and 5 GHz. The chart also indicates that variations inthe matching network impedance do not drastically degrade thegain.

The down-conversion mixer has a common-gate configura-tion (Fig. 5), which operates as a passive mixer and thus yieldsa high IIP3. Phase and gain mismatch are minimized by havingthe I/Q signal paths share a current source.

Each PGA has folded configuration with source-degenerationpMOS, as shown in Fig. 6. This configuration can increase lin-earity because of small stacking transistors. The gain is con-trolled by changing the resistor combination between the differ-ential signal nodes. The 7-bit digital signal controls the resister


Fig. 5. Schematic circuit diagram of down-conversion mixer.

Fig. 6. Schematic circuit diagram of programmable gain amplifier.

Fig. 7. Schematic circuit diagram of DC offset cancellation circuit.

combination of each PGA; this can achieve 66-dB tuning witha gain step of 1 dB.

The static DC offset of the PGA input signal is compen-sated for by using a high-pass filter with a cut-off frequency of150 kHz (Fig. 7). The high-pass filter consists of MIM capacitorC1 and pMOS (Q1, Q2). The Q1 and Q2 operate not only as ahigh-resistance resistor but also as a bias circuit for PGA.

The dynamic DC offset is compensated for by using an AAFLconsisting of an offset voltage detecting circuit and a tri-statebuffer (Fig. 7). When the PGA output voltage exceeds the upperlimit of the input-referred P-1 dB for the following circuit, theoffset voltage detecting circuit activates the feedback loop. Thatis, the tri-state buffer output is set to low so that the node voltagerapidly decreases. When the DC level exceeds the lower limit,the node voltage increases quickly. Since the PGA has a low-

Fig. 8. Schematic circuit diagram of widely tunable fourth-order Butterworthlow-pass filter.

Fig. 9. Schematic circuit diagram of ADTM transconductor.

pass characteristic, the response of the PGA output signal isslow compared with that of the input signal. This causes anovershoot response of the loop, which minimizes the residualDC offset. Fast response with negligible power consumptionis achieved since the feedback loop is activated only when theoutput signal exceeds the input referred P-1 dB for the followingcircuit.

Fig. 8 shows a schematic diagram of a widely tunablefourth-order Butterworth low-pass filter consisting of twobi-quad filters with a cascade connection. The filter employsnewly developed adaptive DC-current-control triode-biasedMOSFET transconductor (ADTM transconductor) core forwide frequency tuning and high linearity.

In the transconductor core, shown in Fig. 9, the output signalof the cascode amplifier, which is composed of Q1, Q2, and cur-rent source CS0, is fed back to the Q1 drain through Q3, so thatQ1 operates under constant drain-to-source bias condi-tions in the triode region. The dc current and transcon-ductance of this circuit are determined by those of Q1:

where is the input voltage to the gate, is the thresholdvoltage, and is the factor. These equations indicate that

has linear dependence on under constant . Thisresults in high linearity. Although the large is required athigh , the adaptive DC-current-control circuit controls cur-rent CS1 and CS2 so as to compensate for the excess DC-current


Fig. 10. Schematic circuit diagram of a parallel configuration ADTMtransconductor.

of current mirror circuit (Q3 and Q4) even under a high-gm con-dition. This is because the current mirror circuit operating in thesaturation region does not need a large DC current.

The transconductor is incorporated into the filter as a parallelconfiguration that operates in the balance mode (Fig. 10). Thisprovides constant differential transconductance. The drain cur-rent signal of Q5 has the same magnitude and opposite polarityas that of Q3n because of the mirror circuit comprising Q6n,Q7n, and Q5. Thus, the desired differential signals from Q4 andQ5 are in-phase, that is, amplified, while the undesired common-mode signals caused by the nonlinearity are out-of-phase, thatis, cancelled out. This leads to high linearity for a large inputsignal.

The simulated tuning range of the fourth-order Butterworthlow-pass filter was from 2 to 12 MHz.

B. Transmitter

The baseband I/Q signals in the transmitter chain are gen-erated by 10-bit 80-MHz DACs in a companion digital base-band chip. The transmit baseband LPFs are identical to the onesused in the receiver. After reconstruction filtering, the modu-lated signal is up-converted into each RF frequency band bysingle-sideband doubly balanced mixers. The differential signalis subsequently converted into a single-ended one and furtheramplified by DAs. Off-chip power amplifiers are used to con-serve overall system power. LO leakage in a direct-conversiontransmitter occurs at the center of the RF signal frequency band.It is not possible to eliminate this with an RF filter.

Although LO leakage and/or I/Q mismatches can be causedby various imbalances and mismatches both in the RF domainand baseband, they can be compensated for by applying a base-band DC offset, a phase-offset and a gain-offset. An active feed-back system can correct most of these errors by measuring theRF constellation under a known test signal and using a linearcorrelator, commonly placed in the digital domain of the trans-ceiver, to correct the offsets. Fig. 11 shows a schematic of theenvelope detector, which are placed in each transmitter path fol-lowed by a low-pass filter and common drain output buffer tocompensate for LO leakage and I/Q mismatches. The detector

Fig. 11. Schematic circuit diagram for envelope detectors.

Fig. 12. Schematic block diagram of ��-based dual-band low-phase-noisefractional-N frequency synthesizer.

consists of a resistor-loaded inverter in which a MOSFET hasbeen pre-biased immediately below the threshold voltage, thusthe circuit behaves as Class-B amplifier. The sensitivity to tran-sistor corner variations is reduced by using current mirror bi-asing. The low-pass filter has a 20-MHz cutoff frequency and48-dB suppression.

C. Phase-Locked Loop (PLL)

The -based dual-band low-phase-noise fractional-N fre-quency synthesizer consists of a dual-band VCO with a digitallycontrolled MIM capacitor bank, a divide-by-two circuit gener-ating quadrature LO signals, an LO buffer, a pulse-swalloweddual-modulus divider, a third-order modulator, a charge-pump (CP) with a cascode current mirror circuit, and a second-order off-chip loop filter (LF) (Fig. 12).

The dual-band VCO has a switched resonator with aback-gate impedance controlled MOS switch (Fig. 13). Theresonator consists of tapped inductors with pMOS switches anda 5-bit weighted digitally controlled MIM capacitor array. Athigh frequencies (9.6–11.9 GHz), unused turns of the inductorsare shorted by the pMOS switches, reducing the inductance.When the switches are in off state, the inductance is large andthe VCO oscillates at low frequencies. Since the back-gateimpedance of the pMOS switches in the off state is set high


Fig. 13. Schematic circuit diagram for dual-band VCO.

by disconnecting the n-well from the , this configurationreduces the drain-to-substrate parasitic capacitance in the offstate. The circuit can thus match two different tuning rangesand achieve a wide tuning range with a compact layout. TheVCO gain is reduced without sacrificing the tuning range bydividing both frequency ranges into a total of 22 bands; aband is selected by changing the combination of capacitors inthe MIM capacitor bank. Continuous frequency tuning withineach band is achieved by using accumulation-mode nMOSvaractors. The frequency band is selected as follows. Whenthe loop filter output voltage exceeds the VCO tuning range,the digital controller selects the appropriate frequency band bychanging the capacitor combination. The controller also setsthe loop filter voltage to the middle of the tuning voltage rangeand synchronizes the swallow counter output to the referencesignal. This prevents unwanted ripples in the loop filter voltageand leads to high-speed frequency-band selection.

The nMOS switches in the capacitor bank have a configura-tion similar to that of the tapped inductor. This configuration re-duces the drain-to-substrate parasitic capacitance in the off stateto half, so this VCO configuration enables high-frequency oscil-lation with low phase noise.

Since the fractional-N synthesizer permits operation with ahigh-frequency reference, the division ratio of the phase-lockedloop can be set lower to achieve low in-band phase noise. How-ever, fractional operation introduces quantization noise and thespurious signal. The PLL noise due to the modulator as afunction of the modulator order is given by [9]

where is the synthesizer closed loop transfer function,is the spectrum of the quantization noise, is the sam-

Fig. 14. Simulated carrier-to-noise ratio for �� modulator.

Fig. 15. Die photograph of transceiver.

pling frequency, is the offset frequency, is the modulatororder, is the charge pump gain, is the VCO gain, and

is the transfer function for the loop filter. is given by, and

Fig. 14 shows the simulated carrier-to-noise ratio (CNR)for the modulator as a function of the modulator order; a40-MHz reference clock was used as the sampling clock forthe modulator, and the cutoff frequency of the loop filter wasset to 300 kHz. The third-order configuration is best becauseit results in the lowest noise characteristics within the desiredoffset frequency band. Since the main cause of the spurioussignal in the PLL is the nonlinearity of the charge pump, a cas-code current mirror configuration is used in the charge-pumpcircuit (Fig. 12). This circuit enlarges the output impedance of


Fig. 16. Total receiver gain and receiver noise figure as a function of baseband output frequency at (a) 2.4 and (b) 5.2 GHz.

Fig. 17. Noise figure as a function of LO frequency at 2.4 and 5.2 GHz.

the current source, thereby reducing the sourcing and sinkingcurrent mismatch. This reduces the level of the spurious signal.

D. Power Consumption

The simulated power consumption in each building block isas follows. In the receive path, RF front end including LNA andMIX consumes 20 mA, the analog baseband block includingPGAs and LPFs consumes 14 mA. The power consumption ofthe analog baseband in transmit path is 10 mA, and that of the RFblock including MOD and DAs is 40 mA. The power consump-tion of the PLL is 22 mA. The local buffer consumes 20 mA inRx mode, and 8 mA in Tx mode.

IV. MEASURED RESULTS

The transceiver was fabricated using a 0.18- m one-poly six-metal (1P6M) CMOS process. A die photograph of the trans-ceiver is shown in Fig. 15. The die was 4.2 by 4.1 mm. Thetotal receiver gain and receiver noise figure at 2.4 and 5.2 GHzare plotted in Fig. 16(a) and (b) as functions of the basebandoutput frequency. Noise figures of 3.5 and 4.2 dB were obtainedat 2.4 and 5.2 GHz, respectively. These values are comparableto the lowest values reported to date for dual-band transceivers[1]–[8].

As shown in Fig. 16, the maximum gain for the total re-ceive path was 75 dB for both frequencies. The total gain wascontrolled with a 1-dB gain step from 8 to 75 dB. The figure

Fig. 18. Input-output characteristics of receiver path in maximum and min-imum gain modes at (a) 2.4 and (b) 5.2 GHz.

Fig. 19. Transient responses of DC-offset cancellation circuit, including PGA,with (a) positive and (b) negative DC offsets.

also shows that the cutoff frequency for the 5-GHz band canbe tuned from 2.5 to 10 MHz, so the transceiver can supportmultiple-channel bandwidth systems. The small increase in thenoise figure at 5 MHz mode was caused by the noise of feed-back circuit in LPF.

The receive path current consumption was 78 mA at high gainmode for both frequency bands.

Fig. 17 shows the noise figure as a function of the local oscil-lator frequency for the 2.4- and 5-GHz bands at the maximumgain. The noise figure deviation was small, within 0.1 dB for2.4–2.5 GHz, and 0.65 dB for 4.9–5.95 GHz. The input-output


Fig. 20. LO phase noise characteristics at (a) 2.4 and (b) 5.2 GHz.

Fig. 21. 64 QAM transmission constellation at 2.4 and 5.2 GHz.

characteristics of the receive path in the maximum and min-imum gain modes for the 2.4- and 5-GHz bands are plotted inFig. 18(a) and (b). For the 2.4-GHz band, the local frequencywas 2.48 GHz, and two-tone frequencies are depicted. The IIP3was 7 dBm and 5 dBm for the maximum and minimum gainmodes, respectively. For the 5-GHz band, the local frequencywas 5.24 GHz, and two-tone frequencies are again depicted. TheIIP3 was 5 and 21 dBm for the maximum and minimum gainmodes, respectively.

The dynamic performance of the DC-offset cancellation loopwas measured by applying a sinusoidal signal superimposed ona step signal. Fig. 19(a) and (b) shows the transient responsesof the loop with positive and negative DC offsets, respectively.The vertical axis is the voltage difference from the input referredP-1 dB for the ADTM-LPF; the step voltage was 300 mV. Thepositive and negative DC-offset settling times were 0.05 and0.08 s, respectively, and the loop had no serious overshooting.

Fig. 20(a) and (b) plot the LO phase noise characteristicsat 2.4 and 5.2 GHz, respectively; the bandwidth of the loopfilter was set at 300 kHz. The phase noise was 95 dBc/Hz ata 100-kHz offset frequency for both frequencies. At a 1-MHzoffset, a phase noise of 110 dBc/Hz was obtained for bothfrequencies. The integrated rms phase errors within the signalbandwidth of 1.7 degree and 1.87 degree were obtained at 2.4and 5.2 GHz, respectively. The spurious signal of the PLL wasless than 66 dBc. In 6-Mb/s mode, sensitivities of 93 and

94 dBm were obtained at 2.4 and 5.2 GHz, respectively. In36-Mb/s mode, the receiver achieved a sensitivity of 80 dBmfor both frequencies. These sensitivities do not include the balunloss which was used in this measurement.

TABLE ISUMMARY OF TRANSCEIVER PERFORMANCE

Fig. 21 plots the 64 QAM transmit constellations for outputfrequencies of 2.4 and 5.2 GHz. The error vector magnitudeswere 3.2 and 3.4% at 2.4 and 5.2 GHz, respectively; the outputpower was 10 dBm. Current consumption was 76 mA at asupply voltage of 1.8 V.

The measured transceiver performance is summarized inTable I.

V. CONCLUSION

The developed transceiver supports worldwide dual-bandWLAN systems with frequency ranges of 2.4 to 2.5 GHz and4.9 to 5.95 GHz, and channel bandwidth ranges of 5 to 24 MHz.The receiver noise figures were 3.5 and 4.2 dB, respectively, ata maximum gain of 75 dB. The receiver IIP3 in maximum gainmode was 5 and 21 dBm at 2.4 and 5.2 GHz, respectively.The EVMs of the transmit signal were 3.2 and 3.4%, respec-tively. The current consumption was 78 mA for the receive pathand 76 mA for the transmit path.

ACKNOWLEDGMENT

The authors are grateful to Mr. Takuji Mochizuki, Mr.Masaho Mineo, Dr. Shinichi Tanaka, and Dr. Naotaka Sumihirofor their valuable comments and continuous encouragementthroughout this work.


REFERENCES

[1] R. Ahola et al., “A single-chip CMOS transceiver for 802.11a/b/gwireless LANs,” IEEE J. Solid-State Circuits, vol. 39, no. 12, pp.2250–2258, Dec. 2004.

[2] M. Zargari et al., “A single-chip dual-band tri-mode CMOS transceiverfor IEEE 802.11a/b/g wireless LAN,” IEEE J. Solid-State Circuits, vol.39, no. 12, pp. 2239–2249, Dec. 2004.

[3] K. Vavelidis et al., “A dual-band 5.15–5.35-GHz, 2.4–2.5-GHz 0.18�m CMOS transceiver for 802.11a/b/g wireless LAN,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1180–1184, Jul. 2004.

[4] L. Perraud et al., “A direct-conversion CMOS transceiver for the 802.11a/b/g WLAN standard utilizing a Cartesian feedback transmitter,”IEEE J. Solid-State Circuits, vol. 39, no. 12, pp. 2226–2238, Dec. 2004.

[5] Z. Xu et al., “A compact dual-band direct-conversion CMOS trans-ceiver for 802.11a/b/g WLAN,” in IEEE Int. Solid-State Circuits Conf.(ISSCC) Dig. Tech. Papers, 2005, pp. 98–99.

[6] T. Maeda et al., “A low-power-consumption direct-conversion CMOStransceiver for multi-standard 5-GHz wireless LAN systems withchannel bandwidth of 5–20 MHz,” IEEE J. Solid-State Circuits, vol.41, no. 2, pp. 375–383, Feb. 2006.

[7] A. Behzad et al., “A 5-GHz direct-conversion CMOS transceiver uti-lizing automatic frequency control for the IEEE 802.11a wireless LANstandard,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2209–2220,Dec. 2003.

[8] A. Behzad et al., “A 4.92–5.845 GHz direct-conversion CMOS trans-ceiver for IEEE 802.11a wireless LAN,” in RFIC Symp. Dig. Papers,2004, pp. 335–338.

[9] T. A. D. Riley et al., “Delta-sigma modulation in fractional-N fre-quency synthesis,” IEEE J. Solid-State Circuits, vol. 28, no. 5, pp.553–559, May 1993.

Tadashi Maeda (M’05) received the B.E. andM.E. degrees in electronics engineering from theToyohashi University of Technology, Toyohashi,Japan, in 1981 and 1983, respectively, and the D.E.degree in electronic engineering from the Universityof Tokyo, Tokyo, Japan, in 1999.

In 1983, he joined NEC Corporation, wherehe researched and developed GaAs digital LSIs.Since 1999, he has developed RF CMOS circuitsas a principal researcher in NEC’s System DevicesResearch Laboratories.

Dr. Maeda is a member of the International Solid-State Circuits ConferenceWireless Communication Subcommittee, the IEEE Solid-State Circuits Society,and the Institute of Electronics, Information and Communication Engineers.

Noriaki Matsuno received the B.E. and M.E.degrees in electrical engineering from NagoyaUniversity, Nagoya, Japan, in 1991 and 1993,respectively.

He joined NEC’s Microelectronics ResearchLaboratories in 1993, where he researched anddeveloped GaAs FET devices for high-speed digitalLSIs. From 1995 to 1999, he researched and devel-oped power MOSFETs and power MOS MMICs.From 1999 to 2003, he worked on device design,modeling, and simulations for SiGe HBTs. Since

2001, he has been working on the development of RF CMOS circuits. He isnow a principal researcher in NEC’s System Devices Research Laboratories.

Mr. Matsuno is a member of the Institute of Electronics, Information andCommunication Engineers.

Shinichi Hori received the B.E. degree in mechanicsand the M.E. degree in electronics from the Uni-versity of Tokyo, Tokyo, Japan, in 1998 and 2000,respectively.

He joined NEC Corporation in 2000 and has beenresearching and developing RF CMOS circuits in theSystem Devices Research Laboratory.

Mr. Hori is a member of the Institute of Elec-tronics, Information and Communication Engineers.

Tomoyuki Yamase (M’05) received the B.S. degreein electrical engineering from Michigan State Univer-sity, Lansing, in 2001.

He joined NEC Corporation in 2002 and has beendeveloping RF CMOS circuits in the Ultra HighSpeed Device Research Laboratory of the SystemDevices Research Laboratories.

Mr. Yamase is a member of the IEEE Solid-StateCircuits Society.

Takashi Tokairin received the B.E. and M.E.degrees in electronic engineering from TohokuUniversity, Sendai, Japan, in 2001 and 2003,respectively.

He joined NEC Corporation in 2003 and has beenresearching and developing RF CMOS circuits in theSystem Devices Research Laboratory.

Mr. Tokairin is a member of the Institute of Elec-tronics, Information and Communication Engineers.

Kiyoshi Yanagisawa received the B.E. and M.E. de-grees in information science from Tohoku University,Sendai, Japan, in 1998 and 2000, respectively.

He joined NEC Corporation in 2004 and has beenresearching and developing mixed-signal CMOS cir-cuits in the System Devices Research Laboratory.

Hitoshi Yano received the B.E. and M.E. degreesin electrical engineering from Hokkaido University,Sapporo, Japan, in 1985 and 1987, respectively.

He joined NEC’s Microelectronics Research Lab-oratories in 1987. From 1987 to 1994, he researchedand developed GaAs FET devices, especially fordevelopment of two-dimensional device simulationtechnology. Since 1994, he has been designing GaAsheterojunction MMICs and CMOS MMICs.

Mr. Yano is a member of the Institute ofElectronics, Information and Communication

Engineers of Japan.

Robert Walkington received the B.Eng., M.Res.,and Ph.D. degrees in electronic and electrical engi-neering from University College London, London,U.K., in 1998, 1999, and 2002, respectively. HisPh.D. work, in collaboration with Nokia Networks,U.K., was in the area of noise-shaping fractional-Nfrequency synthesizers.

In 2002, he joined NEC’s System Device ResearchLaboratories, where he has worked on the design ofRF and mixed-signal CMOS circuits and integratedtransceiver systems. His current research interests

include system/circuit level co-optimization and broadband reconfigurableRFIC design.


Keiichi Numata received the B.E. and M.E. degreesin electrical engineering from Hokkaido University,Sapporo, Japan, in 1990 and 1992, respectively.

In 1992, he joined NEC Corporation, where heresearched and developed GaAs digital LSIs. Since1999, he has been developing antenna switch ICs andRF CMOS circuits. He is now a principal researcherin the System Devices Research Laboratories.

Nobuhide Yoshida received the B.E. and M.E. de-grees in electrical engineering from Keio University,Tokyo, Japan, in 1992 and 1994, respectively.

He joined NEC’s Microelectronics Research Lab-oratories in 1994, where he researched and developedGaAs digital LSIs. Since 2002, he has been devel-oping RF CMOS circuits in the System Device Re-search Laboratories.

Mr. Yoshida is a member of the Institute of Elec-tronics, Information and Communication Engineers.

Yuji Takahashi received the B.E. and M.E. degreesin electrical engineering from Kobe University, Kobe,Japan, in 1991 and 1993, respectively.

He joined NEC’s System Devices ResearchLaboratory in 1993 and has been researching anddeveloping RF and high-speed ICs for wirelesscommunication.

Mr. Takahashi is a member of the Institute of Elec-tronics, Information, and Communication Engineersof Japan.

Hikaru Hida (M’92) received the B.E. and M.E. de-grees in electronics from Osaka University, Osaka,Japan, in 1980 and 1982, respectively, and the D.E.degree from the University of Tokyo, Tokyo, Japan,in 1995.

He joined NEC Corporation in 1982 and is nowa Senior Manager in the System Devices ResearchLaboratories. He has helped develop high-speedGaAs heterojunction FETs, analog and digitalLSIs, and cutting-edge technologies for Si CMOSe-DRAM ASICs. His current interest is the research

and development of RF-CMOS LSI core designs and GaAs MMIC/RFmodules for mobile, WLAN, and WPAN applications, as well as that ofhigh-speed CMOS SERDES and 10–40-Gb/s GaAs and InP ICs for opticalcommunications.

Dr. Hida is a member of the IEEE Solid-State Circuits Society.

ieee journal of solid-state circuits, vol. 41, no. 11 ...ccharles/ece6730/lectures/lecture23.pdfat...

Documents