ime technical proposal high density fowlp for mobile ...s hd fo... · high density fowlp for mobile...
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High Density FOWLP Consortium Forum
High Density FOWLP
for Mobile Applications
IME Technical Proposal
22 April 2014
High Density FOWLP Consortium Forum
Conventional PoP, with TMV
Packaging driver for portable / mobile applications
Key drivers/needs •Smaller form-factor lower profile, substrate-less•Higher performance higher speed, more I/O •Higher integration multi chip integrated platform •Low cost less processing step, low cost materials
Substrate based side-by-side package
Thin core /coreless subst. with side-by-side die within package
Stacked chip approach Side-by-side
Packaging solutions options
IC-1IC-2
IC-3
Low cost, high density, integrated packaging solutions is needed
Current
PoP with conventional FOWLP
PoP with high density FO Multi-chip integrated on low cost high density WLP
-No substrate-Lower profile-Short interconnect-Wafer level process-Lower cost
Proposed package
© 2014 A*STAR Institute of Microelectronics and Proprietary
High Density FOWLP Consortium Forum
Pri
ce p
er
pin
(c$
)
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
50 100 350 750 1,500 3,000 5,000I/O counts
300mm, single RDL
300mm, double RDL
Conventional
Fan-Out WLP
Flip-Chip BGA
with substrate
Lo
w C
ost
High Density
High Density Multi-Chip Packaging : Cost Comparison
IME’s High Density
Fan-Out WLP
Cost Effective Because :
• Removing Flip-chip BGA substrate
• Minimizing No of RDL layers with Fine L/S (2um/2um)
• Integrating Multi-Chips with Wafer Level Processing
© 2014 A*STAR Institute of Microelectronics and Proprietary
High Density FOWLP Consortium Forum
Fan-Out Wafer-Level Technology: RDL size vs I/O count
Total Silicon Die Area (mm2)
I/O
Co
un
t
100 200
100
300
500
1000
3000
2000
300
RDL- 1st Fan-Out WLP
(L/S: 2 µm/2 µm)
Mold-1st Fan-Out WLP
(L/S: <5 µm/5 µm)
Current Fan-Out WLP
(L/S: >5 µm/5 µm)
© 2014 A*STAR Institute of Microelectronics and Proprietary
High Density FOWLP Consortium Forum
IME approach on High Density FOWLP“RDL-first” FOWLP“Mold-first” FOWLP
Target App Smart phone
Package 15 mm x 15 mm, I/O ~1000, Thickness ~450 µm
Benefits Existing infrastructure in FOWLP manufacturing
Challenges Die shift, wafer warpage, RDL L/S < 10 µm/10 µm
Target App Tablet
Package 20 mm x 20 mm, I/O ~2000, Thickness ~450 µm
Benefits Fine Pitch RDL with L/S ≤ 2 µm/2 µm
Challenges Require support wafer
Chip placement on molding tape on mold frame
Wafer level molding
Release from mold frame
RDL and bumping processing
Singulation
IC IC
IC IC
IC IC
Formation of RDL and UBM on Carrier
Die-to-Wafer Bonding
Wafer Molding
Support Carrier Removal & bumping
Singulation
IC IC
Sacrificial layer
Carrier
© 2014 A*STAR Institute of Microelectronics and Proprietary
High Density FOWLP Consortium Forum
Test Vehicle Specs from Industry Feedback
TV 1 TV 2
Mold-1st FOWLP* RDL-1st FOWLP*
Specifications• RDL L/S ≤ 5 µm/5 µm, 2 layers • Package size : 15 mm x 15 mm• Package I/O count: ~1000• No of chips: 2 chips /package• Reliability : MSL3, TCOB 1000
Specifications• RDL L/S ≤ 2 µm/2 µm, minimum 2 layers• Package size : 20 mm x 20 mm• Package I/O count: ~2000• No of chips: 3 chips / package • Reliability: MSL3, TCOB 1000
Note: * Spec to be finalized after member’s inputs
© 2014 A*STAR Institute of Microelectronics and Proprietary
High Density FOWLP Consortium Forum
Reliability of large FOWLP
•Creep fatigue analysis and life prediction modeling •Solder joint design enhancement
Challenges & Proposed Solution
Routability & SI/PI design
•Routing of 2K-3K I/O and reduce RDL layer•SI/PI and PDN design for multi-layer fine RDL •Develop EDA methodology for PDK
Wafer warpage andmoldable UF void
• Mold Compound material, process and design optimization• Overmold and die thickness• Molding void prediction by mold simulation and design optimization
Challenge
Proposed solution
Chip-to-Mold non-planarity
•Mold tape and Pick & place process •Spin-coated dielectric / laminated dielectric films for surface planarity
Topography with multi-layer fine RDL
•PR and photo-dielectric with higher planarity and smaller via opening•Cu density uniformity and incorporating Cu dummy structures•Sacrificial and carrier removal process
Die shift causing misalignment
•Improved lithography techniques to compensate die shift • Establish Design guidelines based on tool, material & process tolerance to minimize die shift
© 2014 A*STAR Institute of Microelectronics and Proprietary
High Density FOWLP Consortium Forum
Development of high density fan-out wafer level package with fine pitch multi-layer redistribution layer technology, including the following:
Project objective
Design of Test Vehicle
•High I/O FOWLP with fine RDL routability
•Electrical design, characterization, and PDK development
• Integrated high-Q inductor and antenna
Mold-first and RDL-first fabrication process flow
•Fabrication process development
• Lithography process development
•Photo-resist and dielectric materials
Modeling and Characterization
• Die shift and moldable underfill void analysis and prediction
• Structural, material and process analysis for wafer warpage
• Board level reliability for large FOWLP
Test vehicle assembly build, Reliability & FA
•Test vehicle fabrication and assembly build •Package and board level reliability testing •Failure mechanism analysis
1/4 global model & submodel
Coupling
Coupling
Sym.
Sym.
Sym.
Coupling
S1 S2
PBGA solder joint distribution1/8 global model & submodel
Sym.
2D model (2D)
Sym.
Sym.
Sym.
Sym.
© 2014 A*STAR Institute of Microelectronics and Proprietary
High Density FOWLP Consortium Forum
IME High Density FOWLP Consortium
Member’s Inputs
Product Roadmap
Technology, Design requirements
Performance, reliability
requirements
Advanced materials, process and
equipments
Member benefits
1. End-to-End solution for High Density, Low cost FOWLP for mobile/tablet applications
2. Fan-Out Technology platform for supply chain members to drive and co-develop next
generation FOWLP
3. Extensive foreground data availability based on Member’s requirements.
IME
300 mm Fab, FOWLP engineering line
Mold 1st & RDL 1st fabrication process flow
Design guidelines for reliable FOWLP
EDA Flow and Fan-Out PDK
Demonstration test vehicle
Reliability, FA
High Density FOWLP
Consortium
Fine RDL development
Design, modeling
and materials
OSAT
Equipment
Materials Foundry
IDM/
Fabless
IME
© 2014 A*STAR Institute of Microelectronics and Proprietary
High Density FOWLP Consortium Forum
Test vehicle design
• SI/PI prediction with multi-layer RDL
• Parasitic RLC extraction for fine RDL
• EDA flow with PDK and Routing Analysis
• Integrated high-Q inductor and antenna
Modeling and design solutions
• Design guideline to minimize die
Shift < 3 µm, wafer warpage < 0.5 mm
• Solution for void free moldable underfill
for RDL 1st process
• Stress analysis of multi-layer fine RDL
• Design guidelines for reliable FOWLP
of < 20 mm x 20 mm for TCOB
Assembly, reliability and FA
• Assembly flow for 20 mm x 20 mm FOWLP
• Package level reliability to meet MSL3
• Board level reliability to meet TCOB of
1000 cycles and JEDEC drop test
• Failure mechanism of board level reliability
Fabrication: Mold 1st & RDL 1st
• Manufacturable process flow for
fine L/S(2 µm/2 µm) RDL
• Litho process for die shift and topography
compensation
• Identify material for carrier and adhesive
of RDL first process
1/4 global model & submodel
Coupling
Coupling
Sym.
Sym.
Sym.
Coupling
S1 S2
PBGA solder joint distribution1/8 global model & submodel
Sym.
2D model (2D)
Sym.
Sym.
Sym.
Sym.
Deliverables Low cost multi chip, high I/O FOWLP package solution with 2 µm/2 µm RDL line/spacing
Innovative wafer level fabrication for mold 1st and RDL 1st approach
© 2014 A*STAR Institute of Microelectronics and Proprietary