integrated class-d audio amplifier with 95% efficiency and 105 db snr

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IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 11, NOVEMBER 2014 1

Integrated Class-D Audio Amplifier With95% Efficiency and 105 dB SNR

Xicheng Jiang, Fellow, IEEE, Jungwoo Song, Darwin Cheung, Minsheng Wang, and Sasi Kumar Arunachalam

Abstract—An integrated ultralow EMI Class-D amplifier witha feed-forward ADC and feedback filters is demonstrated in a180 nm CMOS and wire-bonded package. Circuit and architec-ture techniques, which enable 1.75 W into an 8 Ohm speaker,105 dB SNR, 95% efficiency, 0.004% THD+N, and 15.4 dB marginbeyond the EN55022 Class-B standard, are discussed.

Index Terms—ADC, audio, class-D amplifier, efficiency, EMI,feed-forward, feedback, filter, SNR, THD+N.

I. INTRODUCTION

T HE goal of audio amplifiers is to reproduce input audiosignals at the speakers efficiently and at low distortion

with desired volume and power levels. A straightforward analogimplementation of an audio amplifier uses a transistor in linearmode to create an output voltage that is a scaled copy of the inputvoltage. Class-AB [1], [2] is a commonly used linear amplifiertopology. The Class-AB amplifier (Fig. 1) uses some DC biascurrent to prevent cross-over distortion and enable good soundquality. However, even a well-designed class-AB amplifier [1],[2] has significant power dissipation because the output voltageswings are generally far less than the supply rail. The largedrain-source voltage drops thus produce significantinstantaneous power dissipation. On the other hand, a Class-Damplifier (Fig. 2), or so called switching amplifier, transformsthe input signal to output pulses using a pulse-width modulation(PWM) technique. When the output switches conduct current,the voltage drop across the switch is at minimum (idealzero). When reaches the maximum value, it does not con-duct any current. The out-of-phase current versus voltage in theoutput switches leads to very low (ideal zero) power consump-tion of the output power devices. Consequently, good efficiency(90% and beyond) can be achieved. Compared to linear ampli-fier topology, such as a Class-AB amplifier, Class-D topologyhas better efficiency and larger output power, while the lin-earity and supply rejection are worse. Class-D audio amplifiers[3]–[19] are increasingly needed in portable devices driven by alithium battery (2.5–5.5 V) for their high efficiency and outputpower capability. Various circuit techniques [3]–[10] have beendeveloped to overcome class-D amplifier limitations such as

Manuscript received January 18, 2014; revised April 28, 2014 and June 02,2014; accepted June 27, 2014. This paper was approved by Guest Editor ZhihuaWang.The authors are with Broadcom Corporation, Irvine, CA 92617 USA (e-mail:

[email protected]).Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/JSSC.2014.2335713

Fig. 1. Class-AB amplifier.

Fig. 2. Class-D amplifier.

pop/click noise, electromagnetic interference, short-circuit con-ditions, and overlimit voice coil temperature or membrane ex-cursion. The advanced circuit techniques enable wide adoptionof Class-D technology in mobile devices.Class-D amplifiers for mobile applications require two crit-

ical features: filter-free operation and direct battery hookup.Class-D amplifiers with the above features have recently beenreported [14]–[16]. Their reported THD+N is around 60 dBto 70 dB and the maximum output power, specified at 1%THD N, is less than the potential power achievable withbattery voltage .Class-D amplifiers with much higher performance have also

been reported [11]–[13]. However, they need a bulky audio bandLC filter to reduce quiescent power consumption. This is due tothe fact that they use a traditional binary PWM which producespulses of 50% duty cycles at a zero input signal. If an LC filteris not used, large quiescent power is consumed. However, sizeand cost of the LC filter limits its usefulness for mobile appli-cations. A ternary PWM can produce narrow-width pulses withzero input signals and provide small quiescent power withoutan LC filter. This modulation is used in [14]–[16] to ensurefilter-free operation.Direct battery hookup is also desired since any power con-

version device between the battery and the class-D degrades thepower efficiency. However, the battery voltage disturbances in-duced by the operation of other circuits, especially RF trans-mitter(s), can seriously degrade the audio performance [16].

0018-9200 © 2014 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.


2 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 49, NO. 11, NOVEMBER 2014

Smartphones and tablets with rich multimedia requirespeaker drivers to provide high-output power, high efficiency,high dynamic range, and low distortion. Previously reportedClass-D amplifiers [5], [18] can achieve 1.5 W peak outputpower into an 8 speaker with a stand-alone wafer-levelchip-scale package [5], [18] and a supply boost [5]. However,the low-cost integrated solutions with wire-bond packages [14],[15] provide only 1 W or less peak output power. Althoughprevious works [14], [15] are implemented in fine geometryCMOS process, high-voltage tolerance transistors such aspower FETs [15], or cascoded power FETs [14] have beenused to support direct battery operation of the power stage.Moreover, class-D amplifier THD+N performance is limitedby the intermodulation distortion and the disturbance causedby the rail-to-rail switching output. The intermodulation can beeliminated by sampling and holding the signal at the output ofthe loop filter [18]. The input common-mode disturbance canbe reduced by a differential-signaling front-end with a complexswitching scheme [17]. Nevertheless, the loop filter suffersfrom processing the high-frequency feedback signal.This paper presents an improved Class-D architecture with

a feed-forward ADC and feedback filters. The integratedamplifier with a wire-bond package achieves 95% efficiency,105 dB dynamic range, 0.004% THD+N, and 1.75 W into an8 speaker without a supply boost.The paper is organized as follows. The architecture consider-

ations are described in Section II. The feedback loop design ispresented in Section III. The feed-forward path is explained inSection IV, and the implementation details of the feedback pathare given in Section V. The measurement results are presentedin Section VI. Finally, the conclusions are given in Section VII.

II. CLASS-D ARCHITECTURE CONSIDERATION

The architecture of a typical Class-D amplifier for cellularapplications is shown in Fig. 3. The feedback loop helps reducedistortion and noise. It also helps improve the power-supply re-jection (PSR). High PSR at 217 Hz is critical in a GSM system.The conventional Class-D amplifier architecture has severallimitations. Conventional architecture directly feedbacks theClass-D output to the input of the loop filter. This causes largecommon-mode variations and large disturbances at the inputof the loop filter. As a result, the conventional Class-D ampli-fier has limited THD N performance. In addition, the loopfilter outputs in conventional Class-D amplifiers [5], [7]–[18]include signals and other non-idealities such as the supplynoise. Consequently, the loop filter can easily saturate beforethe Class-D output reaches the maximum achievable level. Theloop filter output includes large signal swing when the inputsignal is large. This not only increases the current consumptionof the amplifier to support the large output swing, but alsolimits the error correction range before the loop is saturated.For the loop to sufficiently suppress the battery disturbancein the mobile system, the signal level (namely the outputpower), has to be limited to keep the distortion low. Typicallythe output stage of the Class-D amplifier directly interfaceswith an external speaker. The large switching current throughthe speaker coil coupling with the parasitic inductance from

Fig. 3. Conventional Class-D architecture.

the wire-bond package tends to induce large overshoots andundershoots at the amplifier output. To make the device operatereliably, conventional designs reduce the output signal swingsby an amount equivalent to the overshoot or undershoot. Theparasitic resistance from the bonding wires further limits theoutput signal swing. As a result, existing Class-D amplifierswith a wire-bond package have very limited output powercapabilities.The proposed architecture, as shown in Fig. 4, resolves all of

the aforementioned issues. The proposed architecture includesa feed-forward ADC path, feedback filters, and edge rate con-trol in the driver stage. The feed-forward path is designed toprocess the signal using the loop filter to integrate only the dif-ference between the input and the feedback signals. The loopfilter, therefore, mainly responds to errors injected into the loop.The new architecture significantly extends the loop filter opera-tion range to support a much larger signal level and, therefore,a larger output power capability. To avoid PSRR performancedegradation due to the feed-forward architecture, the loop filter,feedback, and feed-forward paths are powered by an internalLDO. The internally compensated LDO consumes 50 uA of qui-escent current and less than 1% of the Class-D amplifier area.Instead of using simple resistor feedback, the proposed architec-ture includes filters in the feedback path to reduce the high-fre-quency intermodulation distortion associated with direct feed-back and also eliminate the loop filter input common-mode dis-turbance from the Class-D output. The overshoots and under-shoots are suppressed by controlling the slew rate of the outputtransition edge in this design. The operation and implementationof the edge rate control are the same as our previous publication[4]. The output-switching edge rate is controlled by adjustingthe transition time of the predriver output. The predrivers inFig. 4(a) were realized by digital gates with additional sourceresistance. The slew rate of the predriver output is determinedby the source resistance and the gate capacitance of the powertransistor. In addition, the switching edge rate control reduceselectromagnetic interference (EMI) and enables the system tomeet the EN55022 Class-B standard without any external com-ponents.To intuitively understand the new class-D architecture, a sim-

plified diagram is shown in Fig. 4(b), where FF stands for feed-forward path; LF stands for loop filter; FB stands for feedbackpath; stands for driver; represents input signal; repre-sents output signal; represents the output signal of the loopfilter, and represents supply noise. Assuming the gain for thefeed-forward path, the gain for the feedback path and the gain


JIANG et al.: INTEGRATED CLASS-D AUDIO AMPLIFIER WITH 95% EFFICIENCY AND 105 dB SNR 3

Fig. 4. (a) Proposed Class-D architecture. (b) Simplified diagram.

for the driver stage all equal to 1, it is easy to find the followingexpressions.

The signal gain from the input to the output of the class-Damplifier is:

(1)

The loop filter output swing relative to the input signal isgiven by

(2)

The supply noise to the class-D output transfer functionassuming zero input is given by

(3)

where is the loop filter gain.

III. FEEDBACK LOOP DESIGN

The loop filter is a critical block in the analog feedbackClass-D implementation in achieving low noise, low distortion,and high power supply ripple rejection. Conventional topolo-gies use a second-order loop for its simplicity. Due to the finitegain from the second-order loop, this conventional loop has alimited capability to reject power supply noise and is sensitiveto battery disturbances. To overcome this issue, a fourth-orderloop was designed for high-loop gain to sufficiently attenuatethe supply ripples. Compared to conventional architectures, thishigh-gain loop is less sensitive to battery disturbances becausethe increased loop gain directly translates to higher powersupply noise rejection. In addition, the high-gain loop relaxesthe feed-forward path noise and distortion requirements. Any

Fig. 5. Loop filter structure.

imperfection at the output of the feed-forward path will beattenuated by the higher loop gain when referred back to theinput of the amplifier.The loop filter, as shown in Fig. 5, consists of a chain of four

integrators with a resonant loop. Notch is introduced to maxi-mize the supply ripple rejection in the audio band. A cascadeof four integrators provides more than 100 dB of gain at theGSM TDMA frequency of 217 Hz. Even though PWM itselfis a non-linear operation, the PWM generation preserves theinput signal characteristic as long as the input signal is band-width-limited [24]. It implies that the PWM generation can betreated as linear operation if the signal frequency under consid-eration is much lower compared to the modulation frequency

. Furthermore, the loop filter rejects high frequency com-ponents caused by the nonlinear operation of PWM. As a re-sult, the input signal to the PWM block is bandwidth-limited.This enables linear analysis of closed loop to be feasible upto certain input frequency. It is verified that the linear analysisof the class-D loop is valid up to the unit gain frequency ofthe loop through extensive transient simulations. Conse-quently, all transfer functions and the loop stability can be eval-uated by using the linear analysis methodology. Closed-looptransfer functions from the input of each integrator to the outputof the Class-D amplifier are plotted in Fig. 6. In the audio bandfrom 20 Hz to 22 kHz, the noise contribution from the inte-grator in later stages is attenuated by the integrators in precedingstages. Consequently, the design requirements of the integratorsin later stages are significantly relaxed compared to the 1st inte-grator. Increasing the order of the loop filter does not necessarilyincrease the system cost in terms of die area and power con-sumption. However, maintaining the stability of the main loopwhen feedback is applied around the fourth-order loop filter ischallenging, especially considering that resistors and capacitorsmay vary % in the commercial CMOS process. An on-chipRC calibration circuit adjusts the loop filter passive components(resistors and capacitors) to maintain a relatively constant loopresponse, even under the condition of process, voltage, and tem-perature variations. The on-chip RC calibration circuit tunes theRC time constant to “match” with an internal timing reference.After the calibration, the RC time constants are within 2.5% ofthe design targets. Fig. 7 plots the loop gain and phase responsesas a function of frequency in the cases of typical RC value and



Fig. 6. Closed loop transfer function from the input of each integrator to theoutput of the Class-D amplifier.

Fig. 7. (a) Bode diagram with RC variation. (b) Interpretation of the bode plotusing Nyquist diagram.

% of RC variations. The region in Fig. 7(a) where the phaseis less than and the gain is larger than 0 dB does not affectthe loop stability. This can be easily understood if the bode dia-grams are converted into a Nyquist plot, as shown in Fig. 7(b).The gain and the phase in the bode plot of Fig. 7(a) correspondto in Fig. 7(b). Based on Nyquist’s theory, the stabilityis determined by whether the critical point is encircledas the frequency increases. If the critical point is not en-circled, then the loop is stable. As can be seen in Fig. 7(a) and(b), the phase movement around where the gain is above

Fig. 8. Class-D response without supply disturbance.

Fig. 9. Supply rejection: with and without the loop filter.

0 dB does not encircle the critical point . Good gain mar-gins and phase margins are maintained under all conditions.To validate the effectiveness of supply ripple rejection from

this high-order loop filter, the following simulations are per-formed. First, the simulation is done with a 2 dBFS, 11 kHzinput signal. The output spectrum is very clean under the condi-tion of no supply disturbance as shown in Fig. 8. The high-fre-quency input signal is chosen to speed up the simulation time.Next, the simulation is done with a 20 dBFS, 2 kHz rippleon the supply while the loop filter is disabled. As shown in theoutput spectrum (light-line curve in Fig. 9) that correspondsto open-loop architecture, the supply ripple is mixed with thesignal. By enabling the loop filter, the supply ripple is sup-pressed by more than 70 dB under this specific simulation con-dition as shown in Fig. 9 (solid-line curve). Fig. 10 plots theclosed-loop power supply ripple rejection as a function of fre-quency in the cases of typical RC value and % of RC vari-ations. The PSRR profile using ideal amplifiers is also com-pared against the response when actual amplifiers with limitedbandwidth are used. Even though the actual amplifiers make thenotch less pronounced, good PSRR is maintained over the en-tire audio band under all conditions. It is worth mentioning thatsome circuit imperfections, such as device mismatch, are notconsidered in these simulations.The PWM converter, which is defined as the conversion from

the comparator outputs to the final PWM output as shown in



Fig. 10. Closed-loop supply ripple rejection with RC variation.

Fig. 4, is a nonlinear system. In this nonlinear system, there canbe certain oscillation modes at subharmonic frequencies, suchas , , etc., where is the modulation frequency.The dominant oscillation mode is at a frequency. Thisoscillation can also be characterized as a limited cycle oscilla-tion. The describing function (DF) [21] is very widely used as astandard mathematical tool for analyzing limit cycles. The de-scribing function method is based on quasi-linearization, whichis the approximation of the non-linear system under investiga-tion by a linear transfer function that depends on the amplitudeand frequency of the input waveform. This dependence on am-plitude and frequency generates a family of linear systems thatare combined in an attempt to capture the salient features of non-linear system behavior. Fig. 11 plots the PWM converter gainas a function of a normalized input signal at half modulationfrequency using the describing function method wherethe maximum input amplitude corresponds to 1. The maximumPWM gain at half modulation frequency corresponds to 6 dB.To effectively suppress the limit cycle oscillation, the loop filtergain at half modulation frequency should be designed to be lessthan 6 dB such that the overall loop DF gain at half modula-tion frequency is less than 0 dB. Fig. 12 depicts Class-D ampli-fier output pulses with zero input and different loop filter gainsat half modulation frequency Fig. 12(a) corresponds to the loopfilter gain at 5 dB (not enough to compensate PWM convertergain at 6 dB), Fig. 12(b) corresponds to the loop filter gain at7 dB (more than enough to compensate PWM converter gain

at 6 dB), and Fig. 12(c) is the zoomed-in version of Fig. 12(a)while Fig. 12(d) is the zoomed-in version of Fig. 12(b). Asshown in Fig. 12(c), when limit cycle oscillation is not sup-pressed, the Class-D amplifier outputs relatively wide pulseseven with a zero input signal. As a result, the quiescent cur-rent consumption goes up when the amplifier is connected toan 8 speaker. In addition, a wide output pulse induced by thelimit cycle oscillation and the available signal, limits the outputpower capability. To achieve minimum PWM pulse width at azero input signal and minimum quiescent power consumption,the loop filter bandwidth is optimized such that the combinedloop filter gain and PWM converter gain at is less than0 dB.

Fig. 11. Class-D amplifier gain at half modulation frequency based on describefunction analysis.

Fig. 12. Class-D amplifier output pulse with zero input and different loop gainat half modulation frequency.

IV. FEED-FORWARD PATH

A feed-forward path is used in this design so that the loopfilter mainly deals with the error signal, instead of the inputwith large voltage swing. The feed-forward technique in thispaper is similar to the input feed-forward path used in ADC[23] to improve linearity. The feed-forward path in this design,as shown in Fig. 13, consists of an ADC, a digital PWM, andanalog ramp generators. The performance requirements for theADC and analog ramp circuits are relaxed because the feedbackloop also attenuates any error introduced in the feed-forwardpath. The counter-based ADC, as shown in Fig. 14, requiresonly one comparator. The matching DAC elements can easilymeet the 6–7 bit accuracy requirement. With a 13 MHz clockrate, the ADC has a relatively low latency compared to theClass-D modulation frequency at 722 kHz. The digital PWMgenerator [13] converts the ADC output to a digital PWM signaland realizes a 4th-order noise transfer function. The 4th-orderstructure is chosen to obtain sufficient spectral error shapingwhile also maintaining stability over a wide input range. Thedigital PWM utilizes a digital triangle-wave oscillator to reducethe output pulse rate to only one pulse per cycle of the low-rateoscillator. The operation and detailed implementation of the



Fig. 13. Feed-forward path.

Fig. 14. Counter-based feed-forward ADC.

Fig. 15. Feed-forward ramp generator.

digital PWM generator were described in our previous publi-cation [13]. The ramp generators transform the digital PWMpulses into analog ramp signals by charging and dischargingcapacitors with constant current sources (Fig. 15). A ramp-upsignal starts ramping up when the digital PWM

changes from 0 to 1 or from 1 to 0. A ramp-downsignal starts ramping down when the changesfrom 1 to 0 or from 0 to 1. The feed-forward path consumes100 A current.The Class-D amplifier with a detailed feed-forward path is

shown in Fig. 16. The feed-forward ramp signals ( and) are compared against the loop filter output to generate

the final Class-D PWM output. The comparators in Fig. 16 de-tect zero crossings between the loop filter output signal andthe ramp-up/down signals. The time difference between zero-crossings is converted to a ternary PWM signal by using thetiming information of the rising edges of the two comparatoroutputs. This defines the pulse width and pulse polarity. Thefinal PWM pulse is finely adjusted from the feed-forward digitalPWM pulse to correct errors from the battery disturbance andother sources. The Class-D operation signal flowchart is shownin Fig. 17 where is the analog input signal, is thedigital PWM output, is the analog ramp-up signal,is the analog ramp-down signal, is the output of the loopfilter, is the output of the up comparator,is the output of the down comparator, and finally, is theClass-D amplifier differential output.The operational principle of this Class-D amplifier is signif-

icantly different from other conventional Class-D amplifiers.Conventional closed-loop Class-D amplifiers [5], [7]–[18] usefixed-period triangular waves as the reference. The feed-for-ward path in this Class-D amplifier provides ramp signals withperiod modulated by the input signal. The new modulation

Fig. 16. Proposed Class-D architecture with detailed feed-forward path.

Fig. 17. Class-D operation signal flow chart.

scheme is enabled by the feed-forward path. Fig. 18 illustratesthe effect of the modulated ramp period. In a closed loopclass-D amplifier with fixed-period triangular waves, the loopfilter output swing is proportional to the input signal level asshown at the top of Fig. 18. In this case, the swing becomeslarger as the signal level increases. Since the loop filter outputswing reflects the signal amplitude plus non-idealities such asthe supply noise, the loop filter can readily saturate even beforethe class-D output reaches the maximum level achievable withthe supply. If that happens, the loop loses its capability tosuppress the non-idealities resulting in a significant drop inperformance. Instead, as shown at the bottom of Fig. 18, bymodulating the ramp-up/down periods with the input signal, theloop filter output swing can be made small, and the loop filteroperation range is extended to a level that can support a largersignal. The loop filter output voltage swing with this modu-lated reference is about 10x smaller compared to conventionalclass-D amplifiers with fixed-period triangular waves.

V. FEEDBACK PATH

Direct feedback of the class-D output to the input of the loopfilter can induce distortion in the loop filter operation. Sincethe class-D output switches between ground and whiledriving a speaker coil, its slew rate is extremely large. Also, itis accompanied by an overshoot and undershoot induced by thespeaker coil current and the inductance of the bonding wiresof the supply and load rails. Furthermore, the output commonmode (CM) varies widely as the output switches between supply



Fig. 18. Loop filter output swings in case of two different schemes of PWMgeneration, period-fixed triangular waves (top), and period-modulated ramp-up/down (bottom).

Fig. 19. Feedback filter path.

rails. This is unlike a class-D amplifier with binary modulationwhere the CM of the output is constant.To reduce the high-frequency intermodulation distortion

associated with direct feedback and to eliminate the loop filterinput common-mode disturbance from the Class-D output thathas a rail-to-rail common-mode variation, a feedback path,which consists of filters and an active amplifier with outputcommon-mode regulation, is proposed and shown in Fig. 19.The Class-D output is filtered by the linear RC filter formed byand . The RC filter bandwidth is set high enough to en-

sure loop stability. Shunt resistors are added to attenuatethe filtered Class-D signal to a level that can be easily accom-modated by the active feedback amplifier (A). The attenuationfactor from the shunt resistor is compensated by adjustingthe value of the resistor as shown in Fig. 16. The noisecontribution of the feedback resistor and the feedback amplifieraffects the overall performance. The feedback resistor and thefeedback amplifier in this design are optimized to reduce thenoise contribution.The active amplifier with output common-mode regulation

is shown in Fig. 20. With common-mode feedback to both thefirst and second stages of the amplifier, a large common-modeloop bandwidth is achieved. The resistor (R) and capacitor (C)around the active amplifier provide additional filtering. The am-plifier differential output with a constant common mode is thenfed to the input of the loop filter. The feedback amplifier con-sumes 750 A current.

Fig. 20. Active amplifier in the feedback filter path.

Fig. 21. Die microphotograph.

VI. MEASUREMENT RESULTS

Fabricated in a commercial 180 nm CMOS process, the diemicrophotograph is shown in Fig. 21. The bottom left sectionis the feedback path while the feed-forward path is shown atthe top right. The predriver with source resistance is at themiddle right. The Class-D amplifier together with the inte-grated PMU is packaged in a low-cost wire-bonded package.The Class-D amplifier is measured with an 8 resistor inseries with a 68 H inductor while other power managementunits are operating. The 68 H inductor and the 8 resistorare used to emulate the 8 loudspeaker. The design supportsbattery voltages from 2.5 V to 5.5 V. Fig. 22 shows a plot ofthe A-weighted THD N with a 1 kHz input signal using AudioPrecision equipment. The signal-to-noise ratio (SNR) is calcu-lated by adding 60 dB to the absolute value of the THD N at60 dBFS. The Class-D amplifier achieves over 105 dB SNR

when driving an 8 loudspeaker. The minimum THD N is0.004%. At 40 dB THD N, the output power correspondsto 1.75 W. Fig. 23 shows the measured THD N vs. outputpower with different battery voltages. 750 mW output power isachieved with a 3.6 V typical battery voltage. Fig. 24 depictsthe measured output spectrum with a 1 kHz input signal and1.5 W output power. Better than 0.01% THD is achieved. Theclass-D efficiency versus output power is shown in Fig. 25. Apeak efficiency of 95% is achieved at a 1.75 W power output.The radiated electromagnetic emission was measured with acommercial smartphone that uses this Class-D amplifier. The



Fig. 22. Measured THD N vs. output power.

Fig. 23. Measured THD N vs. output power at different battery voltages.

Fig. 24. Measured output spectrum.

system meets the EN55022 Class-B standard up to 1 GHz witha 15.4 dB margin, as shown in Fig. 26, without any externalcomponents. The power supply rejection is measured with a400 m disturbance on the battery supply and a 60 dBFS

Fig. 25. Measured Class-D amplifier efficiency.

Fig. 26. Measured radiated emission.

Fig. 27. Measured PSRR.

input signal. Fig. 27 shows the measured spectrum of both thesupply and the Class-D amplifier output. A PSRR of 96.8 dB isachieved at the GSM TDMA frequency of 217 Hz.Table I summarizes the measured performance of this work

and compares it to recent state-of-the-art work. This amplifierachieves the highest margin to meet the EN55022 Class-B stan-dard. It also achieves the highest efficiency of 95% and thehighest dynamic range at 105 dB. It is the only reported Class-Damplifier with a wire- bonded package that achieves beyond1.5 W without a supply boost.



TABLE ICLASS-D AMPLIFIER PERFORMANCE SUMMARY AND COMPARISON

VII. CONCLUSION

This paper has presented an audio Class-D amplifier with105 dB dynamic range, 95% peak efficiency, and 1.75 Woutput power into an 8 loudspeaker in 0.18 m CMOS. Thefeed-forward ADC path and the switching edge rate control helpto achieve the higest reported output power in a wire-bondedpackage. The feedback filter path reduces the high-frequencyintermodulation distortion and eliminates the loop filter inputcommon-mode disturbance. As a result, 0.004% minimumTHD N is achieved. A fourth-order loop filter with high loopgain enables 96 dB PSRR at 217 Hz. Furthermore, the Class-Damplifier meets the EN55022 Class-B radiation standard witha 15.4 dB margin.

ACKNOWLEDGMENT

The authors would like to thank their colleagues ToddBrooks, Jianlong Chen, Felix Cheung, Iuri Mehr, John Platenak,and Nir Matalon for their valuable contributions.

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Xicheng Jiang (M’98–SM’11–F’14) received theB.S. degree from the University of Science andTechnology of China, Hefei, China, and the M.S.and Ph.D. degrees in electrical engineering from theUniversity of California, Los Angeles, CA, USA.Since 1997, he has been with Analog and RF

microelectronics group at Broadcom, Irvine, CA,USA, where he is a Director of Engineering anda Broadcom Distinguished Engineer. His researchinterest includes data converters, high-speed serialtransceivers, cellular baseband, Hi-Fi audio drivers,

microphone interfaces and precision sensor interfaces.Dr. Jiang is a Fellow of IEEE. He currently serves on the Technical Program

Committee of ISSCC and CICC. He is a named inventor on more than 30 issuedand pendingU.S. patents and has authored or coauthored over 30 conference andjournal papers. He was a co-recipient of the CICC 2009 Best Paper Award andthe CICC 2013 Best Poster Paper Award.

Jungwoo Song received the B.S. and M.S. degreesin physics from Seoul National University, Seoul,Korea, in 1987 and 1989, respectively.In 1989, he joined Hyundai Electronics (now

Hynix Semiconductor), Korea. He started his careerin the fields of process development and processintegration, and then migrated into analog and mixedcircuit design of communication area. In 2000, hejoined the Analog/RF and Mixed Signal group ofBroadcom Corporation, Irvine, CA, USA, and hasbeen leading analog circuit development in audio

area since then. He holds several patents and has authored or coauthoredseveral papers.Mr. Song was a co-recipient of Best Paper Awards at the 2009 IEEE Custom

Integrated Circuit Conference (CICC).

Darwin Cheung received the B.Eng. andM.Phil. de-grees in electronic engineering fromHongKongUni-versity of Science and Technology, Hong Kong, in1994 and 1996, respectively.He has been working for Broadcom Corporation,

Irvine, CA, USA, as an analog design engineer since1995. He worked on set-top box analog front-ends,ADCs, and DACs. He is currently engaged in audioCODEC design.

Minsheng Wang received the B.S. and M.S. de-grees in electrical engineering from NorthwesternPolytechnical University, China, in 1988 and 1991,respectively. He received the first Ph.D. degree fromXidian University, China, in 1994, and the secondPh.D. degree from Texas A&M University, CollegeStation, TX, USA, in 1998.He was with Texas Instruments from 1998 to 2001

and with Broadcom Corporation from 2001 to 2013working on the low-power mixed-signal product de-sign and development. He is now with Qualcomm.

He has been awarded 16 patents, and has authored or coauthored six conferenceand journal papers.Dr. Wang was a co-recipient of the 2009 IEEE Custom Integrated Circuit

Conference (CICC) Best Paper Award.

Sasi Kumar Arunachalam received the Bachelor’sdegree in electrical engineering from the Birla Insti-tute of Technology and Science, Pilani, India, in 2002and the M.S. degree from Oregon State University,Corvallis, OR, USA, in 2005.He has been with Broadcom Corporation, Irvine,

CA, USA, since 2005, working on high-precisionmixed-signal circuit design including delta-sigmadata converters and audio drivers.

integrated class-d audio amplifier with 95% efficiency and 105 db snr

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