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On Designof Narrow-Band Low-Noise Amplifierswith Inductive Source DegenerationI. M. FilanovskyUniversity of AlbertaEdmonton, Alberta, Canada, T6G 2E1E-mail: [email protected]

Abstract-The stage of inductively degenerated common-source amplifer is widely used in narrow-band amplifiers. Thenoise performance of this stage can be optimized for the noisemodel that is valid in the range of RF frequencies, and thatincludes drain and gate correlated noise sources. A ten-stepdesign procedure is given. It results in the circuit with optimalnoise figure. An example of design is given. The feasibilityoffurther optimization connected with fmed power dissipation isdiscussed.I . INTRODUCTION

In design of RF front-end amplifiers one has to choosebetween the optimal noise and optimal power matching. Thedesigner solves this dilemma building an amplifier withmatched input impedance, and using methods that do notdegrade the noise performance. The common-source stagewith inductive source degeneration (Fig. 1, a) is a popularapproach for narrow-band amplifiers. Indeed, using asimplified model forMOStransistor (Fig. 1, b) one finds thatthe input impedance of this circuit, Z ( j o ) s

This input impedance is that of a series RLC-network, with aresistive termwhich is directly proportional to the inductance value. It is

ReZin ( j w )=( g d s11C g s =U T L , (2)

I - 1 +1-Fig. 1. Amplifier with source inductive degenerationa) inductive degeneration, b) small-signal equivalent circuit,c) stage circuit,d) transistor noise model used at RF

important to emphasize that L, does not bring with it thethermal noise of an ordinary resistor because a pureinductance is noiseless. This fact is exploited to provide aspecified input impedance without degrading the noiseperformance of the amplifier.To avoid using large active devices this circuit is tuned atthe resonant frequency, 0 0 , by another inductance, L ,,connected in series with the gate (Fig. 1, c) so that theamplifier resonant frequency is

0 0 = 1 / J m . (3)The circuit noise performance is then evaluated using anoise model and calculating the noise figure at the resonantfrequency. A simplified noise model [l] of a short-channelMOS transistor at RF includes correlated current noise

sources (Fig. 1, d). Here id2 is the drain noise currentcharacterized by the spectral density function (SDF)

i d2 /(Af) =4kTEd0, (4)where y=2-3 is a constant, and gdo is the conductance ofthe device open channel. Then, igc2 and iP2 arecorrelated and uncorrelated with id components of the gate

- -noise current. The SDF of igc2 is given by- ( 5 )igc 4 A f )=4kT6gg I c 2 9

i , 2 / ( ~f )4kr6gg (1- Ic l2 .-

nd the SDF of i P 2 is given by-(6)

Here 64 - 6 is a constant, c=jO.395 is the correlationcoefficient -

(7)and

The calculation of the noise figure for the circuitof Fig. 1,c using the model of Fig. 1, d can be found in [1,2]. Whatwas overlooked in [1,2] is a possibility to create a step-by-step design process based on matching and noise figure

64Roc.43rd I E E Midwest Symp.onCircuitsandSystems,LansingM , Aug8-11,ZooO~- ~ R ~~- M ~~- ~ X X ) / B ~O . I X IIEEE2000

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optimization.Thisdeficiency is eliminated here. A ten-stepdesign process is proposed. A numerical example is given.A technical feasibility of further optimization proposed in[1,2] is discussed.

11.NOISEIGUREALCULATIONWe have to consider the contributionsof the input sourcenoise and noise current sources of the transistor in the outputnoise current (Fig.2).Tocalculate the first component, iol , Fig.2, a) one has to

find the transconductance

and find its value at W O .When L , >>L , , henl-woL(Lg +L,)C, =-LgCgsWoL =o, (10)

and the term -L SCgswo2inthe numerator of (9) can beneglected. Inthiscase

- gm- jwoc, (R , [email protected] SDF of noise voltage for the resistanceR, is equal to-

vs / (Af )=4kTRsMultiplying this SDF by the square modulus of thetransconductuctance(11) one obtains that

I IC)

Fig. 2. Calculationof noise contributions

To find the contribution from the uncorrelated partof thegate one has to consider the circuitof Fig. 2, b. It is easy toshow that the relationship between the output componenti02 and i in this circuit s

At the resonant frequency one obtains from (14) thati02 =i , 1 [T , + &+ L , )WO 4 5 )[l+(WTL s /R s)l j O OFrom( 15) one finds that-Here QL =(L g +Ls >(WO1Rs =14w0RsCgs) .Substituting(6) and (8) into(16) one finds

Finally, to find the contributions from the drain noisecurrent id ,and correlated with it the component of the gatecurrent igc one has to consider the circuit of Fig.2, c. Using(1-1) one finds that in this circuit

1 [9 , + (Lis+L ,100(18)I+(WTL s /R, >I jW0'03 =igc 1+ d [l+(WTLS 4 1 1

at WO .This relationship can be rewritten as

Using the definition(7)one obtainsfrom( 19) that

Substituting n(20)the SDFs of the components one finds

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Combining the contributions made by the transistor in theoutput noise factor one finds that the SDF of this contributionis

where rNow one can find the circuit noise factor

111.NOISE ACTOR PTIMIZATIONThe expression(24) can be found in [1,2].The derivationwas done here because the model given in Fig. 1, d is notwidely used. A possible optimization of noise figure is alsomentioned in[1,2].-One can create a step-by-step design process based onmatching and resulting in noise figure optimization. Indeed,substituting71 fkom(23) and

into(24)one can rewrite the noise factor as. 32 1 ~I & +2 p +- ( l + p ) +p Q ~ , (26)QLwhere p =(& ) (5y) s a numerical value that depends onthe transistor characteristicsonly.One can see that (26) can be optimized with respect toQL . The optimal value, Q L ~ ~ ~ ,s found by simpledifferentiation. t isequal to

Q~opt=Jm (27)and with this value of QL the noise factor becomes

I V. DESIGN ROCEDURENow we can propose the following design procedure forthe stage with source inductive degeneration.

1.Choose a smallest, technologically well controlled andrepeatable value of L, (usually 1-3nH)that can be realizedas an integrated nductororas a bond wire inductor.2. Find the transistor uni ty gain fkequencyOT =g , I C from the condition W T L ,=R, .3. Knowing transistor parametersa, 6,and y , ind theparameter p =(h2)(5y) and calculate the optimal valueQ~opr=&GG .find the value of gate inductor L , =[ ( Q L R ~ )001- L , .4. Knowing the stage resonant operating frequency 0 0 ,

5 . Find the device gate -capacitancec,, =1/[wo2(L g+L , ) ] .6. Assume that C =(2 3)CoxWZ as usual [3].Choose

the minimal possible value of device lengthL and find thevalue of the device width W =-- .3 c g s2 CO&7. Find the device transconductanceg , =OTC~,.

8. Find the device effective voltagevef l =v, - vT = gmL .Use this result in bias circuitP?ZCOXWcalculation.9. Find the required device drain currentI D =(1/2)gmVe# Use thi s result in bias circuitcalculation. '

10.FindThe first round of design procedure is over. Somesecondary effects (gate resistance, resistance of inductors)increase the noise figure. These factors may be taken intoconsideration after the firststage of design.

V. DESIGN XAMPLEAs an example we consider design of a GPS narrow-band matched amplifier operating at the resonant

fiequency 00 =10" sec-'. Let R,=50 Q. The amplifiershould be realized in CMOS 0.5 pm (drawn) technology.This technology has pnCox=156 pA/V2, andCox=3.8*10-3pF/pm2. The device with the gate drawnlength L , =0.5 pm has the effective engthL=0.4pm.Wetake for this technology [l] that y =2, 64,a=0.85, and1 c I=0.395.

As in[ 1 westartthe design choosing L , =1.4nH. Thenwe find that one has to use the device with

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50 =3.57*10" sec-l. Using theLs 1.4*10-9W* =s=4*0 852

5*2transistor parameters one finds that p=-0.289.Then one can find that the optimal value of QL,~isQLopt = =2.11 . Now we can determinethat L, +L , =2.11*50=1.056*10-8H=10.6nH. Then1o'Othe gate inductor will have the value ofL , =10.6-1.4 =9.2nH. This inductor is quite large forthe integrated realization, and can be realized, for example,as external component. -

lo2*10.6*10-9Now one can find that C ==0.943pF. Then, with L=0.4pm the device width will beW= (3/2)*0'943 =930 pm. The required devicetransconductance is g , =0.943*10-12 *3.57*10"=3.37*10-2 A!V=33665 p m . This transconductancevalue is obtained when the effective voltage

3.8*10-3 *0.4

33665*0'4=0.094 V. s applied to the device. TheveH= 156*930device should be biased by the currentFinally one can find that he noise factor will beTo complete the design requires the addition of bias and

output circuitry. For narrow-band applications, it isadvantageous to tune out the output capacitance to increasethe gain. So, a typical single-ended amplifier mght appearas shown in Fig. 3.This design assumes that the outputFig.3. The narrow-band low-noise amplifier with source

I, =0.5*33.7*0.092=1.58mA.F op=1+5.24 00 /0~)=1+1.47=2.47 3.9dB).

ICL

Fig.3. The narrow-band low-noise amplifierwith source inductive degeneration

inductive degeneration circuit is tuned at the sameftequency W O , and the output coil has the Q-factor about4to realize the gain of 10.

Transistor M I s biased using the current mirror scheme,and the resistor R B ~ , s chosen large enough that itsequivalent noise current can be ignored. The blockingcapacitor CB shifts the resonance frequency by4% only.

W. DISCUSSIONND CONCLUSIONSThe amplifier similar to the proposed one was realized

[2], and the obtained noise figure was 3.5 dB (the authorshoped to obtain2.1dB).The proposed design process requires that y, 6,and aare known. Yet, these values are known for long-channeldevices only (y =2/3, 6=4/3, a=1). If one redesignthe amplifier using these values one will find thatQLopr=1.87.This value is not much different from2.11thatwas found for y =2, 64, nd a=0.85. If 6=2y (as it isconsidered now), then the exact value of a has a weakinfluence on the design process, and one can use the long-channel model.What the designer should expect is an increased value ofnoise figure. If one uses the long-channel device parametersone can find thatand the noise figure would be 1.68 (2.3dB). Hence, one canexpect the increaseof noise figure by 1.6dBat least.

The obtained optimal value of Q L ~ ~ ~oincides with thebest figure for a given transconductance design [2] obtainedat the step7of the proposed design procedure.Finally, in [2] is discussed the optimization of the designprocess for a fixed power dissipated by the stage. It is foundthat in this caseThis optimization would improve the resulting noise figure(1.45 or 1.6 dB) by 0.7 dB only. The design for thisoptimization could be hardly justifiable because theimprovement on the level of 3.9 dB is not very muchdifferent from usual measurement errors.

F op =1+2.44(00 U T ) , (29)

Fopt=l+l.62(w0/ aT) . (30)

REFERENCES[l ] T. H. Lee, The Design of CMOS Radio-F requency

Integrated Circuits, Cambridge University Press,Cambridge,1998.[2] D. K . Shaeffer,T. H. Lee, A 1.5-V, 1.5-GHz CMOSLow Noise Amplifier, IEEE J . Solid-state Circuits, vol.[3] D. Johns, K . Martin,Analog Integrated Circuit Design,32,NO5,pp. 745-759, 1997.J . Wiley, New York, 1997.

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