1

Logic Design Lab 4Verilog—introduction

Logic Design Lab 4Logic Design Lab 4VerilogVerilog——introduction introduction

Instructor: Instructor: KuanKuan Jen Lin (Jen Lin (林寬仁林寬仁))EE--Mail: Mail: kjlin@mails.fju.edu.twkjlin@mails.fju.edu.twWeb: Web: http://http://vlsi.ee.fju.edu.tw/teacher/kjlin/kjlin.htmvlsi.ee.fju.edu.tw/teacher/kjlin/kjlin.htmRoom: SF 727BRoom: SF 727B

2

FPGA Design Flow

Design entry

Synthesis

Functional simulation

Fitting

Programming & configuration

Timing simulation

畫電路圖

HDL programming

3

Use CAD Tools to design and verify logic circuits

• Create design– Draw schematic– Use HDL (e.g. Verilog), like C programming

• Verify design: give test patterns, and check if outputs meet specification.– Simulation

• Graphical input/ouput• Embedded test_modules in HDL programs

– Emulation (Prototyping): • FPGA/CPLD• Discrete components

4

Schematic Capture

5

Simulation

6

What is an HDL?• A Hardware Description Language (HDL) is a high

level programming language with special language constructs used to model the function of hardware logic circuits.

• The special language constructs provide you the ability to:– Describe the connectivity (structure) of a

circuit– Describe the functionality (bhavior) of a

circuit– Describe a circuit at various levels of

abstraction– Describe the timing information and timing

constraints of a circuit– Express concurrency

7

Why Use an HDL?• Model the design in higher level of abstraction

– Reduce the design capturing effort– Easy for handling complex design– Separate from implementation, increase the protability– Potential for design re-use

• Mix behavioral/structural descriptioms in adesign– Model datapath and regular portion of circuit

structurally– Model control and regular portion of circuit behaviorally

• Model the design and testbench with the same language

8

First Example

9

Structural Description(An SR Latch)

name of the module

Port declarationType declaration

primitive gates with names and

interconnections

module nandLatch(q, qBar,set, reset);ouput q, qbar;input set, reset;nand g1 (q, qBar, set);nand g2 (qBar, q, reset);endmodule

A module is defined

g1

g2

q

qBar

set

Reset

10

Primitives

11

Overview of Verilog Module• A verilog module includes the following parts:

module module_name (port list) ;

Declarations of port-type, wires, reg…

Instantiation of primitives

assign-dataflow statements

endmodule

always & initialBehavioral blocks

Task & function (testbench)

12

Structural Description(A combinational circuit)

module binaryToESeg(input A, B, C, D,output eSeg);wire p1, p2, p3, p4;

nand g1 (p1, C, ~D);nand g2 (p2, A, B);nand g3 (p3, ~B, ~D);nand g4 (p4, A, C);nand g5 (eSeg, p1, p2, p3, p4);endmodule

g2B

A

g1~D

C

g3~D

~B

g4C

A

g5

p1

p2

p3

p4

eSeg

eCB

D

AeSeg

Gate output is an implicit wires

13

Verilog Operator (PP. 152)module binaryToESeg (A, B, C, D, eSeg);input A, B, C, D;output eSeg;wire p1, p2, p3, p4;

assign p1= ~(c & ~D);assign p2= ~(A & B);assign p3=~(~B & ~D);assign p4=~(A & C);assign eSeg= ~(p1 & p2 & p3 & p4)

// assign eSeg = (c & ~D) | (A & B) | (~B & ~D) | (A & C);endmodule

g2B

A

g1~D

C

g3~D

~B

g4C

A

g5

p1

p2

p3

p4

eSeg

14

Operators (1/2)• Logic operators : return a value.

&&, ||, !assign a = b && c;

• Bitwise logic operators : return result in bus form.&, |, ~, assign a[2:0] = b[2:0] & c[2:0];

• Equality operator: ==, !=• Reduction operator: a = &b;• Relational operator: >=, > ,

15

Operators (2/2)• Are all Verilog operators synthesizable?• Conditional operators

e.g. assign a = c ? x : y ;• Shift operators

e.g. assign a = b

Module Hierarchymodule fulladder(S, Co, A, B, Ci);

input A, B, Ci;output S, Co;assign Co = { (A ^ B) & Ci } | (A & B);assign S = A ^ B ^ Ci;

endmoduleA

B

Ci

S

Co

A B

SCiCo

module adder(S, C4, A, B, C0);input [3:0] A, B;input C0;output [3:0] S;output C4;wire C1, C2, C3; //Intermediate carries//Instantiate the fulladderfulladder FA0(S[0], C1, A[0], B[0], C0);fulladder FA1(S[1], C2, A[1], B[1], C1);fulladder FA2(S[2], C3, A[2], B[2], C2);fulladder FA3(S[3], C4, A[3], B[3], C3);

endmodule

A B

SCiCo FA3

A B

SCiCo FA2

A B

SCiCo FA1

A B

SCiCo FA0

A[3]

S[3] S[2] S[1] S[0]

C4

A[2] A[1] A[0]B[3] B[2] B[1] B[0]

C2 C1 C0C3

18

Create a Testbench For a Module

testbench

Test Generator

And

Monitor

Design Under

Test

(DUT)

19

module_testBench

module testBench;wire w1, w2, w3, w4, w5;binaryToESeg d (w1, w2, w3, w4, w5);test_bToESeg t (w1, w2, w3, w4, w5);endmodule

20

Test modulemodule test_bToESeg(output reg A, B, C, D, input eSeg);initial // two slashes introduce a single line commentbegin$monitor ( $time,,"A = %b B = %b C = %b D = %b, eSeg = %b",A, B, C, D, eSeg);//waveform for simulating the nand lip lop#10 A = 0; B = 0; C = 0; D = 0;#10 D = 1;#10 C = 1; D = 0;#10 $finish;endendmodule

0 A = x B = x C = x D = x, eSeg = x10 A = 0 B = 0 C = 0 D = 0, eSeg = x12 A = 0 B = 0 C = 0 D = 0, eSeg = 120 A = 0 B = 0 C = 0 D = 1, eSeg = 122 A = 0 B = 0 C = 0 D = 1, eSeg = 030 A = 0 B = 0 C = 1 D = 0, eSeg = 032 A = 0 B = 0 C = 1 D = 0, eSeg = 1

21

Interconnection of Design and Test Modules

testbench

Test Generator

And

Monitor

Design Under

Test

(DUT)

eSegAB

C

D

eSegAB

C

D

22

A behavioral Model of BinaryToESeg

modulebinaryToESeg_Behavioral

(input A, B, C, D,output reg eSeg);always @(A, B, C, D) begin

eSeg =1;if (~A & D)

eSeg=0;if (~A & B & ~C)

eSeg = 0;if (~B & ~C & D)

eSeg = 0;end

endmodule

1111

1100

0100

1101

AB

CD

eSeg

C-like

Procedural statements

Sensitive list

23

always (sensitive list) begin…C-like procedural statements….endRules for combinational circuits•All inputs to your combinational function must be listed in the sensitive list.•Combinational output(s) must be assigned to every control path.

24

Behavioral modelling• A behavioral model of a module is an

abstraction of how the module works.• always defines a process

– Suspend execution of this “always process”until a change occurs one of variable in the sensitive list.

• Procedural statement – C programming-like– Conversely, structural descriptions are

concurrent statements.• Within an “always” process, the left side

of “=“ must be declared as register.– Register does not always need a physical

storage.

25

Verilog 程式結構module name( port list)

Declarartion of signals 宣告Interconnections of low-level modules or primitivesassign p= a&b……assign ……always@(...) begin…….endalways@(...) begin …………..end

endmodule

Concurrent running

26

Why use behavioral descrption?

• Use behavioral model on early design stage.– HDLs are designed originally for

simulation• Write testbench• Partial behavioral descriptions can be

synthesized to circuits.

27

Standard Model of a Moore FSM

00/0 01/1

11/0

0

10

01

1reset

Comb.

Circuit

State

Registers

OutputInputComb.

Circuit

Z

D Q

clk

D Q

clk

~Q1

Q0

Q0

x

x

Q1

clk

reset

//D flip-flopmodule D_FF(D, Q, CLK, RST);input D, CLK, RST;output Q;reg Q;always @(posedge CLK or

negedge RST)if(~RST)

Q = 1'b0;else

Q = D;endmodule

module state_machine(x, reset, clk, z);

input x, Reset, clk;output z;wire D1, D0;assign z =~Q1 & Q0;assign D1 =Q0 & x;assign D0= x | Q1;

D_FF A1(D1, Q1, clk, reset);D_FF A0(D0, Q0, clk, reset);endmodule

Z

D Q

clk

D Q

clk

~Q1

Q0

Q0

x

x

Q1

clk

reset

29

behavioral model of FSMmodule fsm(output reg z,

input x, clk, resetreg [1:0] curStste, nextStste;always @(x, curState) begin

z=~curState[1] & curState[0];nextState=0;if (curState ==0)

if (x) nextState=1;if (curState ==1)

if (x) nextState=3;if (curState ==3)

if (x) nextState=3;else nextState =1;

endend

00/0 01/1

11/0

0

10

01

1reset

30

D_FFalways @(posedge clk, negedge reset) begin

if (~reset)curState

31

Model hardware concurrency

• Verilog is a parallel HDL.• Model HW concurrency:

– Continuous assignmentassign v = x + y + z;

– Procedural blockalways @(posedge c or d) begin

v = c +d + e;w = m –n;

end– Note: Any continuous assignment can be rewritten

as a procedural block.

32

Module Hierarchy

board

Display driver

m16 m555

A counter example

clkcount

33

Top modulemodule boardWithConcatenation;

wire clock, eSeg, w3, w2, w1, w0;m16 counter ({w3, w2, w1, w0}, clock);m555 clockGen (clock);binaryToESeg disp (eSeg, w3, w2, w1, w0);

initial$monitor ($time,,,"count=%d, eSeg=%d", {w3, w2,

w1, w0}, eSeg);endmodule

instantiate

Bus concatenation

34

m16 (Counter)module m16(output reg [3:0] ctr = 1, input clock);

always @(posedge clock)ctr

35

A clock generator (simulation)

module m555(output reg clock);

initial#5 clock = 1;always#50 clock = ~ clock;

endmodule

36

Rules for Synthesizable Combinational Circuits

• All inputs to your combinational function must be listed in the sensitive list.

• Combinational output(s) must be assigned to every control path.

37

module synAutoSensitivity (input a, b, c,output reg f);always @( a, b ,c)

if (a == 1)f = b;

elsef = c;

endmodule

always @( *)

38

module synAutoSensitivity (input a, b, c,output reg f);always @(*) begin

f = c;if (a == 1)

f = b;endendmodule

39

Inferred Latches

amodulesynAutoSensitivity(

input a, b, c,output reg f);always @(*)

if (a == 1)f = b & c ;

// else f = ?endmodule

40

Use case Statement

• Using Case Statement– Using full_case (attributes)、 explicitly

specify (truth table form) or a defaultitem to fully specify.

– Specify Don’t Care situations for input and output.

41

Use case Statement (cont.)• Truth table method

– List each input combination

– Assign to output(s) in each case item.

module fred(output reg f,input a, b, c);

always @ (a or b or c)case ({a, b, c})

3’b000: f = 1’b0;3’b001: f = 1’b1;3’b010: f = 1’b1;3’b011: f = 1’b1;3’b100: f = 1’b1;3’b101: f = 1’b0;3’b110: f = 1’b0;3’b111: f = 1’b1;

endcaseendmodule

42

Use case Statement (cont.)

module fred(output reg f,input a, b, c);

always @(a or b or c)case({a,b,c})

3’b000: f = 1’b0;3’b101: f = 1’b0;3’b110: f = 1’b0;default: f = 1’b1;

endcaseendmodule

43

Specify don’t care

• Rules– You can’t say

“if (a == 1’bx)…”this has meaning in simulation, but not in synthesis.

– However, an unknown x on the right-hand side will be interpreted as a don’t care. The inverse function was implemented;

x’s taken as ones.

00 01 11 10

0

1

ab

c1 1

11 1

0x

x

44

Specify don’t care (cont.)

module caseExample((output reg f,input a, b, c);always @ (a or b or c)

case ({a, b, c})3’b001: f = 1’b1;3’b010: f = 1’b1;3’b011: f = 1’b1;3’b100: f = 1’b1;3’b110: f = 1’b0;3’b111: f = 1’b1;default: f = 1’bx;

endcaseendmodule

45

Rules for Synthesizable Sequential Circuits

• The sensitive list includes only the edges of the clock, reset and preset conditions.

• Inside the always block, the reset and preset conditions are specified first.– if (~reset),,,,

• Any register assigned to in the sequential always block will be implemented using flip-flops.

• The “

46

Latch inferences

module synLatchReset( Q, g, d, reset);

input g, d, reset;output Q;reg Q;always @(*)

if (~reset)Q = 0;

else if (g)Q = d;// else Q = ?

endmodule

• To infer a latch, two situations must exist in the always statement:

– At least one control path must exist that does not assign to an output.

– The sensitivity list must not contain any edge-sensitive specifications. (level-sensitive )

47

Flip Flop inferencesmodule synDFF( q, clock, d);input clock, d;output q;reg q;always @(posedge clock,

negedge reset, posedgeset) beginif (~reset)

q

48

Conclusion

Required – from the presence of an edge specifier, the tool infers a flip flop. All registers in the always block are clocked by the specified edge.

No affect.Inferred flip flop

Not allowed.There must exist at least one control path where an output is not assign to. From this “omission,”the tool infers a latch.

Interred latch

Not allowed. The whole input set must be in the sensitivity list.Theconstruct @(*) assure this.

An output must be assigned to in all control path

Combinational

Edge Specifiers in Sensitivity ListOutput Assign ToType of Logic