low cost multi-site soc/sip ic testing solution · 2008-07-16 · 2-3. data move and dsp time...

Multi-site SOC/SIP IC testing Tutorial by Jin-Soo Ko 제 9 회테스트학술대회2008. 6. 25.

Jin-Soo.Ko, Teradyne Inc.

[email protected]

Low Cost Multi-Site SOC/SiP IC Testing Solution

제 9 회테스트학술대회2008. 6. 25. Multi-site SOC/SIP IC testing Tutorial by Jin-Soo Ko

Agenda

Overview1. Overview and History

Architecture2. High Throughput Single-site Test Architecture3. High Throughput Multi-site Test Architecture4. Highest Throughput Multi-site Test Architecture5. Multi-site Testing Throughput and Efficiency Calculation

Interface6. Design the Multi-site DIB7. AC Extension for Multi-site Testing

Conclusion


1. Overview and History

1-1. Multi-site testing overview

1-2. Multi-site History and Future


1-1. Multi-site Testing Overview

• Needs high density instruments• Large application space• High ATE option accuracy• Easy Development S/W tool• High parallelism >95-99%• Parallel test development

1999 – 4 site2002 – 8 site2006 – 16 site2008 – 32 site plan

Multi-site testing provides high tester system utilization and reduces the cost of testing


Quad site Codec test – 1999

•Needs to handle a lot of AC in and out pins - Relay Mux module design

•Needs to test DC test items faster and more accurately

- Use AC digitizers for testing DC items- Developed DC capture by digitizer

synchronize with HSD pattern –Pset and u-code control concept forDC testing

•Result38% single site test time reduction 89% parallelism on Catalyst

I_ DAC 8bitI_ DAC 8bitQ_DAC 8bitQ_DAC 8bit

DUT 1DUT 1

IF_ADC 12bitIF_ADC 12bit

AFC_DAC 11bitAFC_DAC 11bitAGC_DAC 10bitAGC_DAC 10bit

Audio CodecAudio Codec

RX_ DAC 13bitRX_ DAC 13bitTX_ADC 13bitTX_ADC 13bit

SerialSerialInterfaceInterface

ControllerController

IF IF InterfaceInterfaceAudio Audio InterfaceInterface

1-2-1. Multi-site Testing History : 4 Site

6제 9 회테스트학술대회2008. 6. 25. Multi-site SOC/SIP IC testing Tutorial by Jin-Soo Ko

Octal site CD-P test - 2003

• Use IG-XL and relay mux circuit• 96% parallelism• 10x more throughput on FLEX

than the single site testing on Catalyst

1-2-2. Multi-site Testing History: 8 Site


16 site MP3 or Smart Phone Processor test - 2007

Single vs. 16 sites test time difference is only 1.74 sParallel Efficiency is 98.38%25% less COT

* comment: Normalized to 10 as 16 site testing time

98.38%10.00*9.33*8.99*8.88*8.04*Parallel efficiencyx16x8x4x2x1

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 2 3 4 5 6 7

8 9 10 11 12 13 14 15

1-2-3. Multi-site Testing History: 16 Site


>16 site SoC/SiP Device test solution• Number of AC sources and digitizers, HSD, and DC sources?

• Size of DIB application space?• >16 site SoC/SiP device handler?

1-2-4. Multi-site Testing History: >16 Site


2. High Throughput Single-site Test Architecture

2-1. Reduced Instrument Setup Times• Instrument setup microcode in pattern (Pset)• Simultaneous “broadcast” instrument setups

2-2. Device Response Wait Time Reduction• Instrument settling times characterized and controlled in Pattern Tool• Deferred limits minimize CPU interruption

2-3. Data Move and DSP Time Reduction• Instrument initiated move• Back ground move• Back ground data processing by dedicated processors


Program Instruments with PSets

Select Source Signal

Trigger measurements at precise times

Reprogram Instruments with PSets

Select different Source Signal

Trigger measurements at precise times

Automatic data move and processing

-3dB

Automatic data move and processing

…and so on…

Very fast and precise setups – high repeatability – short test times !Very fast and precise setups – high repeatability – short test times !

2-1. Reduce Instrument Setup Time


2-2. Device Response Wait Time Reduction

- Combo Test Scope shot


Conventional Single Conventional Single Threaded EnvironmentThreaded Environment

Setup Inst.Setup Inst.CaptureCapture

MoveMove

TestTestDSPDSP

Multithreaded Environment Auto Pipelining by ATE system

Capture

TestDSPMove

Capture

Capture

2-3. Data Move and DSP Time Reduction

TestDSPMove

TestDSPMove

Background Move & DSP Structure


3. High Throughput Multi-site Test Architecture

3-1. High Density Instruments• Multiple instruments can support multiple sites

3-2. Multi-site Test Architecture• 3-2a. System level of OS and H/W integration

- Efficient multiple H/W option control to get high parallelism of the test

• 3-2b. Easy programming and debugging tools- Makes user easy to develop complex multi-site testing program


3-1. High Density Instruments

Add more channel numbers and speed by improving new ASIC and FPGA design technique and reduce the per channel price

AC Channel: 4 >8 >16 >32 >64Low Speed Digital: 128DC: 32 > 64 > 128High Speed Digital: 64 > 128 > 256 > 364


SITE

1

SITE

1

SITE

3

SITE

4

SITE

2

SITE

3

SITE

4

SITE

2

SITE

5

SITE

7

SITE

8

SITE

6

SITE

5

SITE

7

SITE

8

SITE

6

SITE

1

(4 sec/2.92 sec) x 8 site = 10.96 times

Single site Test time 4 sec to Octal site Test time 2.93 sec

TestDSPMove

TestDSPMove

Setup Inst.Setup Inst.CaptureCapture

3-2a. Multi-Site Test Architecture – multi-parallel background move and DSP


3-2b. Multi-Site Test Architecture -Multi-site Test Development is SAME as Single-site

Test Procedures are the same regardless of number of sites.Procedure variables are available on site-by-site basis.Debug tools are site aware.Test results are available on a site-by-site basis for easy comparison.


4. Highest Throughput Multi-site Test Architecture

4-1. Efficient Test Resources Assignment

4-2. Upgradeable CPU/DSP and OS

4-3. Concurrent testing-Distributed clock architecture provide ultimate flexibility -Logical Pattern Generators


• Assign independent resources for each site to increase parallelism • HSD• Low speed signal capture option• DSP• PPMU

• Possible shared resources to reduce cost of test• Time Measurement Unit (TMU)• Signal sources• High speed signal capture option • DSP

• Possible shared resources to increase site to site correlation• Reference DC source• Signal source and capture

4-1a. Efficient Test Resources Assignment

A20

A20 1. Do we have extended UDB option on FLEX? If not, we can't assume that sharing relay control bits will reduce the cost of test. 2. Instead of Timer, we may use "Time Measurement Unit (TMU)" instead3. For bullet 3, we may use: "Possible shared resources to increase test throughput". Alawadhi, 2003-12-01


site0

AC Cap #1

AC Src #1

DC30

PPMU HSD

site1

HSD

site7

HSD

refsrc

Relay control data bit

TMU

AC Cap #2 AC Cap #8DC30 DC30

PPMU PPMU

AC Src #2

AC Src #8

4-1b. Multi-site Test Resources Assignment Examplefor Octal site testing

A21

A21 It is recommended that we use 8 sites visualization instead of combining sites 2-6 in one box OR we can remove the box for sites 2-6 and put dots in between "....." Alawadhi, 2003-12-01


Total Test Time vs. Sample Size

0100020003000400050006000700080009000

very small small mediumSample size

Test

Tim

e (m

s)

ST 6.4 D6, CPU24MT 6.4 D6, CPU24ST 6.4 D6, U60MT 6.4 D6, U60

CPU-24 to U-60S-S 39% TTRM-M 34% TTRS-M 48% TTR

CPU-24 to U-60 Comparisons4-2a. CPU and DSP update for Multi-site Test


ADSL QUAD AFE

Single site Using

CPU-24

100%

50%

0%

Relative Test Time

Single siteusingU-60

50% less test time vs. CPU24100% More throughput per test

cell!

4-2b. New CPU & DSP Option for more Throughput

Same program, 1 Same program, 1 day change overday change over


Digital Vectors

DSP

/µC

Cor

e

AC Capture

AC Setup

Digital Vectors

Rea

dC

hann

el C

ore

Data move Processing

DC Parametrics

‘old think’

‘linear flow’

‘one thing at a time’

Obsolete

44--3a. Multi Pattern Generators and Concurrent 3a. Multi Pattern Generators and Concurrent TestingTesting


44--3b. Concurrent Block Testing3b. Concurrent Block Testing

Est. Test Time Savings

DSP

/µC

Cor

e

Digital Vectors(Concurrent Portion)

Digital Vectors(Non-concurrent Portion)

AC CaptureData move Processing

AC Setup

Digital Vectors

Rea

d C

hann

el C

ore

Flex DSP and PowerPort speed datamove and DSP processing

DC Parametrics

Dual PatGen tests DSP core durinRead Channel tests. Test time savings: 50-80%


• 2 - 100ms Digital Patterns• 2 - Mixed Signal Captures

• 75 ms Setup & Capture + 30ms DSP


10 0 ms

10 0 ms

80 ms

75 ms

30ms

45 ms

Typical single site testing flow

44--3c. Concurrent test Example3c. Concurrent test Example430 m

s


• 2 - 100ms Digital Patterns• 2 - Mixed Signal Captures



430 ms

10 0 ms

10 0 ms

80 ms

75 ms

30ms

45 ms

Total Test Time is now 200 ms!

215% more Throughput

10 0 ms

10 0 ms

75 ms

45 ms

30ms 80 m

s

200 ms

4.3d. Concurrent test flow using 4.3d. Concurrent test flow using Dual Dual PatGenPatGen

•Flex DSP •Dual PatGen


5. Multi-site Testing Throughput and Efficiency Calculation

1-1. PPH (Part Per Hour) Throughput calculation and Example

1-2. OTE (Overall Tester Efficiency) Calculation and Example


Single Site T = 4.3 sec.n = 1I = 0.3 sec.U = 0.8

3600 * 1 * 0.8PPH x1 =

16 Site T = 5.59 sec. (98% parallel efficiency)n = 16I = 2.5 sec.U = 0.9 (Increased due to more sites)

4.3 + 0.3

PPH x1 = 626

3600 * 16 * 0.9PPH x16 =

5.59 + 2.5

PPH x16 = 6408

A throughput increase of 1023% !!!A throughput increase of 1023% !!!

11--1. 1. PPH Throughput calculation and Example

3600 * n * UPPH xn =

T + I


The OTE formula:

PPH multi SHP single

PPH multi = multi site PPH

PPH single = single site PPH

SHP single = System + Handler Price for single site

SHP multi = System + Handler Price for multi site

PPH single SHP multi

11--2a. OTE2a. OTE calculation and Example

OTE = *


PPH x1 = 626

PPH x16 = 6408

SHP x1 = 1.6 M + 0.05M

SHP x16 = 2.5 M + 0.1M

6408 * 1.65M626 * 2.51M

OTE = = 673%

Quad Site SOC testing increases overall tester efficiency by: 673% !!!

11--2a. OTE2a. OTE calculation for 16 site


6. Design the Multi-site Board

1-1. Multi-site DIB Design


•Set COT/PPH target•Plan System configuration•Forecast Throughput/COT

•Create test setups•Select test techniques•Allocate resources

ANALYZE DESIGN

•Layout•Manufacture•Load

DIB

•Code•Simulate

TESTS

•Check DIB •Debug Program

•Optimize•Correlate•Document

DEVELOP

DEBUG

RELEASE

Multisite Test Design Overview

1 2

3


Assign system resources to sites

1

Create DIB conceptual schematic

Verify schematic against system configuration(Simulate Pinmap)

Match ?

2

Use alternate resources

and/or techniques

Design test setups

Design & Develop Steps

Test Program Development

DIB schematic

capture

DIB Layout Design

DIB PCB Manufacturing

DIB Assembly

Test Program Simulation

Chk

Chk

3

2

DIB Checker Development

At this stage, nothing is different between the single site and multisite


• Objective:• Optimize the multisite test

hardware solution

Section III: Designing the Multisite DIB

Resource analysis

Simulate the design

Pinmap design

Generate Detailed Schematic

Layout

Design Multi-site Test Interface


Resource Analysis

• Objectives:

• Test Time Prevention

• Determine number and type of tester resources necessary

Section III: Designing the Multisite Board

Resource analysis

Simulate the design

Pinmap design


Layout


Before You Begin - System Analysis

• Must have a good understanding of each test

• Engineering Test Plan

• Working and stable single site program if single site hardware already exists.

• It is feasible to begin with a multisite DIB and program

• It is easier to first think in terms of single site requirements

• Must have configuration of target systems

• Test Socket Characteristics

• Handler/Prober information


Definitions

“Dedicated Resource” or “Parallel Resource” -any tester instrument/resource which will be utilized by only one site and by only one DUT functional block.

Digitizer

Site #0

Site #1

Dedicated or parallel resources


Definitions

“Serial Resource” or “Shared Resource” -any tester instrument/resource which will be used by more than one site; one site at time.

Timer

Site #0

Site #1

Serial or shared resource

MUX

Where possible, this MUX could be inside the

system such as using the HSD path to the TMS


Definitions

VHFAWG

Site #0

Site #1Common resource

“Common Resource” - any tester instrument/resource which will be used by more than one site simultaneously.

BUFFER


Definitions

ACDIG1

Muxed resources

“Muxed Resource” - any tester instrument/resource which will be utilized by more than one DUT functional block.

MUX

ACDIG2

MUX

DAC

DAC

Site #1

DAC

DAC

Site #0


Definitions

ACDIG

Shared muxed resource

“Shared Muxed Resource” -any tester instrument/resource which will be utilized by more than one site, and multiplexed to more than one DUT functional block on each site.

MUX

MUX

DAC

DAC

Site #1

DAC

DAC

Site #0


Resource Analysis – Relay Control bit

• How many relays can I place in parallel?• [Catalyst] The maximum SDB instantaneous current

per test head is 500mA.• Relay drivers may be added to the DIB to control more

current than the SDB.• [Catalyst] The 12V and 5V coil relays are the most

common relays used, powered with +12V and +5V user supplies. These supplies are limited to 1A each.• Calculate the total current required by all relays to

avoid blowing fuse.

Relays


Stored Data Bit Characteristics (Open Collector Output)

Typical Characteristics@ 16ma, vol < 0.4v actual data = 0.14v@ 60ma, vol < 0.7v actual data = 0.42v@ 120ma, vol < 1.4v actual data = 0.80v

Data taken from a Catalyst

SDB

SDB


Resource Analysis – Block Diagram Design

• Start with a block diagram of a single DUT with tester resources is essential (“Test Application Drawing”).• Make detailed enough to be able to determine what resources are

needed coincidentally.


Test Application DrawingAssign Resources


Resource Analysis -Details• For each pin of the DUT, make a list of measurements and test conditions:

• note the required accuracy• Review Device Specifications• Review Tester Specifications

• note the boundary conditions (max. and min. V, I, frequency etc…)• Set-up sheets should be developed for all tests

OR• copies of the Test Application Drawing can be used highlighting the

instruments/conditions for each test

• Assign instrument(s) types to each pin based upon measurement requirements. Do this for one site to start.• This may be an iterative operation


Single Site Resource Analysis

DIG

SRC

DIGCAP

DIGSRC

Add additional Digital Channels

Add power supplies

Etc.

Dedicated Resource

MuxedResource

MuxedResource


• Count total number of instruments required of each type for one site.-Some of the instruments might be common, shared or muxed

• Account for number of each instrument needed for total number of sites.

• calculate the total area of the footprints of all components on the DIB (include the contactors) • this should be no more than 50% of the application area on the

DIB (conservative). • It can get closer to 80% or more with some difficulty in routing

and signal crosstalk. • Consider also adding daughter cards in the “Z space” of the

DIB

Resource Analysis


DIB with Z-Axis Modules


Example of Some Vertical Modules

Relay Module DIB Source

DIB Digitizer Clock Fan outBandwidth compression


Building Construction DIB

Mezzanine type construction


Spider Card and Pogo Ring

Pogo Ring Adaptor

Spider Card


• Reconcile tester configuration with number of instruments required by possibly:• reducing number of sites• multiplexing instruments for non-coincident functional

blocks of the DUT• sharing resources across sites • reconsider alternate resources to make same test

conditions• possibly add DIB “instrumentation”• reconsider tester configuration additions/changes• DIB diagnostic/focused calibration circuitry

• However, try to keep the DIB as simple as possible!

Resource Analysis – Possible alternatives


• The tradeoffs between (remaining elements we can change)• lower single-site test time (includes concurrent

testing)• number of sites • Parallelism (lowering overhead)

• There is not a general priority order for these factors. Each factor can have more effect than the other, depending on the circumstances.

Resource Analysis – Final Optimization



• Objectives:- Making certain the test program and

hardware schematic design agree

Section III: Designing the Multisite DIB

Resource analysis

Simulate the design

Pinmap design


Layout



• It is suggested that a system is used for assigning reference designators that identifies the associated site.• An example is:

• Site 0 use C100 - C199, R100 - R199, …• Site 1 use C200 - C299, R200 - R299, …• Site n ……• Components common to all sites C1 - C99, R1-R99…• Number the reference designators such that components of

the various sites of the same function only differ in the 100’s (e.g., C100, C200, … represent the same part on different sites)

• Another example is:• Site 0 use C1_0, C2_0…• Site 1 use C1_1, C2_1…

• Pick a standard and follow it


Component Naming Example


Layout

• Goal:- Create board design uniform among

sites

Section III: Designing the Multisite Board

Resource analysis

Simulate the design

Pinmap design


Layout


Layout• Layout

• attempt to make each site symmetrical or mirrored of other sites.

• limit site-to-site interactions especially with common resources.

• DC source returns are shared (infamous “ground”) and considerations of this should be taken into account. Various DIB design techniques are available.

• Place the DGS connection to “ground” strategically. It should be the best representation of the “ground” or reference of all sites.


Site0

Site3

Site2

Site1

Site4

Site7

Site6

Site5

Site0

Site1

Site2

Site3

Site4

Site5

Site6

Site7

DIB Layout –Example for octal site testing

• Customer selected handler defined DUT placement


Site0

Site3

Site2

Site1

Site4

Site7

Site6

Site5

• Customer selected handler defined DUT placement



Site0

Site3

Site2

Site1

Site4

Site7

Site6

Site5

• Keepout space forced shift of center point from J13 to J15

• Required creation of specialized docking plate



• Keepout space forced shift of center point from J13 to J15

• Required creation of specialized docking plate

Site0

Site3

Site2

Site1

Site4

Site7

Site6

Site5



• Lent to symmetric division of applications space

• Easy site to site correlation

• Simplify debug

Site0

Site3

Site2

Site1

Site4

Site7

Site6

Site5

Site 0 Site 1 Site 2 Site 3




• Opt to use dedicated HSDsfor additional symmetry

• Divide one DC30 across four sites

• One dedicated BBAC scr/cap per site

• DC 75 for TMU only



BBAC

HSD200DC30

DC75BBAC

HSD200

BBACHSD200

DC30

DC75

BBAC

HSD200

HSD200

HSD200HSD200

HSD200




• Group source and capture fan-out relays

• Decoupling Caps and filter components under DUT

• AC jumpers for debug

DUTSite x30

DC30DIRECT OUT HSDs

5

Capture Relays

15

BB

AC

Cap

BB

AC

Src

Source Relays

Buffer

8HSD DIB ACCESS

9 Applications relaysPins 1, 3, 5, 8, 9, 10, 12, 28, 30

13

BBACSrc

BBACCap



DUTSite x

Capture Relays

15

BB

AC

Cap

BB

AC

Src

Source Relays

Buffer

9 Applications relays

Pins 1, 3, 5, 8, 9, 10, 12, 28, 30

13


6. AC Extension for Multi-Site Testing

AC option expend for supporting multi input ports and sites•Fan-otut and Muxing circuit design


1 AC Source and 1 AC Capture for site application• 8-32 sites application using

AC MUX relays

• 8 sites8 src/cap + 112 relays



Multi-site Testing ConstraintsD

UT 28

AC SRC 5

AC CAP 5

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX

DU

T 29

AC SRC 6

AC CAP 6

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX

DU

T 30

AC SRC 7

AC CAP 7

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX

DU

T 31

AC SRC 8

AC CAP 8

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX

DU

T 4

AC SRC 5

AC CAP 5

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX

DU

T 5

AC SRC 6

AC CAP 6

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX

DU

T 6

AC SRC 7

AC CAP 7

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX

DU

T 7

AC SRC 8

AC CAP 8

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX

DU

T 0

AC SRC 1

AC CAP 1

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX

DU

T 1

AC SRC 2

AC CAP 2

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX

DU

T 2

AC SRC 3

AC CAP 3

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX

DU

T 3

AC SRC 4

AC CAP 4

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX

1 to 4 MUX


AC Source for Low Cost Multi-site Testing

AC Source requirement• Multiple source channels > 32• Single-ended or differential source• DC or AC coupling• Impedance matching and power driving capability

• Driver output impedance - 50 or 75 ohm

• I and Q signal source• Dual Capture engines and good inter-channel skew and repeatability

• AC source Bandwidth• Needs wide bandwidth

• Source channel performance• Low Noise, Harmonics, distortions



Muxing circuit design• DC or AC coupling• Uses relay circuitry

• High frequency signal source• Long switching and settling time - a few 100us to ms • Limited relay life time - 10M to 100M times• Big size

• Uses an analog switch or an optical coupled MOS FET• Fast switching time - a few 10ns to 100ns• Frequency BW and impedance limitation

by channel capacitance - a few 1 to100pf)and on-resistance - a few ohm)

• Gain error, group delay and high distortion issues• High reliability and long life time• Small size

4

4

DU

T

AC SOURCE



Fan-out driver design• Uses OP Amps for driving multiple channels simultaneously

• Fast driver signal settling time• Different selections of the OP amp depend on the noise and distortions or frequency band • Careful design for handling AC signal Gain, phase and offset error• May need a switch to DC option for DC parametric testing• Can add signal shaping circuit - LPF, differential to single-ended buffer or attenuator• Limited compensation for the each fan-out buffer gain and offset error

Driver

DriverDriver

Driver

DU

TD

UT

DU

TD

UT

Optional Filter AC SOURCE

4

4

DU

T

AC SOURCE


Signal Capture Zoom In

SNR, THD

SFDR

Noise Floor

Dynamic Test Result using 8 fan-out circuitfor 16 bit ADC


Sine Wave input Signal Capture for Histogram

Zoom In

Linearity Test Result using 8 fan-out circuitfor 16 bit ADC


AC Capture for Low Cost Multi-site Testing

Muxing circuit design• DUT is DC coupled or has a small AC coupling cap and a short settling

time• Use relays

• Long switching and settling time - a few 100us to ms• High frequency signal capture• Limited relay life time - 10M to 100M times switching• Big size

• Uses an analog switch or an optical coupled MOS FET• Fast switching time - a few 10ns to 100ns• Frequency BW and impedance limitation

by channel capacitance - a few 1 to 100pfand on-resistance - a few ohm

• Gain error, group delay and high distortion issues• High reliability and long life time• Small size

4

4

DU

TAC CAPTURE



Advanced muxing circuit design• Uses an analog switch or a photo coupling switch with a high

impedance buffer• Minimizes the analog switch turn-on resistance error • Fast switching time• High reliability of the switching circuit

• Parallel buffers save capture signal settling time• Complex design

DU

TD

UT

DU

TD

UTBufferA-SW

A-SWA-SWA-SW

DRVBufferBufferBuffer

AC CAPTURE

4

4

DU

T

AC SOURCE


Loopback test through fan-out and capture buffer circuit for 1Khz and 1Mhz signal



AC Capture for other tests• DC tests using AC Capture

• Saves DC meters• Uses a high speed Muxing circuit• High speed large samples capturing for background DSP processing• High noise DC signal filtering and data averaging using the background DSP• Good pin to pin correlation • Improve the test time and Cp, Cpk of the test

• Frequency and timing signal tests using AC Capture• Uses direct sampling or undersampling technique• Uses DSP filtering noise technique for finding the exact threshold level• Mathematical over sampling technique for finding the exact gain of the signal• Limited by the AC option bandwidth


Other Issues of Multi-site Testing

Application issues• Differential signal skew matching

• Reduces the gain and phase error• Matches the P&N channel length

• I/Q signal phase/gain test• High AC signal source and capture skew

repetition between the channels• Single serial capture - long capture time but

easy to test the phase difference • Dual parallel capture - short capture time but

needs good channel to channel skew calibration• Relay life time

• Uses an reed relay - 10M to 300M switching time

• Uses an analog switches - long life time• Save application space

• Relay module• Fan-out module• MUX module

Delay = 130ps/inch


Conclusion

• Need very high density DC/AC/HSD ATE instrument options

• Need multi-site testing ATE architecture and OS• Back Ground move and DSP technology• ATE option setup by pattern and settling time optimization• DUT time only test• Concurrent test

• Need to design optimized DIB circuit and interface• Need AC source and capture extension and application

technique


ENDEND

low cost multi-site soc/sip ic testing solution · 2008-07-16 · 2-3. data move and dsp time...

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