module1: soc system specification, languages, model 최해욱 (icu, 공학부 )

Module1: SoC System Specification,Languages,Model

최해욱 (ICU, 공학부 )

2Copyright 2003ⓒ

Title: SoC Architecture Module1: SoC System Specification//Languages/Model

(모듈 1:System Specification/Model/Analysis) 목차

Introduction

SoC Specification

Specification Languages

SoC Model

3Copyright 2003ⓒ


SoC: System-On-Chip Definition A complex IC that integrates the major functional elements of a complete end-product into a single chip. General SoC Organization: hardware - at least one programmable processor - on-chip memory - accelerating function units implemented in hardware. - interfaces to peripheral devices - interfaces to real world (analog & O/MEMS components)

software - Real time OS - Device Drivers O/MEMS: opto/microelectronic mechanical system

4Copyright 2003ⓒ


SoC: System-On-Chip (Cont’d)

System Viewpoint A collection of all kinds of components and/or subsystems that are appropriately interconnected to perform the specified functions for end users.

An SoC design is a “product creation process” which Starts at identifying the end-user needs Ends at delivering a product with enough functional satisfaction to overcome the payment from the end-user

5Copyright 2003ⓒ


SoC Applications

Communication Digital cellular phone Networking

Computer PC/Workstation Chipsets

Consumer Game box Digital Camera

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Benefits of Using SoC

Reduced size

Reduced overall system cost

Lower power consumption

Increased performance

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Success SoCs or Platforms

■ The Philips Nexperia Digital Video Platform

■ The TI OMAP Platform

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Characteristics of Philips Nexperia Platform Approach

■ Flexibility for easy differentiation and product upgradeability

(through programmability and extensive S/W & H/W IP choice)

■ Innovation – addressing new, exciting, consumer applications

■ Future-proof via S/W upgrade ability and a roadmap of

compatible platform instances

■ The use of an architecture framework and IP blocks to flesh out

designs

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Philips Nexperia-DVP Reference Architecture

D

evic

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ol

& s

tatu

s

Nexperia-DVP System on Silicon

DEVICE IP BLOCK

MIPS CPU

DEVICE IP BLOCK

DEVICE IP BLOCK

PRXXXX

D$

I$

DEVICE IP BLOCK

TriMedia CPU

DEVICE IP BLOCK

DEVICE IP BLOCK

TM-XXXX

D$

I$

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ME

MO

RY

AC

CE

SS

DRAM

MMI

B

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Co

mp

ress

ed A

/V In

pu

t B

us

Philips Nexperia-DVP S/W Reference Architecture

Analog Inputs

Analog Front End

Analog Front End

Digital Inputs

Analog Front End

Optical Drive

Network Protocols

Hard Disk

Digital Front Ends

Co

mp

ress

ed A

/V In

pu

t B

us

Network Protocols

Players

Broadcast-MPEG2

VCD/SVCD

DVD

CD/SACD

WMT

RN

Broadcast-MPEG4

Recoders

DVD+RW Auth

PVR-SPTS

Lo-Rate SPTS

CD/DVD-MP3

U

nco

mp

ress

ed A

/V In

pu

t B

us

Transcoders

Translaters

TS-SPTS Filter

Loopback / Feedthrough

Digital Outputs

Protocol Stack

Network Protocols

Driver

HDD/Ethernet

Presentation Engine

Audio and Video Processing

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Characteristics of TI OMAP Platform Approach

■ Hierarchical Definition of Platforms

■ Critical Role of Software as well as Hardware

■ OCP (Open Core Protocol) based SoC platform

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Hierarchy of Platforms in OMAP Processors

Reference Design

Application Platform

SoC Platform

ASIC Library & Tools

Silicon Technology

Application Specific

Broadly Applicable

OMAP Products

OMAP Infrastructure

Reuse

System Platform

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TI OMAP 1510 Platform Interanal Architecture

Peripheral Bus

TI925

SDRAM Bus(16)

Peripherals: LCD Controller, Interrupt Handlers, Timers, GPIO, UARTs, McBSP

Peripheral Bus

C55X

SystemDMA

Peripherals Buses (8/16/32)

MAIL Box

DSP MMU

IMIF

Traffic Controller

EMIFF EMIFS

SRAM

LB MMUHASB MMU

Flash Bus(16)

LB(32)

HASB(32)

GPP: TI925 Core - 16KB I-Cache - Write Buffer - MMU and D-MMU - Dual TLB

DSP: C55x Core Internal Memory - 48KW SARAM - 32KW DARAM - 16KW PDRAM24KB I-CacheGraphic HW AcceleratorARM Port Interface

IPC - Mail Boxes - API - DSP MMU System DMA Traffic Controller Internal SRAM Busses Peripherals

14Copyright 2003ⓒ


TI OMAP 1510 Platform S/W Architecture

TI925 General-Purpose Processor

OS kernel& drivers

TMS320 DSP

MPEG4

OS adapter LINK driver

MCU Bridge Kernel

RESOURCE MANAGER

LINK driver Other drivers

DSP/BIOS Kernel

RM Server

MP3 AMR

MEDIA APIs

raw data streams video audio speech

XDAIS AlgorithmsEncapsulated in socket nodes

Node Data Base

15Copyright 2003ⓒ

Title: SoC Architecture Module1: SoC System Specification//Languages/Model SoC Design Flow

SystemAnalysi

s

Fun

ctio

nal

Desi

gn

Arc

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ect

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l D

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Inte

gra

tion

D

esi

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Ph

ysi

cal

Desi

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Man

ufa

ctu

rin

g L

ink

Block AuthoringVC

DeliveryChip Integration SW

Development

Su

pp

ort

in

g

Tech

nolo

gy

Executable Spec

SystemAnalysis

Virtual SystemAnalysis

DynamicVerificatio

n

Test

bench

es

Test

bench

es

Chip Spec/

IP Selection

Block Spec

Form

al IP

han

doff

Integration PlanningStatic

Verification

Implementation

Block Design

Planning

PhysicalVerificatio

n

PhysicalVerificatio

n

RTOS/Application Selection

Module Developmen

t

S/W Distribution

Authoring Guide

IP Portfoli

o

IP Portfolio

Cell libraries

IntegrationPlatform

SW Development

Links

RTOS/ Application

DynamicVerificatio

n

StaticVerificatio

n

ChipImplement

ation

16Copyright 2003ⓒ


The History of the SoC

The History of the System-on-Chip

o The Glorious Hope (1995-1999)

o The Reign of Terror: Reality & disappointment (1999-2001)

o Thermidor: Platform transformation (2000-2002)

o L’Avenir: The radiant future?

17Copyright 2003ⓒ


The Glorious Hope (1995-1999)

o Productivity Gap vs. IP based design

o 3 Seminal Events

o VSIA (1996) : Virtual Socket Interface Association, aiming to reduce the confusion & design bottlenecks involved with IP reuse at the hard, firm & soft levels through the identification of de facto standards in use for IP development, exchange & integration, & the creation of new standards.

o RMM (1998 & 1999) : Reuse Methodology Manual by Michael Keating & Pierre Bricaud, describing a series of guidelines and rules for effective creation and reuse of individual soft & hard IP blocks, system level integration and verification, etc.

o ALBA (1996~ Present): Scotland government sponsored academic-industry-government collaborative project to support, enhance and attract SoC design activities by establishing of 3 key pillars, the institute for system level integration (ISLI), a business infrastructure, the Virtual Component Exchange or VCX, a dedicated ALBA center for SoC companies.

18Copyright 2003ⓒ


The History of the SoC The Glorious Hope (1995-1999)

o Design Gap (difference between what semiconductor industry can produce (58%/Yr)and what designer can design in a certain period(21%/Yr)

International Technology RoadmapFor Semiconductors 1999 Ed.- Semiconductor Industry Association

19Copyright 2003ⓒ


The History of the SoC The Glorious Hope (1995-1999)

o Shrinking TTM (Time-To-Market)

PCSPCS

CellularCellular

PCsPCs

VCRsVCRs

Color TVColor TV Cable TVCable TV

Black & Black & White TVWhite TV

DVBDVB

DVDDVD

1 million1 millionUnitsUnits

55 1010 1515 20 years20 years

20Copyright 2003ⓒ


Solution to Design Gap => IP-based Design

Planned IP Reuse

uPCore

SRAM

FLASH

D-Cache USB

MPEG

SRAM

FIFO

Logic

uPCore

SRAM

FLASH

Logic

SW I/F IPLogic

ASIC on DSM

Complex ASICwith a few IPs

Plug & play SOC

PersonalReuse

Designer-specificreuse

practices

Retainingkey personnel

SourceReuse

Functional startingpoints for block

design

Document,testbench,

predictability

CoreReuse

Predictable,Pre-

verified,Core

function

Firm/hard IP

VirtualComponent

Reuse

SocketizedFunctions forPlug & Playintegration

Opportunistic IP Reuse

Adopted from ‘Surviving the SOC revolution’ by H. Chang et.al.

Platform-based design (PBD)Block-based design (BBD) Time-driven design (TDD)Area Driven

21Copyright 2003ⓒ


The The Reign of Terror: Reality & disappointment (1999-2001)

- Overheated IT economy starting in 1999 => collapse of the industry

o Thermidor: Platform transformation (2000-2002)

o L’Avenir: The radiant future?

The History of the SoC

22Copyright 2003ⓒ

Title: SoC Architecture Module1: SoC System Specification//Languages/ModelChallenges in SoC Epoch

Time-to-market

Process roadmap acceleration Consumerization of electronic devices

Silicon Complexity

Heterogeneous processes Billion Transistors, Deep submicron effects : crosstalk,

wire delays, electromigration, mask costs

23Copyright 2003ⓒ


Challenges in SoC Epoch (Cont’d)

Design Complexity

µCs, DSPs, HW/SW, SW protocol stacks, RTOS’s, digital/analog IPs, On-chips buses System-level architecture

Life-in-market

Performance/Energy/Cost tradeoff Scalable architecture with unified design environment

24Copyright 2003ⓒ


How to Solve the Complexity?

Use a known real entity

A pre-designed component (IP reuse) A platform (architecture reuse)

Partition

Based on functionality Hardware and software

Modeling

At different level Consistent and accurate

25Copyright 2003ⓒ


IP A predefined, designed/verified, reusable building block for System-on-Chip Software IP, Silicon IP (Soft IP, Hard IP, …) IP types Foundation IP (cell library, gate array) Standard IP (MPEG2/4, JPEG, USB, IEEE 1394, PCI…) Star IP (ARM, MIPS, Rambus, …)

Ancillary characteristics

Deliverable at certain level, software/hardware interfaces Modeling at different levels Customizable, Configurable, Parameterizable

26Copyright 2003ⓒ


Criteria in Selecting IP’s

Processor IP selection criteria

Power, performance, area, cost Flexibility Hardness (hard IP vs. soft IP) Available system software Development environment Simulation model Support library Support OS Inter-operability with other IP’s

27Copyright 2003ⓒ


Challenges for CAD Tools inIP-based SoC Design

Designing at higher levels of abstraction Verification Better and faster verification Timing & Power Better physical design tools and tool integration, for instance 3D modeling Testing Different testing schemes Capacity To support high number of gate counts

28Copyright 2003ⓒ


Challenges for CAD Tools inIP-based SoC Design (Cont’d)

IP Integration

To support use of commercial IP

Hard IP Transition

Better physical design tool

IP Standards

To facilitate use of IP from multiple sources

IP security

To support various business model

29Copyright 2003ⓒ


Platform

A fully defined bus structure and a collection of IP blocks

A design methodology to support the feature of “Plugging and Playing”

The definition of a platform is the result of a trade-off process involving reusability (programmability and configurability), cost and performance optimization.

Enhance the differentiation

30Copyright 2003ⓒ


SOC Specification

Document-based specification

Executable specification

Precise behavior description

No communication overhead

No standard yet

Stable methodology

CAD tool support required

31Copyright 2003ⓒ


Specification Languages

HDL-based specification language VHDL, Verilog Benefit from existing design flow Good for hardware description

HLL-based specification language SystemC, SpecC Typically based on C/C++ Good for software/system description

Mixed form Superlog, CoWareC

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Core Technologies

IP Development

System Architecture

SoC Verification

Embedded Software

High Speed/Low Power Design

33Copyright 2003ⓒ


System Architecture Design

Specification, Requirement, Functionalities Architecture C-level design, SystemC description and simulation Advantages Broader design space performance, power, cost tradeoff scalability, good for time-in-market Early verification module well-defined, partition, refinement necessary for time-to-market

34Copyright 2003ⓒ


Interfacing IPs

PCB (=Processor + Peripheral) shrinks to SOC

Interface between HW and HW

FIFO-based interface: I/O On-chip bus is required

On-chip bus: System Bus & Peripheral Bus

35Copyright 2003ⓒ


Candidates for Standard On-Chip Bus ARM (www.arm.com) AMBA (Advanced Microcontroller Bus Architecture) IBM (www.chips.ibm.com) CoreConnect (PLB/OPB/DCR) PALM Chip (www.palmchip.com) M Bus/Palm Bus Mentor Graphics (www.inventra.com) FISP Bus OMI (www.omimo.be) PI (peripheral Interconnect) Bus Fujitsu (www.fujitsu.com) Spcl Bus

36Copyright 2003ⓒ


SoC Verification

System-level verification

concurrent, early software hardware co-simulation testbench setup behavior modeling: instruction set simulator, bus functional model, memory behavior model, Verilog or SystemC hardware model

A dedicated testbench for every IP

Register access test to verify bus Test for checking of blocks interconnected functionality and block external interfaces Emulation

37Copyright 2003ⓒ


What is ISV?

ISV = In-System Verification When is ISV required? Design refinement down along the hierarchy

- Comparison between design levels

In-system operation: confirm correct behavior in system environment - Simulation (Chip, I/F) - All-software (Software, Software) - Emulation (HW[FPGA], HW) - Virtual chip (Software, Hardware)

38Copyright 2003ⓒ


High Speed / Low PowerDesign

Deep submicron effect High speed circuit design Low power / low voltage design Tradeoffs: Cost vs. Functionality Cost vs. Speed Power vs. Speed

39Copyright 2003ⓒ

Title: SoC Architecture Module1: SoC System Specification//Languages/Model SoC Design Flow

SystemAnalysi

s

Fun

ctio

nal

Desi

gn

Arc

hit

ect

ura

l D

esi

gn

Inte

gra

tion

D

esi

gn

Ph

ysi

cal

Desi

gn

Man

ufa

ctu

rin

g L

ink

Block AuthoringVC

DeliveryChip Integration SW

Development

Su

pp

ort

in

g

Tech

nolo

gy

Executable Spec

SystemAnalysis

Virtual SystemAnalysis

DynamicVerificatio

n

Test

bench

es

Test

bench

es

Chip Spec/

IP Selection

Block Spec

Form

al IP

han

doff

Integration PlanningStatic

Verification

Implementation

Block Design

Planning

PhysicalVerificatio

n

PhysicalVerificatio

n

RTOS/Application Selection

Module Developmen

t

S/W Distribution

Authoring Guide

IP Portfoli

o

IP Portfolio

Cell libraries

IntegrationPlatform

SW Development

Links

RTOS/ Application

DynamicVerificatio

n

StaticVerificatio

n

ChipImplement

ation

40Copyright 2003ⓒ


Why do we need models? To perform various design tasks!

Performance modeling Functional modeling and specification Design and synthesis Validation and verification Test vector generation Test coverage analysis Architecture evaluation and mapping Technology mapping Placement and routing

41Copyright 2003ⓒ


What is a Model?

Model: A model is a simplification of another entity, which can be a physical thing or another model. The model contains exactly those characteristics and properties of the modeled entity which are relevant for a given task. A model is minimal with respect to a task, if it does not contain any other characteristics than those relevant for the task.

A model relates to an entity A model is a simplification of that entity A model is related to a task and an objective A model may relate to a not yet existing entity

42Copyright 2003ⓒ


Properties of Models

Inherent property: The property is inherent in every model. E.g. the finite state space of a finite state machine model.

Static property: The property can be statically evaluated. E.g. the required memory of a finite state machine model.

Dynamic property: The property can only be dynamically evaluated. E.g. the required memory of a C program.

In design we often deal with models of not-yet-existing

entities. Thus, the model properties constrain the future

entities.

43Copyright 2003ⓒ


Heterogeneous Models are Necessary

A system consists of different parts. E.g. data flow and control flow dominated parts.

Different objectives apply for different parts. E.g. the system and its environment.

Different parts are developed by different people and tools. E.g. HW and SW.

44Copyright 2003ⓒ


(모듈 1) 참고문헌 “System Modeling – Model of Computation and their Applications,” Axel Jant

sch LECS, Royal Institute of Technology, Stockholm, Sweden Jan, 2004. “Winning the SoC Revolution-Experiences in Real Design,” Grant Martin & He

nry Chang, Cadence Labs, KAP, Jun, 2003. “Reuse Methodology Manual,” Michael Keating & Pierre Bricaud, KAP, 2003. “System Design and Methodology: Modeling and Design of Embedded Syste

ms,” Petru Eles, Linkopings Univ., Sweden “Embedded Systems Design,” Frank Vahid, Tony Givargis, John Wiley & Sons,

Inc., 2002. “Memory Issues in Embedded Systems-on-Chip,” Preeti Ranjan Panda, (Syno

psys, Inc.) Nikil Dutt,(Univ. of Cal/Irvine), Alexandru Nicolau(Univ. of Cal/Irvine), KAP 1999.

module1: soc system specification, languages, model 최해욱 (icu, 공학부 )

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