module2: system architecture for reconfigurable platform 최해욱 (icu, 공학부 )

Module2: System Architecture for Reconfigurable Platform

최해욱 (ICU, 공학부 )

2Copyright 2003ⓒ

Title: SoC Architecture Module2: System Architecture for Reconfigurable Platform

목 차 Module 1 : SoC System Specification, Language, Model, Analysis Module 2 : System Architecture for Reconfigurable Platform

- Platform-based Design and Platform Architecture - IP-based Design, Virtual-component-based Design

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( 모듈 2) 목차

System-on-Chip Architectures

SoC Design Methodology

Platform-based Design

Configurable Processor Cores

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( 모듈 2) System-on-Chip Architectures A system-on-chip architecture integrates several

heterogeneous components on a single chip

Memory

Increasingly powerful applications are possible! An efficient implementation requires many low

level details

FPGAMicrocontroller

CustomHardware

DSP

CommunicationStructure

Analog-Digital

Digital-Analog

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( 모듈 2) A typical system-on-chip

A typical system-on-chip on a single chip

DSPMicro-processorMemory

CustomLogic(ASIC)

System on a chip

I/O

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MicroProcessor MemoryI/O

Control

MemoryCtrl

VideoDecoder

BUSBRIDGE

TIMER GPIOINTRCTRL

UART

DRAM

Canonical form of an SoC A microprocessor and its memor

y subsystem On-Chip buses A memory controller for external

memory A communications controller A video decoder A timer and interrupt controller A general purpose I/O (GPIO) in

terface A UART interface

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( 모듈 2) SoC Architectures

A SoC integrates many heterogeneous components on a single chip

A SoC is a parallel architecture and thus the work on parallel computers can be used

A key challenge is to design the communication between the different entities of a SoC in order to minimize the communication overhead

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( 모듈 2) How to design future embedded systems?

Specification

o Design productivity increases with the level of

abstraction

o The task of functional verification is very difficult

at low abstraction levels

Implementation

o Efficient implementations require to exploit the

low-level features of the target architecture

Idea (Specification)

Challenge for System Design!

Product (Implementation)

Desig

n

abstract

detailed

Abstraction Gap

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( 모듈 2) Abstraction Levels

It is important to work on the right level of abstraction!

SYSTEM

REGISTER

CHIP

GATE

CIRCUIT

SILICON

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( 모듈 2) System Level

A/BComputer

IMU

Radar

C/D

IMU: Interrupt Managing Unit (?)C/D: Carrier Detection (?)

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( 모듈 2) Chip Level

uP

RAM

Pararllel Port

USART

InterruptController

16

8

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( 모듈 2) Register Level

Reg

Clk A

Inc

Reg

Clk B

Sel

MUX

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( 모듈 2) Gate Level

A

B

Sum

Cin

Cout

P

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( 모듈 2) Transistor Level

Vdd

Vin

GND

Vout

SP

DP

DN

SN

GN

GP

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( 모듈 2) Layout (Silicon) Level

VddGND

Vin

Vout

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( 모듈 2) The importance of the level of abstraction

The right level of abstraction allows to make the appropriate decisions without considering unnecessary details

Shorter design times

Though in theory everything can be fine-tuned at the silicon level, it is in practice impossible to make a large design at the silicon level

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( 모듈 2) SoC Design

The continuous progress in silicon process technology allows to increase more and more functionality on a single chip => Systems on a chip become reality

Market-driven forces: o Shorter product design schedules and life spans

o Products have to confirm to standards

o The design has to be right from the start. An implementation error means heavy loss of money or product death

o Large designs are integrated into a single chip

The SoC design process must address these driving forces

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( 모듈 2) Primary Design Methodologies

Area Driven Design (ADD) o Digital ASIC on older process technologies

Timing-Driven Design (TDD) o Digital ASIC on Deep Submicron (DSM)

Block-Based Design (BBD) o Complex ASIC with Intellectual Property Blocks

Platform-Based Design (PBD) o System-on-a-chip

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( 모듈 2) Area-Driven Design (ADD)

Earlier process technologies were not able to integrate very many transistors on a single chip

Area was very important and the effort was put on logic optimization

ADD was used mainly for new designs (no reuse)

Logic

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( 모듈 2) Timing-Driven Design (TDD)

With continuous improvements in process technologies, area became less important

Focus shifted to performance (speed and power) constraints

Time-to-market became increasingly important TDD is used for new designs on DSM processes Design teams are small

Logic

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( 모듈 2) Timing-Driven Design (TDD)

TDD became possible due to: o Interactive floor-planning tools, which gave good area and

delay estimates

o Static-timing analysis tools, which inform the designer, if

timing requirements are violated

o Compiler (synthesis) tools, which move the design to higher levels of abstraction

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( 모듈 2) Block-Based Design (BBD)

Improved process technologies allow to put additional components on a single chip (memory, microprocessor cores)

Applications are more complex and are very difficult to design and verify, if developed from scratch

Multiple design teams work on different parts of the system

Reusable virtual components (VCs) can be acquired from other companies

Complex ASICLogic

DSP Core Memory

IP-Block

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Ideally a BBD is behaviorally modeled at the system level

HW/SW trade-offs, functional HW/SW co-verification is ideally performed at that level

Design is partitioned into several components, which are then designed at a lower level (RTL for HW)

Then the entire design is verified (integration test)

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System Model

Verification

Partitioning & Mapping

HW-Model (VHDL)

SW-Model (C/C++)

HW Synthesis

SW Compilation

Executable Program

Netlist

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BBD has been possible due to:

o High-level system analysis tools

o Block floor planning

• Constraint budgets for top-level chip interconnects

• Infrastructure models for clock, test, and bus architectures

that can be used for timing abstraction

o Integrated synthesis and physical design

• The influence of physical design issues is handled in the

synthesis process (better tools)

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( 모듈 2) Platform-Based Design (PBD)

Deep Submicron Technologies allow to put many components on a single chip

The costs for test and verification are continuously increasing

Design Reuse is a prerequisite to enable PBD and shortens Time-To-Market

System-on-a-Chip

ATM

Logic

MPEG

DSP Core

RAM

ROM

Proc Core

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Like BBD, PBD starts at System Level (similar design flow) PBD is heavily based on design reuse Pre-verified blocks with standardized interfaces are used The following design concepts must be further developed: o Interface Standardization

o Virtual Component Design

Objective: Plug & Play Design Important: Standardized Test Strategies that can be used

for systems consisting of several components

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PBD becomes possible due to

o System-level and architectural design tools and methodologies

o Physical Layout Tools

• Bus planning

• Block Integration

o Virtual Components functional verification tools

There is a key problem with Virtual Components

(IP-blocks): IP-vendors do not want to reveal the internal

secrets of their designs!

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( 모듈 2) Configurable Processor Cores

Why Configurable Processor Cores? Observations o Time-to-market is critical

o Development time for software is much smaller than for hardware

o Hardware can be customized and has much better performance than software solution

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( 모듈 2) Configurable Processor Cores

Why Configurable Processor Cores? Idea

o Combine the advantages of hardware and software in form of

a customizable processor to achieve

• Clearly shorter Time-To-Market than hardware

• Clearly better performance than software

o Provide a processor platform with a basic architecture that can be

extended

• by additional optimized units (MAC, Floating-Point Unit)

• Own instructions together with own customized hardware can be

defined for the processor

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( 모듈 2) Example for a configurable processor: Xtensa(Tensilica)

The Xtensa processor core

o Targets system-on-chip applications

o Is configurable, extensible and synthesizable

o Has

• Base Instruction Set Architecture

• Configurable Functions (Parameterized)

• Optional Functions

• Designer-Defined Functions and Registers

(For Acceleration of Specific Algorithms)

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( 모듈 2) Basic Xtensa Core

32-bit architecture

Base configuration:

o 32-bit ALU

o Up to 64 general purpose registers

o 6 special purpose registers

o 80 base instructions

o Improved 16- and 24-bit RISC instruction encoding

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( 모듈 2) Optional Architecture

Execution Units

o Multipliers, 16 and 32 bits

o MAC-Unit, Floating-Point Unit

Interface Options

Memory Subsystem Options

o Memory Management Options

o Local Data and Instruction Caches

o Separate RAM, ROM Areas for Data and Instruction

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( 모듈 2) Tensilica Extension Language

The Tensilica extension language is used to describe new instructions, registers and execution units that are then automatically added to the Xtensa processor

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( 모듈 2) Xtensa Processor Design Process

The Tensilica extension language is used to describe new instructions, registers and execution units that are then automatically added to the Xtensa processor

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( 모듈 2) Design Flow

1. Choose basic Xtensa processor

2. Specify algorithm in C

3. Compile to Target Processor

4. Profile and check, if design constraints are met

5. If constraints are met, everything is fine, otherwise

6. Choose optional functions (e.g. Multiplier) or design new instructions for the critical part => improved architecture

7. Adjust your code for the new architecture

8. Go back to 3.

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( 모듈 2) Summary (Configurable Processor)

The Xtensa concept provides o Not only a configurable architecture

o But also a design methodology

The idea is to take the best of both the hardware and the software world in order to

o Have good performance

o Short Time-to-Market

Xtensa processors can be used as parts of a system-on-chip architecture

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( 모듈 ) 참고문헌 “System Modeling – Model of Computation and their Applications,” Axel Jant

sch LECS, Royal Institute of Technology, Stockholm, Sweden Jan, 2004. “Winning the SoC Revolution-Experiences in Real Design,” Grant Martin & He

nry Chang, Cadence Labs, KAP, Jun, 2003. “System Design and Methodology: Modeling and Design of Embedded Syste

ms,” Petru Eles, Linkopings Univ., Sweden “Memory Issues in Embedded Systems-on-Chip,” Preeti Ranjan Panda (Synop

sys, Inc.), Nikil Dutt (Univ. of Cal/Irvine), Alexandru Nicolau (Univ. of Cal/Irvine), KAP 1999.

module2: system architecture for reconfigurable platform 최해욱 (icu, 공학부 )

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