mosfet lectures 2013

8/13/2019 MOSFET Lectures 2013

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E6604 Advanced Topics Semiconductor Devices

Metal Oxide Semiconductor Field Effect Transistors

Metal oxide semiconductor field effecttransistors

1. Field effect transistors: introduction

2. MOS capacitors (MOSC)

3. Long channel MOSFET

4. Short channel effects in MOSFETs

5. Strained silicon MOSFETs


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Field Effect Transistors

Three-terminal devices similarto a parallel plate capacitor

One plate acts as conducting

channel between source and drain

Another plate (gate) controls thecharge induced in the channelvia an electric field.

Gate

Source Drain

Dielectric


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Types of FETsThe FETs represent a family of devices:1. Junction field effect transistors (JFET)2. Metal semiconductor field effect transistors

(MESFET)3. Metal insulator semiconductor field effect transistors

(MISFET)

Examples: MOSFET is a type of MISFET Thin film transistor (TFT)


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Active Matrix Information Display

Do you know whats at the back of your TV ?


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Thin Film transistorsThe TFT is a device of great importance to the information

display industry and large area electronics .Used for semiconductors that cannot be obtained easily in theform of wafers. A low cost substrate e.g. glass is used.Typically, a TFT often has an inverted structure compared withthe MOSFET.


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MOSFET: Introduction o Metal Oxide Semiconductor Field Effect Transistor.

o The silicon MOSFET is the most important device in VLSItechnology because of its application in logic and memoryICs. E.g. microprocessors, DRAM, non-volatile memory

o MOSFETs are manufactured in immense numbers by thesemiconductor industry worldwide every year. MOSFETfabrication is relatively straightforward compared with bipolartransistors

o MOSFET structure is well suited for device scaling .


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MOSFET historical developmentThe MOSFET was invented in 1960at Bell laboratories by Atalla and Kahngusing the planar process.

The device consists of silicon (Si), itsoxide (SiO 2) and a metal gate.

Current flows parallel to the Si surface inan inversion layer. The SiO 2 acts as aninsulator and a diffusion mask for thesource and drain. It took 30 years todevelop because of the difficulties withthe semiconductor/dielectric interface. C.T. Sah Evolution of MOS transistor fromconcept to VLSI Proc. IEEE 76, 1280 (1988)


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MOSFET Operation Uses an electric field effect to modulate the conductivity of

silicon surface.

Controlling gate electrode is electrically isolated from thesilicon (zero input current). Unipolar device: current in on-state due to minority carriers

in a thin conducting sheet next to the Si-SiO 2 interface.

The conducting layer is formed by inverting the Si surfacein the channel region. Inversion ensures good device todevice isolation

G

S D


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Scaling of MOSFETsSource: MRS Bulletin

2000 2008


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MOS Capacitors

1. Conducting gate (metal orheavily doped polysilicon)

2. Silicon dioxide (SiO 2) gateInsulator*

3. Silicon substrate (100)* SiONx silicon oxynitride and

high k dielectrics are also usednowadaysNote: p-Si substrate for p-MOSC; nSi substrate for n-MOSC


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Energy band diagram for MOSC

Fundamentals of Modern VLSI Devices, Ch. 2

Metal Silicon Oxide p-Silicon

EF

EC

Ev

q m

q m

Ec

EFEv

q s

Eg


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DefinitionsVacuum level , E 0: energy at which the electron is free from the

lattice (convenient reference energy).Electron affinity , q m: energy required to raise an electron fromthe conduction band edge, E C to E 0. (usually measured in eV)

Work function , q m,s : energy required to raise an electron fromthe Fermi level, E f to E 0.

Ionization energy : energy required to raise an electron from thevalence band edge, E V to E 0.


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Charge Coupled DeviceEvery digital camera uses an image sensor to capture the

imagesIn some digital cameras, CCDs are used as the image sensor. Photons converted to electrons are stored inside the pixels of the CCD.

A CCD is basically an array

of MOS capacitors

J.D. Cressler, Silicon Earth CUP (2009)


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MOS Capacitor: Bias Conditions A MOS capacitor can be biased into any of four conditions:

1. Flatband2. Accumulation3. Depletion4. Inversion

Applies to both n-MOS and p-MOS capacitors.

For brevity, only p-MOS capacitors will be discussed in detail inthe following. For n-MOS capacitors, polarities are reversed.


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Flatband Condition

This is a special condition of the MOS capacitor where there is nonet charge or electric field within the silicon.

Note: the energy bands in both silicon and oxide are flat.For the hypothetical case of m = Si as shown, flatband occurs atthe flatband voltage with V g = VFB = 0V (VFB usually is not zero).


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Accumulation in p-MOSC

Negative gate bias relative to the Si substrate (electrons in metalgain energy).

Fermi level of metal raised with respect to Fermi level of Si.

Electric field is induced in the silicon dioxide.


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Accumulation in p-MOSCEnergy band of Si bends upwards near the surface because:

Holes (majority carriers) are attracted to the surface and form anaccumulation layer

At equilibrium (zero net current), the Fermi level must remainconstant throughout the Si.

The carrier concentration in Si is substantially smaller than that ina metal.


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Inversion in p-MOSC

For a sufficiently positive gate bias, the intrinsic Fermi level at theSi surface will be pushed below the Fermi level.

At this condition, it is energetically favorable for electrons topopulate the Si surface (potential well). The Si surface of the p-MOSC is said to be inverted to n-type.


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Inversion in p-MOSCSince electrons are minority carriers in p-Si, they have to be

generated by thermal excitation to form the inversion layer.From Boltzmann relation, electron concentration dependsexponentially on the difference between E i and E F.

Weak inversion : occurs as soon as intrinsic Fermi level crossesthe Fermi level ( MOSFET turn off ).

Strong inversion : occurs when electron concentration at surfaceequals hole concentration in the bulk of substrate ( MOSFET turn on ).


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Inversion in p-MOSC

At strong inversion, negative charge in Si consists of: Electrons in surface inversion layer

Negative acceptor dopant fixed charge

The width of the depletion layer no longer increases with gatebias because of the screening effect of the inversion layer.


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Poissons* EquationUsed for finding potentials within semiconductor devices.

Based on Gausss law (see appendix): D

Substituting for D = and = -grad ,

2

r : permittivity of medium.

For 1-D problems in Cartesian coordinates, this simplifies to:

2

2

dxd

* Pwahsong French


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Surface potential of SiliconElectrostatic potential within silicon is usually (but not necessarily)

described using the intrinsic potential, i .

q

E ii

For a one-dimensional analysis, the band bending in Si is givenby:

)()()( x x x ii

(0) = s is the surface potential.


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Surface potential in silicon of MOScapacitor


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Solving Poissons Equation for p-MOSCThe potential (x) is found by solving:

)()()()(22

x N x N xn x pq

dxd

ad Si

subject to the boundary conditions that: = 0 inside the bulk and =

s at the surface of the Si.

Note: p, n, N d and N a are concentrations.


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From charge neutrality requirements in the bulk, we get:

a

iaad N

n N x N x N

2

)()( (law of mass action)

Hole density, p(x) is given by Boltzmann relation:

kT q

N kT

qn x p a

i f i

exp)(

exp)(

Electron density, n(x) is given by:

kT q

N n

kT qn xn

a

i f ii

exp)(exp

2


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Substituting these charge densities into Poissons equationyields:

1exp1exp

2

2

2

kT q

N n

kT q N q

dxd

a

ia

Si

Note: right hand side does not involve N d anymore. After some algebraic manipulations, this equation can beintegrated from the bulk to an arbitrary point x.


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The square of the electric field E = -d /dx can be expressed thusin terms of the potential :

1exp1exp2

)(

222

kT q

kT q

N n

kT q

kT qkTN

dxd

xa

i

Si

a

Oxide Silicon

No field

Gaussian Surface

D

E6604 Ad d T i S i d D i


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At x = 0, E = E s and = s.

From Gausss law, the charge per unit area induced in silicon, Q s:

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1exp1exp2

kT q

kT q

N n

kT q

kT q

kTN Q ssa

issaSis

This equation embodies all the MOS bias conditions discussedearlier (i.e. accumulation, depletion, inversion).

E6604 Ad d T i S i d t D i


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Silicon Charge, Q s For flat-band, s = 0 and Q s = 0

For accumulation, s < 0 (electron energy), the exp(-q s/kT) termdominates and Q s increases as exp(-q s/2kT).

For depletion, s > 0 and the term q s/kT dominates. This leadsto a dependence of Q s on s1/2.

When s increases further, the exponential term(ni2/Na)exp(q s/kT) eventually becomes dominant and inversionoccurs. Q s becomes proportional to exp(q s/2kT).



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Plot of charge density Q s versus surface potential



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Strong InversionThis case can only be solved numerically because both the

depletion and inversion charge term has to be included:

kT q

N n

kT qkTN

dxd

a

i

Si

a

exp2

2

2

Example:Numerical solution carried out for

p-type wafer: N a = 10 16 cm -3 (typical for CMOS)surface potential: 0.85V and 0.88V



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Angstrom



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p


Common criterion for strong inversionThe onset of strong inversion is said to occur when the surfacepotential reaches a value where the term:

1exp22

kT q

N n s

a

i

This can be rewritten in the more familiar form of:

i

a Bs n

N q

kT inv ln22)(

Here B = f - i (x = infinity) is the bulk potential.



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p


MOS Gate Voltage EquationThe Si surface potential, s is not directly measurable. However,

it is related to the gate voltage V g.

s

ox

ssoxg

C

QV V

where C ox is the oxide capacitance per unit area .

Note: V g is the sum of the voltage drops across the oxide and theband bending in Si and we assume for simplicity, V fb = 0. V fb maynot be zero in practice.



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MOS Small Signal CapacitancesThe total small signal MOS capacitance is defined as:

g

s

dV

Qd C

We can differentiate the gate voltage equation with respect to |Q s |and define a Si component capacitance:

s

sSi d

Qd C



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from which,

Siox C C C 111



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Experimental Method for Measuring MOS CapacitanceProcedure:

Apply a dc bias across the MOScapacitor.

Superpose a small ac signal (


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Capacitance- Gate Voltage Curves (p-MOSC)

Note: Flatband voltage = 0V for this plot.



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Capacitance-Voltage: AccumulationFrom solution of Poissons equation, we know that in theaccumulation region:

kT q

Q ss 2exp

Hence,

sgoxsSi V C kT qQ

kT qC

22



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The MOS capacitance is:

sgox V

qkT C C

/21

11

Since 2kT/q ~ 52mV at room temperature, the capacitancerapidly approaches C ox as V g decreases.

For voltages close to the flatband voltage, the capacitancedecreases.



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Capacitance-Voltage: DepletionIn this region, the depletion approximation is applicable and

s

aSid Si qN C C

2

where C d is the depletion region capacitance.

The total capacitance is:

aSi

s

ox qN C C

211

The capacitance decreases with increasing gate bias in thisregion.


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Capacitance-Voltage: Inversion (high frequency)If the frequency of the applied ac signal is too high, the inversioncharge (minority carriers) will not be able to follow the signal andonly the depletion charge (majority carriers) can respond.

CSi is given by the depletion capacitance with the depletion widthat maximum value.

The high frequency capacitance is a constant:

aSi

ia

ox N qn N kT

C C 2min)/ln(411


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Equivalent circuits for an MOS capacitor



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Deep DepletionIf the dc bias is ramped up very fast (ramp time < minority carrierresponse time), the inversion layer will not have a chance to form.

The MOS capacitor will be biased into deep depletion. Thedepletion width will continue to increase and the capacitance will

continue to decrease below C min.Deep depletion is a non-equilibrium condition so eventually thecapacitance will return to C min.

The time it takes to return to C min is called the retention time.



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Oxide and Interface ChargesThe C-V characteristics of real MOS structures are different fromthe ideal characteristic considered so far.

Differences arise from the presence of:- Interface trapped charge, Q it

Fixed oxide charge, Q f Mobile ionic charge, Q m Oxide trapped charge, Q ot

[IEEE nomenclature was standardized by Deal in 1978. It is used throughoutthe literature.]


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Surface States and Interface Trapped ChargeLocalized electronic statesdue to the termination ofperiodicity at the Si surface.(refer BJT)Surface states are located at theSi-SiO 2 interface and haveenergies in the Si bandgap.

Electrons and holes can be trappedby surface states causing:

reduced conduction current reduced carrier mobility

Metal SiO 2 Silicon

SurfaceStates

EF

EC

EV



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Control of Surface States1. The density of surface states depends strongly on waferorientation (100) < (110) < (111). Hence, Si(100) wafers arepreferred for CMOS fabrication.

2. Post-metallization anneal: Annealing at 400 0C in a hydrogen (or deuterium, D

2*) containing

ambient is effective in reducing surface states. H-Si bonds willterminate and passivate dangling bonds.

*Deuterium (heavy hydrogen) is an isotope of hydrogen with one neutron in thenucleus .


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Mobile Ionic Charge These charges are due to Na + or K+ contamination during

wafer processing.

Na + and K + ions can drift readily within SiO 2 when anelectric field is applied and at elevated temperatures.

Mobile ionic charge near the Si-SiO 2 interface can causeleakage currents and increased Coulomb scattering.

Contamination control is essential to reduce mobile ioniccharge. Hence, the need for cleanrooms in waferfabrication.



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Oxide Trapped Charge Localized states (traps) can be generated easily inside

SiO 2 by bombardment by charge particles or energeticphotons.

Traps can subsequently trap electrons or holes injected by

tunneling or hot carrier effects into SiO 2. Traps are removed relatively easily by thermal annealing.


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CMOS Complementary metal

oxide semiconductor

(CMOS) logic makes useof p- and n-channelMOSFETs to realize logicfunctions.

In a CMOS circuit, 50% ofdevices are pMOS and50% are nMOS.

CMOS logic is usednowadays because of itslow standby powerdissipation.

IBM System 390 G5 MicroprocessorSource: Fundamentals of modern VLSIdevices (back cover)



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Schematic Diagram of n-MOSFETTaur, Ning, Ch. 3



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Basic Operation of n-MOSFET1. OFF StateGate voltage is zero or below threshold V t.Silicon surface is in accumulation or depletion.Only leakage current flows between the source and drain(two back-to-back n +-p junctions).

2. ON StateGate voltage is positive or above threshold.Silicon surface inverted to n-type due to electrons from source

drainConducting channel links the source and drain.Drain voltage results in electron current.



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Long Channel MOSFETsThese are earlier generation MOSFETs where the channel lengthis greater than ~10 microns.

Two approximations will be used to derive the currentcharacteristics of long channel MOSFETs:

Gradual channel approximation (GCA)

Charge sheet approximation

Current-voltage expressions describe the on-state of theMOSFET device.


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Drain Current ModelCoordinates:x: normal to Si surfacey: parallel to current directionz: perpendicular to current directionL: channel lengthW: channel width

Terminal voltages:Vds : drain voltage (relative to source)

Vg: gate voltageV(y): voltage at point y along channel(relative to source)



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Gradual Channel ApproximationThe variation of the electric field along the channel (y-direction) is much smaller than the corresponding fieldvariation perpendicular to the channel (x-direction).

Note:

Use of GCA will reduce the Poissons equation from 2-D to just 1-D and simplifies the analysis.

Applicable to most of the channel except the pinch-off pointand beyond.



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The electron current density at a point (x,y) is:

dy ydV

y xnq y x J nn)(

),(),(

(refer BJT collector current)where,

n is the electron mobility in the channel (


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The total current is obtained by multiplying J n by W andintegrating over the depth of the inversion layer from x=0 to x=x i.

dxdydV

y xnqW y I

i x

nds ),()( 0 [There is a sign change because we define I ds>0 when it is in the y direction.]

Applying the GCA, we can take dV/dy out of the integral.We further assume that the channel mobility can be replaced byan averaged or effective mobility, eff which is a constant.

Only n(x,y) remains inside the integral.


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Define Q i to be the charge per unit area under the gate atdistance y along the channel:

i x

i dx y xnq yQ0

),()(

and we can write:

)()()( V QdydV

W yQdydV

W y I ieff ieff ds

Note that V is a function of y only.



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Multiplying both sides by dy and integrate from y=0 to L gives:

dV V QW dy I dsV

ieff

L

ds )]([00

Current continuity means that I ds is a constant independent of y.

Hence, finally,

dV V Q L

W I

dsV

ieff ds )]([0


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B b tit ti g thi i t I d i t g ti g g t


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By substituting this into I ds and integrating, we get:

2/32/3 )2(23

22

22 Bds B

ox

aSids

ds B fbgoxeff ds V

C

qN V

V V V

L

W C I

This is the basic current voltage characteristic for a long channelMOSFET.



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Two regions of MOSFET ON state 1. Linear or triode region (V ds < Vg)

Current I ds increases approximatelylinearly with Vds

2. Saturation region (V ds > Vg)

Current I ds becomes independent ofV

ds.



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I-V Characteristic in Linear (Triode) regionSince V ds is a small quantity in the linear region, I ds can beexpanded as a power series in V ds and retaining only linearterms:

dsox

BaSi B fbgoxeff ds V C

qN V V

LW

C I

42

This can be written more succinctly if we define a thresholdvoltage (for long channel) to be:

ox

BaSi B fbt C

qN V V

42


Substituting V into the I V equation


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Substituting V t into the I-V equation,

dst goxeff ds V V V LW

C I )(

i.e. the transistor behaves like a resistor with a sheet resistivity:

)(

1

t goxeff sh V V C

This sheet resistivity is controlled by the gate voltage V g.


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I-V Characteristic in Saturation RegionFor larger values of V ds , the second order terms in the powerseries expansion of I ds are not negligible and must be retained.The current in this region can be approximated by a second orderquadratic function of V ds .

2

2 dsdst goxeff ds V

mV V V

L

W C I

The quantity m is called the body effect coefficient andm is typically in the range 1.1-1.4.

As V ds increases, the drain current increases in a parabolicmanner and eventually reaches a maximum value.


This maximum of I ds occurs at :


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This maximum of I ds occurs at :

m

V V V V t gdsat ds

)(

at which,

m

V V

LW

C I I t goxeff sat ds 2

2

If the wafer is lightly doped (m=1), I sat reduces to a familiarexpression.

Note: for V ds >Vdsat , the current does not decrease and in factstays constant independent of V ds (saturation region).



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Pinch off and Current SaturationThe inversion charge, Q i ~ -C ox(Vg Vt mV(y)).For V = Vdsat , Q i = 0.

This shows that when saturation occurs, the inversion chargedensity (or surface conducting channel) disappears at the drain.

This condition is termed pinch-off .

For Vds > Vdsat , the pinch-off point only moves slightly towards thesource.

The voltage at this point remains at V dsat .


The physics of the MOSFET beyond pinch off is illustrated by the


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e p ys cs o t e OS beyo d p c o s ust ated by t eplot of V(y).


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Subthreshold CharacteristicsWhen V g is only slightly below V t (~10 -1V), the drain current is notzero. This current is referred as the subthreshold current .It comes about because the silicon surface is in weak inversion and minority carriers are still present.

The subthreshold current of a MOSFET is extremely important fordigital CMOS applications because for whichever output state ofa CMOS logic gate, half of the MOSFETs of one polarity are onand the other MOSFETs of the opposite polarity are off.Subthreshold conduction limits their turn-off behavior andincreases the standby power dissipation . (major issue!)



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Three regions of MOSFET operation

OFF



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Weak Inversion in Long Channel MOSFET

S D

G

Inversion layer

Potential at X = 0

x

y

s


In the subthreshold region, both diffusion and drift currents are


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important. This is different from the saturation region where driftcurrent is the major current component.

It is not easy to analyze subthreshold current and we confine tothe case of low drain bias.

Substituting the inversion charge Q i into the drain current

equation and integrating gives:

)1()1( //)(2

kT qV mkT V V qoxeff ds

dst g eeq

kT m

L

W C I



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Note:The subthreshold current depends on V g, Vds and the body effectcoefficient.

For Vds more than a few kTs, however, the subthreshold currentis mainly controlled by V g.



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Subthreshold SlopeThis describes the variation of the subthreshold current with V g and is usually denoted by the symbol, S.

q

mkT dV

I d S

g

ds 3.2log

1

10

Differentiate log I ds with respect to V g and note that log e10 = 2.3.Typically, S = 70-100mV/decade.

Note: due to an approximation made to derive I ds , the expressionfor S given above is also approximate and tends to underestimatethe actual subthreshold slope by 5-10%.



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Subthreshold SlopeFor VLSI applications, S should be small to obtain a rapid deviceturn-off.

However, this is not easy to achieve because S depends mainlyon the temperature T.

The substrate dopant density N a and the gate oxide thicknesscan be used to adjust S to a limited extent through the body effectcoefficient.



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Importance of the Subthreshold SlopeThe subthreshold slope is especially important to low powermicroelectronics. Typically, the supply voltage is reduced tosave both standby and switching power.

However, due to the finite value and the

limited scalability of S, the supply voltagecannot be made arbitrarily small.

Lowering V cc too much can result insignificant leakage current at logic 0because logic low is too close to V t.

Vcc

Vt

0

Subthresholdregion



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MOSFET Threshold VoltageFor a long channel MOSFET, V t is given by:

ox

BaSi B fbt C

qN V V

42

This is the gate voltage at which the band bending in Si is equalto 2 B and the charge in silicon consists only of the depletioncharge.

Vt is the most important of the MOSFET parameters.


f


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Substrate Bias Dependence of V t The effect of substrate bias (-V bs ) on V t can be easily worked outby using a simple transformation:


The threshold voltage with the substrate bias is:


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ox

BS BaSi B fbt

C

V qN V V

)2(22

i.e. the (reverse) substrate bias will increase the depletion regionand raises the threshold voltage.

The rate of change of V t with Vbs is sometimes called the

substrate sensitivity. The substrate sensitivity increases with bothNa and V bs .


Vt D d T


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Vt Dependence on TemperatureThe threshold voltage is temperature dependent because both V fb and B are functions of temperature.

The temperature coefficient of V t for a Si MOSFET is about 1mV/K.

Note:This is significant for VLSI circuits because they typically operateat elevated temperatures (heat generation) and the subthresholdcurrent will increase as a result of this negative coefficient.


S b i OS


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Submicron MOSFETsTheory outlined thus far can only describe accurately thebehavior of earlier generation MOSFETs.

As lithography improves and the channel length of a MOSFETreduces, significant deviations from long channel behavior can be

readily observed.These deviations are in general undesirable to circuitapplications. Careful device design and process integration are

needed to avoid these effects.


O i i f S d Eff t i S b i


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Origin of Secondary Effects in SubmicronMOSFETs

Breakdown of the assumptions in the one-dimensional modelor equivalently, the onset of two-dimensional effects

The rules for scaling MOS devices are not followedprecisely.


D i ti f L Ch l B h i


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Deviations from Long Channel Behavior1. Short channel effect (SCE)

2. Narrow channel effect (NCE)

3. Velocity saturation

4. Channel length modulation


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Examples of SCE in nMOSFETs and pMOSFETs


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Subthreshold Current in Short Channel MOSFETs


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For the L = 0.2mm device, the subthreshold current is much greater when V ds isincreased.


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Physical Origin of Short Channel Effect


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Physical Origin of Short Channel Effect2. Short Channel DeviceFor the same V g and V ds , the

equipotential contours are morecurvilinear.

Electric field is two-dimensional.

More band-bending at the Si surfaceand depletion region is wider.

Device has lower threshold voltage.


Two dimensional field pattern is due to the proximity of the sourceand drain.


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and drain.

Each forms a p-n junction and has an associated depletionregion.

For the long channel case, these depletion regions are sufficientlyfar apart that they do not affect the field pattern in the device.

For the short channel case, the separation of the source-drain iscomparable to the MOS depletion width and the field pattern isthus strongly affected by the source drain voltages.


Threshold Voltage Lowering by SCE


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Threshold Voltage Lowering by SCE1. Charge Sharing Model*

2. Drain induced barrier lowering (DIBL)**

*L.D Yau, A simple theory to predict the threshold voltage of short channel IGFETs,Solid State Electronics, 17, 1059 (1974).

**R.R. Troutman, VLSI limitations from drain-induced barrier lowering, IEEE Trans.

Electron Devices, ED-26,461 (1979).


Charge Sharing Model


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Charge Sharing ModelThis is the earliest model for estimating the extent of the SCE.

Provides a simple (but rather arbitrary) analytical expression forVt in short channel devices.

Based on the electrostatic principle that electric field lines mustbegin and terminate on electric charges.

Consider the total depletion charge within an nMOSFET:


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This is because some of the charges in the rectangular volumehas to be shared with the source and drain.


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Since the channel region effectively has fewer dopant charges,the V t will be lower.

ox

B B fbt

WLC

QV V

'

2


'' L LWQ


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2

W Q dm B

is the total depletion charge within the trapezoidal region. This isless than the corresponding charge Q B for the long channel case.

LW Q dm B (long channel)


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The plot shows the surface potential (for electrons) as function ofthe normalized distance, y/L.


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At the source (y/L=0), a surface potential barrier preventselectrons from entering the channel region when the device is off.

For long-channel case (curve A), potential barrier is flat anduniform over most of the channel.For short-channel case (curves B,C), potential barrier is lowerand more rounded.

If the drain bias increases, the barrier is lowered even more

(DIBL). A reduced potential barrier increases the likelihood ofelectrons entering the channel and leads to a reduced thresholdvoltage.


2-D Poissons Equation and Lateral Field Penetration

Th l i fi ld i h d l i i f MOSFET i h


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The electric field in the depletion region of a nMOSFET withuniform dopant density is given by:

Si

a y x qN y x

Note:Si x/ x can be interpreted as the charge density controlled by

the gate field and

Si y/ y is the charge density controlled by the source-drain field.


Simulated lateral field vs distance y in depletion region


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Note:

For (a), the lateral field decreases exponentially with distance.


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The characteristic length of this exponential decay does notchange with the channel length.

Hence the lateral field in the middle of the short channel device isstronger than the long channel device.

Application of a drain bias shifts the zero field point towards thesource. The zero field point corresponds to the point of potentialmaximum in DIBL.


Control of SCE by Channel Engineering

Dopant


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One way to minimize the SCE is to use a retrograde doping profile in

the MOSFET channel. Near the Si-SiO 2 interface, the dopant density islower to reduce impurity scattering. The region further down is heavilydoped to limit the depletion widths and reduce the SCE.

This heavily doped region must be accurately positioned by ionimplantation. If the bottom of the source and drain are heavily doped,parasitic junction capacitance will become large.

N+ PolysiliconDopantDensity

xc

x x j Pulse shaped doping x c


Source Drain Extensions


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Shallow junctions insertedbetween source-drain and

submicron device channel.

Self-aligned ion implantation

Deposit spacer dielectric andthen second implant.

Keep source-drain away from channel.Tradeoff is increased series resistance.

S-D Extension

Spacer


Narrow Channel Effect

f f


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If the width of the channel W is reduced to being comparable withthe MOS depletion width (very short gate), one-dimensional

analysis again breaks down.The fringing fields at the end of the gate induce extra depletioncharge. This causes the observed threshold voltage to increase

as W is reduced.


Narrow Channel Effect


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Assuming the fringing region to be cylindrical shaped, we can

show that:


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W

xWLxqN Q d d ad

maxmax

2

1

The increase in V t due to narrow channel effect is:

W C xqN

V ox

d at 2

)( 2max


Velocity Saturation

I l g h l MOSFET I


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In a long channel MOSFET, I dsincreases with V ds until Vdsat and

then saturates at I sat .In a short channel MOSFET,the current will saturate at a

much lower drain voltage.

The saturation current is alsomuch smaller than what ispredictedby long channel theory.


Velocity-Field Relationship

Velocity saturation is due to the non linear relationship between


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Velocity saturation is due to the non-linear relationship betweenthe drift velocity and field for electrons and holes in

semiconductors. At low fields, drift velocity is proportional to electric field:

v = eff EMobility is limited by:

Acoustic phonon scattering Ionized impurity (coulomb) scattering Surface roughness scattering

Gate Oxide

Dopant ion


At high longitudinal fields, the carriers interact with optical

phonons and their velocity no longer increases linearly.


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Experimental velocity-field (v-E) data can be fitted by:

nn

c

eff

v 1

1

where E c : critical field; n = 2 for electrons and n = 1 for holes.


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From this model,

at low fields, we have the familiar relation:


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eff v

At high fields, the velocity saturates at v sat and:

ceff sat v Note:vsat is a constant independent of the field.

eff and E c are functions of the normal (vertical) field


Application of velocity-field relation to current-voltage

For simplicity, consider the case of n=1. Allowing for velocity


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p y g ysaturation effects,

dydV vdydV

V WQ I sat eff

eff ids //1

/)(

After rearranging and integration:

Lv

V

dV V Q LW

I

sat

dseff

V

ieff

ds

ds

1

)()/(0


Note:

The numerator is simply long channel current. This current isbeing reduced by the denominator factor.


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For low fields, the denominator is not significant.

Solid curves: calculated drain saturation current per unit width versus gate overdrive using equation from previous page;Dashed curves: calculated drain saturation current per unit width for long channel behavior


Channel Length Modulation

This causes a slight increase in the drain current of a short


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This causes a slight increase in the drain current of a shortchannel MOSFET beyond the pinch off or velocity saturation

point. As a result, the output conductance of the transistor becomesnon-zero.

Note: the short channel effect can also cause the I ds to increasein a similar way.


Channel Length Modulation

As V ds increases beyond V dsat ,


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As V ds increases beyond V dsat ,pinch off point will shift slightly

towards the source.The distance between the pinch-off point and the drain is the

amount of channel lengthmodulation, L.


Channel Length ModulationThe voltage at the pinch off point is independent of V ds and it will


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g p p premain at V dsat .

Since the GCA is valid up to the pinch off point, the saturationcurrent can be found simply by replacing L by L - L in Isat .

For the simpler long channel case, the saturation current isincreased by the factor L/(L- L):

L

L I

I dsat ds

1


Source-Drain Series Resistance

Parasitic resistances associated with the finite sheet resistivities


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of the source and drain regions and the ohmic contacts.

Not important in long channel devices where the channelresistance is appreciable.

However, channel resistance is comparable to the source drainresistances in short channel devices.


Source-Drain Series ResistanceSource drain resistance causes current degradation and is most


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severe in the linear region with high gate bias.

The typical minimum channel sheet resistivity in this region isabout 2k /sq for nMOSFETs and 7k /sq for pMOSFETs.

Clearly, source drain resistance effects are not significant in thesaturation region (I ds independent of V ds ).


Effect of source drain resistance on I-V characteristics


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Accumulation layer resistance

Gate edge typically overlaps with the source and drain. At thegate - source (or drain) overlap regions, carriers are confined inan accumulation layer with resistance R ac


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an accumulation layer with resistance R ac .

Spreading resistanceThis is the resistance component associated with the spreadingof the injection current from the thin accumulation layer into thesource or drain. For a uniformly doped source-drain,

c

j jsp x

x

W R

4

3ln

2

where j is resistivity; x j and x c are the junction

depth and accumulation layer thickness respectively. W is thedevice width.


Sheet resistance

This is the resistance of the source-drain diffusion regions and issimply given by:


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simply given by:

W S

R sd sh

where S is the spacing between the edge of the gate and the

edge of the metal contact and sd is the resistivity of the sourcedrain diffusion.

This resistance component is usually negligible because of thelow value of sd .


Contact resistance

The contact resistance is given by:


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c

sd c

csd CO lW R

coth

where l c is the width of the contact window; c is the interfacialcontact resistivity of the ohmic contact between the metal andsilicon. Unit is in ohm-cm 2.

Current in an ohmic contact is dominated by tunneling or fieldemission. c is therefore strongly dependent on the barrier heightand the surface doping concentration.


Self-aligned Silicide ContactsIn advanced CMOS devices, R CO and R sh are minimized by the

f lf lig d ili id


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use of self-aligned silicides.

A low resistivity silicide layer (e.g. TiSi 2) is formed over the entiresource drain diffusion. This layer is isolated from the gate bymeans of dielectric spacers. The silicide effectively shunts the

current flow from the diffusion regions.Rsh is limited to the non-silicided regions beneath the spacer.

Rco is reduced because the width of the contact window, l c is thewidth of the diffusion region.


Self Aligned Silicide Contacts


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Strained Silicon MOSFET

From 1970 1997, the semiconductor industry has reliedl l d i li g ( h i ki g idth/thi k ) t


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solely on device scaling (shrinking width/thickness) to

achieve rapid performance gain in integrated circuits. During this period, the material set (Si, SiO 2 ,Al) and theMOSFET structure did not change.

From 1997 till today, however, the industry is increasingly

using new electronic materials e.g: SiGe, strained silicon, high k dielectrics, metal gates Novel device structures: Strained Si FET , FinFET (2011), Si

quantum wire FET (2016) Strained Si MOSFETs were introduced in 2004 and is now

standard in all nanoscale Si MOSFETs


Stained Silicon MOSFETs


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What is Strain?Strain is a term from mechanical engineering. When a force(tension or compression) is applied to any solid e g silicon the


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(tension or compression) is applied to any solid e.g. silicon, thesolid will deform elastically up to a certain limit.

Within the elastic limit, any deformation is fully recovered, i.e.when the force is removed, the solid snaps back to its original

shape and size.Strain is defined as the change in length per unit length and is anumber with NO unit.


Hookes law states that for an elastic solid, the stress is

proportional to strain. The ratio of stress and strain is the Youngsmodulus.


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Stress = Youngs Modulus x Strain

Stress is the force divided by the area perpendicular to the forceand has the unit of Pascal (Pa = N/m 2)

Therefore strained silicon really means silicon under tremendousstress.


Why use strain?

Semiconductor Properties Ge Si


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Crystal structure Diamond DiamondLattice constant (nm) 0.5646 0.5431Density (g/cm 3) 5.3267 2.328Energy gap (eV) 0.67 1.12Electron mobility cm 2V-1s -1 3900 1500

Lattice constant affects the properties of a semiconductor such asthe band gap.


Why use strain?

Semiconductor Properties SC SiCrystal structure ~Diamond Diamond


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Crystal structure Diamond Diamond

Lattice constant (nm) 0.5441 0.5431Density (g/cm 3) Different 2.328Energy gap (eV) Different 1.12Electron mobility cm 2V-1s -1 Different 1500

Consider a hypothetical semiconductor SC with a different latticeconstant from Si but the same crystal structure.


Note:SC does not have to be chemically different from Si. By applyingstress to silicon, we can change its lattice constant because ofH k l


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Hookes law.

Strained Si is therefore not the same as normal silicon.

If stress is applied in the right way, the mobility of electrons andholes can be increased in strained Si.

If stress is applied the wrong way, the mobility of electrons andholes can decrease in strained Si.


Piezoresistivity Effect

Strained silicon devices are basedon the piezoresistivity effect.Strain gauges used for measuring


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Strain gauges used for measuring

Strain in buildings and structures Also make use of this effect.

The resistivity of a semiconductor issensitive to the mechanical strainimposed. This effect was discoveredby Smith (Bell Laboratories) in 1954.

Piezoresistivity effect is not the sameas the piezoelectric effect.


Strained Silicon nMOSFETsTensile stress has to be applied to the Si channel in the direction of the sourceand drain.Thi t i t i ll li d b (i) d iti g l f t il t d SiN


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This stress is typically applied by (i) depositing a layer of tensile stressed SiN x

by plasma enhanced chemical vapor deposition and (ii) selective epitaxialgrowth of SiC x source and drain.

The tensile stress changes the band structure of silicon. In the conductionband, there is a reduction in degenerate states near the conduction bandbottom and intervalley scattering is reduced. This increases the electronmobility.

p-Si

Tensile Silicon Nitride


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Strained Si p-MOSFETsCompressive stress is applied to the Si channel in the direction of the sourceand drain.The compressive stress can be realized by (i) PECVD of compressive SiN


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The compressive stress can be realized by (i) PECVD of compressive SiN x

(control composition) and (ii) selective epitaxial growth of raised SiGe sourcedrain. This is because Ge has a larger atomic radius than Si.

The reason for hole mobility enhancement is very complicated. The presentunderstanding is that the curvature of the valence band is changed and thedegenerate states in the valence band are also lifted.

SiGe source SiGe Drain

n-Si


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Measured leakage current

1E-6

W=1 m

SMT_25nm_SiN SMT_50nm_SiN


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0.0 0.2 0.4 0.6 0.8 1.01E-9

1E-8

1E-7

Vg (V)

W 1 mL=60nmVds=0.1V

I g ( A )

Strained silicon n MOSFET

State of the art gate dielectric


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Metal gate

High k dielectric

Source: IBM

Gate leakage current

Direct tunneling Fowler Nordheim tunneling

Positive gate


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polysilicon p Si polysilicon p Si

S i O2

Barrier height = 3.1eVg

bias

Substrate injection

Reversal of gate bias polarity will lead to gate injection.

Direct tunneling current

Observed at lower gate voltage < barrier height B onsemiconductor side (~3eV)

Occurs mainly in very thin oxide layers


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Occurs mainly in very thin oxide layers

Electrons see the full oxide thickness and they move fromSi to gate by quantum tunneling of electronic wavefunction

DT current is given by a complicated function of the oxidefield E ox that is usually approximated by:

2

32

)1(/exp/exp

P

E P E AE I oxoxox

tunnel

K.F. Scheugraf, C.C. King, C. Hu, Symp. VLSI Tech. 18 (1992)

B

ox B V

P for B Vox >1 otherwise P = 0


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CET and EOT Capacitance equivalent thickness (CET) Measure the specific capacitance, Cacc of the high k MOS

capacitor.


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p CET = 3.90 Cacc CET is the equivalent SiO2 thickness of the high k layer based

on Cacc of the high k MOS capacitor EOT = CET 0.3 (nm) A quantum mechanical correction (0.3nm) is usually applied

to the CET to find the equivalent oxide thickness (EOT)


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Appendix


MOS Electrostatics: Gauss Law

First of Maxwells four E&M equations.


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Integrated form:Qds D

s

.(enclosed charge)

Point form:

D. (charge density)Gaussian Surface(arbitrary)


Computed E-k diagram forunstrained silicon. Each curverepresents solutions toSchrodingers equation and eachpoint gives the energy andmomentum (k) of an eigenstatefor electrons


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for electrons.

Note the x axis is for specificdirections in the Brillouin zone.The Greek alphabets refer topoints of high symmetry.

There are multiple states foreach value of k because allallowed eigenstates can beplotted with the first Brillouinzone. Oval indicates the E g ofsilicon.

mosfet lectures 2013

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