october 18, 2001cho & kim 1 software synthesis ee202a presentation october 18, 2001 young h. cho...
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October 18, 2001 Cho & Kim 1
Software Synthesis EE202A Presentation
October 18, 2001
Young H. Cho and Seung Hyun Kim
October 18, 2001 Cho & Kim 2
OutlineBackgroundHW/SW Co-designSoftware SynthesisSummary
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BackgroundEmbedded SoftwareConstrained Structure “Simple,” Multiple TasksTarget Architecture
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HW/SW Co-designReactive Real-time SystemMixed HW/SW SystemSoftware – FlexibilityHardware – Performance
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HW/SW Co-Design
Formal Languages
Partitioning
HW SynthesisSW Synthesis
RTOS Tasks Logic Synthesis
Code Optimization Logic Optimization
Board Level Prototyping
Co-SimulationAnd
Formal Verification
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Partitioning High-Level DesignFormal Languages
Textual Representation Graphical Representation
Design Partitioning Platform Resource HW/SW Synthesis
A
B
C
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Software SynthesisGoal: Optimized software
from high-level specification Issues to consider
Target hardware support Retargetable compilers
Result: Efficient code for the target processor
A
BC
begin X1=TaskA(W); X2=TaskA(W); Y=TaskB(X1); result=TaskC(X2,Y);end
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Code GenerationStatic Code
Static (object) code for each tasks Library of inline codes Code optimization
Task Handling Resource management Static/dynamic scheduling Communication
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Software Synthesis Example
Task BDownsample
2 to 1
Task AUpsample
1 to 3
3
2
High-LevelDescription
Static Code
for (i=0;i<3;i++) { Out[i]=In;}
Reg=In[0]+In[1];Out=Reg>>1;
main(Samples *In) { while() { /* Schedule 2A */ for (j=0;j<2;j++) {
/* inline code: Task A */ for (i=0;i<3;i++) { OutA[j*3+i]=InA[j]; } }
for (k=0;k<3;k++) {
/* inline code: Task B */ Reg=OutA[k*2] +OutA[k*2+1]; OutB[k]=Reg>>1; } }}
Code Generation
2 (TaskA) 3 (TaskB)
& Schedule
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Programming ModelsFSM Model
Co-design Finite State Machine (CFSM)Dataflow Models
Synchronous Dataflow (SDF) Boolean Dataflow Dynamic Dataflow
Processor NetworkOthers
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CFSMExtended FSMGlobally Asynchronous Locally
Synchronous (GALS)Unbiased towards HW or SWReactive, control-dominated systemsSize of the systems that can be mapped
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SW Synthesis with CFSMSoftware Graph (S-Graph)Task SynthesisReal-Time Operating System (RTOS)Machine Code Compilation
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S-GraphControl/Data-Flow DiagramDirected Acyclic Graph (DAG)
BEGIN
present_c = 1
a = ?c
a’ := 0
emit_y := 1
END
a’ := a + 1a’ := a
emit_y := 0
false true
false true
module simpleCFSM:input c: integer;output y;var a: integer in loop await c; if a = ?c then a := 0; emit y; else a := a + 1; end if end loopend varend module
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Task SynthesisConstruction
Translation of transition function of CFSM Recursively built from the reactive function
Optimization Reordering or collapsing test nodes Code-size estimation
Translation Target language (e.g., C code)
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RTOSScheduling
Individual CFSMCommunication Mechanisms
Set of flags Memory mapped I/O port of the micro-
controller Polling or interrupts
Synthesis or Commercial RTOS
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Cost/Performance EstimationAccurate and Quick Estimation
Code size Min/max execution time
Considerations Code structures System platform
Solution Assign cost/timing parameters
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SDFDigital Signal ProcessingGraphical Representation
Actors/Nodes Directed edges Delays
Synchrony Consume Tokens Produce Tokens Fixed number of Tokens
a
b
c
1
2
1
2
2D
D
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Schedule/MemoryStatic schedulingDetermine task buffer sizeMemory efficient edge delayDeterministic at compile time
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SW Synthesis with SDFLibrary of actor code blocksDetermine static schedule
Optimal code size Performance
Inline code using schedule
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SummaryHW/SW Co-designSoftware Synthesis
Highly optimized code Timing constraints
Efficient Resource Usage Highest performance per cost Control over implementation cost
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Related Research Berkeley HW/SW Co-Design Group
http://www-cad.eecs.berkeley.edu/~polis
Berkeley Ptolemy Group http://ptolemy.eecs.berkeley.edu
CHINOOK http://www.cs.washington.edu/research/chinook/
VULCAN Cadence Cierto VCC Jeckle: the JAVA ECL compiler
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References 1. A. Sangiovanni-Vincentelli, “What is software synthesis?,” Computer
Design Editorial, Department of EECS, UC Berkeley, Berkeley, CA, June 1997.
2. Berkeley POLIS Group, “A Framework for Hardware-Software Co-Design of Embedded System,” POLIS Website, Department of EECS, UC Berkeley, Berkeley, CA, 1997.
3. F. Thoen, M. Cornero, G. Goosens, and H. DeMan, “Software synthesis for real-time information processing systems,” ACM SIGPLAN, Vol. 30, No. 11, November 1995.
4. Linkoping University HW/SW Co-design Course Website, http://www.ida.liu.se/~zebpe/codesign/, 1998.
5. EE249 “Design of Embedded Systems: Models, Validations, and Synthesis,” http://www-cad.eecs.berkeley.edu/~polis/class/index.html, UC Berkeley, CA. 2001.
6. P. Chou, and G. Borriello, “Software scheduling in the co-synthesis of reactive real-time systems,’ 31st ACM/IEEE Design Automation Conference, San Diego, CA, pp. 1-4, June 1994.
..
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References7. E. Lee, “Embedded software,” UC Berkeley ERL Memorandum
M01/26, http://ptolemy.eecs.berkeley.edu/publications/papers/01/embsystems/
8. F. Balarin, L. Lavagno, P. Murthy, and A. Sangiovanni-Vincentelli, “Scheduling for embedded real-time systems,” IEEE Design & Test of Computers, Vol. 15, No. 1, pp. 71-82, January-March 1998. http://ielimg.ihs.com/iel3/54/14269/00655185.pdf
9. S. Bhattacharyya, R. Leupers, and P. Marwedel, “Software synthesis and code generation for signal processing systems,” IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, Vol. 47, No. 9, pp. 849-875, September 2000.
10. S. Bhattacharyya, P. Murthy, and E. Lee, “Synthesis of embedded software dataflow specifications,” Journal of VLSI Signal Processing Systems, Vol. 21, No. 2, pp. 151-166, June 1999.