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Chapter 6

Lecture Homepage : http://signal.korea.ac.kr

2015년 7월 10일

6.2.3 Logic Gate Design Goals The designer should attempt to minimize the undefined input

region while maximizing noise margins

Voltage changes at the output of a gate should not affect the input side of the circuit (Unidirectional)

Voltage levels of the output of one gate should be compatible with the input levels of a proceeding gate

The gate should have sufficient fan-out and fan-in capabilities

The gate should consume minimal power (and area for ICs)

Chapter 6


2015년 7월 10일

6.3 Dynamic Response of Logic Gates

An important figure of merit to describe logic gates is their response in the time domain

Dynamic response : Performance parameters for logic gate

Rise time, Fall time Propagation delay Power-Delay product

Chapter 6


2015년 7월 10일

6.3.1 Rise Time and Fall Times The rise time and fall time, tr and tf, are measured at the 10% and

90% points on the transitions between the two states as shown by the following expressions:

V10% = VL + 0.1∆V

V90% = VL + 0.9∆V = VH – 0.1∆V

where, ∆V = VH – VL

Chapter 6


2015년 7월 10일

Dynamic Response of Logic Gates Fig. 6.5

Chapter 6


2015년 7월 10일

6.3.2 Propagation Delay Propagation delay describes the amount of time between a change

at the 50% point input to cause a change at the 50% point of the output described by the following:

The high-to-low propagation delay, τPHL, and the low-to-high propagation delay, τPLH, are usually not equal, but can be described as an average propagation delay :

2LH

50%VVV

2PLHPHL

P

Chapter 6


2015년 7월 10일

6.3.3 Power Delay Product The overall performance of a logic family is ultimately determined

by how much energy is required to change the state of the logic circuit

The power-delay product is represents the energy required to perform a basic logic operation and is another figure of meritwidely used to compare logic families and given by the following equation :

P : the average power dissipated by the logic gate τP : the average propagation delay Unit : J [Joules]

PPPDP

Chapter 6


Fig. 6.6 Logic Gate Delay vs Power Dissipation

NMOS Review

Chapter 6


Signal Processing Lab., http://signal.korea.ac.krDept. of Elec. and Info. Engr., Korea Univ.

2015년 7월 10일

NMOS Fabrication (cont.)

W : Channel width L : Channel length

Chapter 6



2015년 7월 10일

Qualitative I-V Behavior (a) VGS << VTN

Only small leakage current can flows.

(b) VGS < VTN Depletion region formed under gate merges

with source and drain depletion regions. Depletion region has no free carriers.

Therefore no current flows between source and drain.

(c) VGS > VTN Channel formed between source and drain. If

VDS>0, A resistive connection exists between the source and drain terminals, therefore finite ID flows from drain to source.

The gate terminal is insulated from the channel, thus, there is no DC gate current IB = 0 and IG = 0.

Chapter 6



2015년 7월 10일

Depletion mode NMOS transistor

Depletion mode NMOS device The channel may be established so that it is present under the condition VGS=0

by implanting suitable impurities in the region between source and drain during manufacture and prior to deposing the insulation and the gate.

Under these circumstances, source and drain are connected by a conducting channel.

The channel may be closed by applying a suitable negative voltage (threshold voltage) to the gate.

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Enhancement-mode : Operating region

Channel is established VGS > VTN , VDS = 0V no current flowing between source and drain (VDS = 0V)

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2015년 7월 10일

Enhancement-mode : Operating region (cont.)

Non-saturation region (linear region) The effective gate voltage to maintain the channel is VG = VGS – VTN

There will be voltage available to invert the channel at the drain end so long as VGS – VTN ≥ VDS , and the limiting condition comes when VDS = VGS – VTN

I-V characteristics appear to be a family of nearly straight lines, therefore this operation region is called linear or triode or ohmic region.

DSDS

TNGSnD

TNGSDSTNGS

VVVVL

WKI

VVVVV

)2

)((

,

'

Chapter 6



2015년 7월 10일

Enhancement-mode : Operating region (cont.)

2'

))((2 TNGS

nD VV

LWKI

(c) Saturation region (pinch-off region)

VGS > VTN, VDS > VGS - VTN

Near the drain, there is insufficient electric field available to create the channel

The channel region has disappeared, or pinched off.

When the electrons reach the pinch-off point, they are injected into the depletion region then swept to the drain

The voltage drop across the channel is constant. Hence the drain current saturates at constant value.

Chapter 6



2015년 7월 10일

Enhancement-mode : Operating region (cont.) I-V characteristics for NMOS transistor

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2015년 7월 10일

6.6 NMOS Logic Design

NMOS inverters with four different load configurations are considered

The resistor load Saturated load Linear load Depletion-mode load

The circuit designer’s job is to choose the circuit topology and the W/L ratios of the MOS transistors to achieve the desired logic function

Chapter 6


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6.6.1 NMOS Inverter with a Resistive Load Load resistor R is used to “pull” the

output up toward the power supply VDD

NMOS transistor MS is used to switching transistor

Design parameters The size of R W/L ratio of switching transistor MS

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2015년 7월 10일

Design of VL

To ensure that switching transistor MS is cut-off when the input is in the low logic state

The gate-source voltage of MS must be less than its threshold voltage VTN

VL is designed to be 25~50% of the threshold voltage VTN of switching transistor MS.

For VTN = 1V VL = 0.25 ~ 0.50V In this text book, 0.25V is selected for VL

Chapter 6


2015년 7월 10일

6.6.2 Design of the W/L ratio of MS Known NMOS parameters

Logic low state voltage : VL = 0.25V Threshold voltage : VTN = 1V Transconductance parameter : K’n = 25 x 10-6 A/V2

Power dissipation : 0.25mW

step 1 : Find iDP = VDD x IDD = 0.25 x 10-3 = 5 x IDD , IDD = iD = 50uA , ∴ iD = 50uA

step 2 : Find W/L ratio from drain current iD equation

5 x 10-5 = 25 x 10-6 x (W/L) x (5 – 1 – 0.125) x 0.25 , ∴ (W/L) = 2.06 / 1

DSDS

TNGSnD vvvvL

WKi

2'

Chapter 6


2015년 7월 10일

6.6.3 Load Resistor Design

Known parameters

Power supply voltage : VDD = 5V Logic low state voltage : VL = 0.25V Drain current : 50uA

Find load resistor R

ki

VVRD

LDD 95105

25.055

Chapter 6


2015년 7월 10일

6.6.4 Load Line Visualization : Quiescent Operating point MOSFET output characteristics (violet) and load line (blue) : fig 6.17

Equation for load line

Q-point (red circle) If MOSFET cut-off

iD = 0AvDS = VDD = 5V

If vGS = VH = 5VvDS = VL = 0.25V

RiVv DDDDS

Chapter 6


2015년 7월 10일

Design a NMOS inverter with resistive load for Power supply voltage : VDD = 3.3 V Power dissipation : P = 0.1 mW when VL = 0.2 V Transconductance parameter : Kn

’ = 60 uA/V2

Threshold voltage : VTN = 0.75 V

Find the value of the design parameters of the switching transistor MS Design parameters

load resistor R W/L ratio

Design Example

Chapter 6


2015년 7월 10일

First the value of the current through the resistor must be determined by using the following:

The value of the resistor can now be found by the following which assumes that the transistor is on or the output is low:

μA 3.30V3.3

mW1.0 , DD

DDDDDDD VPiIVIP

kΩ 102μA3.30

V2.0V3.3

D

LDD

iVVR

NMOS Inverter with Resistive Load Design (cont.)

Chapter 6


2015년 7월 10일

NMOS Inverter with Resistive Load Design (cont.) Review of NMOS behavior

Cut-off region

VGS < VTN Triode (Linear) region

VGS - VTN ≥ VDS ≥ 0 , Saturation (pinch-off) region

0≤ VGS - VTN < VDS , For vI = VL = 0.2V

VGS is less than threshold voltage VTN

MOSFET is cut-off Output voltage vO = VH = VDD = 3.3V

DSDS

TNGSnD VVVVL

WKI

2'

2'

2 TNGSn

D VVL

WKI

Chapter 6


2015년 7월 10일

For vI = VH = 3.3V VGS is higher than threshold voltage VTN

MOSFET is operated in triode region

Find W/L ratio by using linear equation (drain current equation)

NMOS Inverter with Resistive Load Design (cont.)

11

103.1

2.022.075.03.31060103.30

22

66

''

LW

LW

VVVVL

WKVVVVL

WKI LL

TNHnDSDS

TNGSnD

0 DSTNGS VVV

Chapter 6


2015년 7월 10일

On-Resistance of the Switching Device

The NMOS resistive load inverter can be thought of as a resistive divider

when the output is low, described by the following expression:

RRRR

RVV

on

on

onDDL

Chapter 6


2015년 7월 10일

On-Resistance of the Switching Device (cont.) When the NMOS resistive load inverter’s output is low, the On-

Resistance of the NMOS can be calculated with the following expression:

Note that Ron should be kept small compared to R to ensure that VL remains low, and also that its value is nonlinear which has a dependence on VDS

2

12

'

'

DSTNGSn

DSDS

TNGSn

DS

D

DSon

vVvL

WK

vvVvL

WK

vivR

Chapter 6


2015년 7월 10일

Load Resistor Problems For completely integrated circuits,

R must be implemented on chipusing the shown structure

Using the given equation, it can be seen that resistors take up a large area of silicon as in an example 95kΩ resistor

1

9500001.0

10195 4

cmcmkRt

WL

tWLR

Chapter 6


2015년 7월 10일

Transistors Alternatives to the Load Resister NMOS load with

a) gate connected to the source : not useful b) gate connected to ground : not useful c) gate connected to VDD : Saturated load inverter

will be considered in chap 6.7

Chapter 6


2015년 7월 10일

Transistors Alternatives to the Load Resister (cont.)

NMOS load with d) gate biased to triode (linear) region : Linear load inverter e) a depletion-mode NMOS : Highest performance

will be considered in chap 6.8 will be considered in chap 6.9

Chapter 6


2015년 7월 10일

Static Logic Inverter Design Strategy 1. Given VDD, VL, and the power level, find IDD from VDD and power

2. Assume MS off, and find high output voltage level VH

3. Use the value of VH for the gate voltage of MS and calculate (W/L)S of the switching transistor based on the design values of IDDand VL

4. Find (W/L)L (load transistor) based on IDD and VL

5. Check the operating region assumptions of MS and ML for vo = VL

6. Verify design with a SPICE simulations

Chapter 6


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This alternative inverter has a load transistor that is biased with VGG defined by the following:

This causes the load transistor to operate in the linear (triode) region

The output voltage in the high output state VH is equal to VDD

TNLDDGG VVV

NMOS Inverter with a Linear Load Device

Chapter 6


2015년 7월 10일

NMOS Inverter with a Linear Load Device (cont.) Operation region of load transistor ML

When vI = VH , vO = VL

Linear region operation condition VGG ≥ VDD + VTNL

DSoDD

TNLOTNLDD

TNLOGGTNLGS

VvVVvVV

VvVVV

condition regionlinear ;DSTNLGS VVV

Chapter 6


2015년 7월 10일

Merit of NMOS inverter with a linear load MOSFET

VH can be reached to VDD

Demerit of NMOS inverter with a linear load MOSFET

Cost problem : Additional power supply Increasing wiring congestion introduced by distribution of the extra

power supply voltage to every logic gate

NMOS Inverter with a Linear Load Device (cont.)

Chapter 6


2015년 7월 10일

NMOS Inverter with a Depletion-mode Load

Because the VTNL is negative, a channel exists even for VGS = 0V, and load transistor conducts until VDS becomes 0V

When input voltage level is VL, output voltage level VH can be reached to VDD

For vI = VOH, because VGSL = 0V, ML is operating in saturation regionVDSL ≥ VGSL – VTNL or VDSL ≥ – VTNL

With the addition of a depletion-mode NMOS (VTH < 0V), it is possible to configure an inverter as shown

Chapter 6


2015년 7월 10일

Design of W/L ratio of ML Design example

Given condition VDD = 5V, VL = 0.25V, VTNL = -3V vO = VL, VDSL = 4.75V ID = 50uA, Kn’=25uA/V2

Operation region : saturation region VDSL ≥ VGSL – VTNL or VDSL ≥ – VTNL

2'

2'

2

)(2

TNLL

n

TNLGSLL

nDL

VL

WK

VVL

WKI

Chapter 6


2015년 7월 10일

Design of W/L ratio of ML(cont.) VTNL with considering body-effect

Calculate (W/L)L

V -2.93)6.06.025.0(5.03

)22(

FFSBTOTNL VγVV

15.21

1466.0

)93.2(102510502

2

2

26

6

2'

2'

TNLn

DL

L

TNLL

nDL

VKI

LW

VL

WKI

Chapter 6


2015년 7월 10일

Design of the W/L ratio of MS (W/L)S is identical to the design of the NMOS logic gate with resistor

load vI = VH = VDD , vO = VL

MS is operated in triode region ( VGS – VTN ≥ VDS ) (W/L) S can be found by using linear equation

DSSDSS

TNSGSSS

'nDS VVVV

LWKI

2

LL

TNSH'n

DS

S VVVVK

IL

W

2

Chapter 6


2015년 7월 10일

NMOS Inverter Summary and Comparison

Resistive load inverter takes up too much area for IC design

The saturated load configuration is the simplest design, but VHnever reaches VDD and has a slow switching speed

The linear load inverter fixes the speed and logic level issues, but it requires an additional power supply

The depletion-mode NMOS load requires extra processing steps, but consumes the smallest area to achieve the highest speed, VH = VDD, and best combination of noise margins

Chapter 6


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Inverter Characteristics & Reference Inverter

Resistor Load Saturated Load Linear Load Depletion-Mode LoadVH 5.0 V 3.4 V 5.0 V 5.0 VVL 0.25 V 0.25 V 0.25 V 0.25 V

NML 0.34 V 0.32 V 0.02 V 0.69 VNMH 1.43 V 0.69 V 2.78 V 2.25 V

Area (μm2) 9500 6.92 9.36 4.21

Chapter 6


2015년 7월 10일

NMOS NAND and NOR gates In NMOS logic, an additional transistor can be added to the simple

inverter to form either a NOR or a NAND logic gate.

The NOR gate represents the combination of an OR operation followed by inversion

The NAND function represents the AND operation followed by inversion

A high logic level corresponds to a logical 1 and a low logic level corresponds to a logical 0

VH ≡ 1 and VL ≡ 0

Chapter 6


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NOR Gates

Simplified switch model for the NOR gate with A on

Two-input NOR gate

A B Y0 0 10 1 01 0 01 1 0

Truth Table

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NOR Gates (cont.) : parallel switching Considering design parameters

MA or MB is conducting alone on-Resistance Ron of each individual

transistor must be chosen to give the desired output level.

Thus (W/L)A and (W/L)B should each be equal to the size of MS is the reference inverter.

MA and MB are both conducting Combined on-resistance Ron will be

equivalent to Ron/2 Then actual output voltage will be

somewhat lower than the original design value of VL = 0.25V

Chapter 6


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NAND Gates

Two-input NAND gate Simplified switch model for the NOR gate with A and B on

A B Y0 0 10 1 11 0 11 1 0

Truth Table

Chapter 6


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NAND Gates : Selecting the Sizes of the MS

tWLR

The NAND switching transistors can be sized based on the depletion-mode load reference inverter

To keep the low voltage level to be comparable to the inverter, the desired Ron of MA and MB must be Ron/2 of MS of reference inverter

Solution 1 : This can be accomplished by approximately doubling the (W/L)A and (W/L)B Review on resistance

Chapter 6


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Solution 2 : The sizes can also be chosen by using the design value of VLand using the following equation:

2)( and V25.0

2''

DSTNGSL

DSTNGSNEW

nDSDS

TNGSS

nD

vVvV

vVvL

WKvvVvL

WKi

SNEW

TNGSNEW

nTNGSS

nD

LW

LW

VvL

WKVvL

WKi

2

225.025.0

225.0 ''

NAND Gates : Selecting the Sizes of the MS (cont.)

Chapter 6


2015년 7월 10일

NAND Gates : Selecting the Sizes of the MS (cont.) Two effects on switching transistors

1: The source-bulk voltages of the two transistors are not equalMust considering body-effectThe values of the threshold voltages are different for MA and MB

2: VGSA ≠ VGSB

Recalculation of (W/L)A and (W/L)B given condition from reference inverter : VDD=5V, ID= 50uA, VL=0.25V

124.4 , 125.0

2125.004.1125.0510251050

04.1)6.06.0125.0(5.01

106.4 , 125.0

2125.01510251050

66

66

BB

TNB

AA

LW

LW

V

LW

LW

Chapter 6


2015년 7월 10일

Input Characteristics of MOSFET (Review)

)22(

)22(

FPFPBSPPTOPTP

FNFNSBNNTONTN

vVV

vVV

Chapter 6


2015년 7월 10일

NAND Gates : Choosing the size of the ML

When both MA and MB are conducting The ID current is limited by the load

device The voltages applied to the load

device are exactly the same as those in the reference inverter.

(W/L)L is the same as in the reference inverter

The completed NAND gate design : Figure 6.35(a) (right figure)

Chapter 6


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Complex NMOS Logic Design

The circuit in the figure has the logic function:

Y = A + BC + BD

Y = A + B(C + D)

A major advantage of NMOS technology is that it is simple to design complex logic functions based on the NOR and NAND gates

First example

Chapter 6


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Second example

Complex NMOS Logic Design (cont.)

The circuit in the figure has the logic function:

Y = AB+ CDB

Y = (A + CD)B

Chapter 6


2015년 7월 10일

Complex NMOS Logic Design (cont.) Device Sizing of Complex NMOS Logic

Using the worst case (longest) path and choosing the W/L ratio such that the Ron of the multiple legs match similar to the technique used to find the W/L ratios in the NAND Gate worst-case path : path CDB CDB path must have the total on-resistance

equivalent to the MS of reference transistor by making each transistor three times the size of

the reference switching transistor size increasing resistance decreasing

n × size (W/L) Ron / n

Chapter 6


2015년 7월 10일

Power Dissipation Two primary contribution to power dissipation in NMOS

inverters

1. Static power dissipationThe static power dissipation that occurs when the logic

gate output is stable in either high or low states

2. Dynamic power dissipationThe power that is dissipated in order to charge and

discharge the total equivalent load capacitance during dynamic switching of the logic gate.

Chapter 6


2015년 7월 10일

Static Power Dissipation Overall static power dissipation of a logic gate is the average of the

power dissipations of the gate when its outputs in the low state and the high state

IDDH = current in the circuit for vO = VH

IDDL = current in the circuit for vO = VL

Since IDDH = 0 A for vO = VH :

2DDLDDDDHDD

avIVIVP

2DDLDD

avIVP

Chapter 6


2015년 7월 10일

Dynamic Power Dissipation Dynamic Power Dissipation is the power dissipated during the

process of charging and discharging the load capacitance connected to the logic gate

DischargingCharging

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2015년 7월 10일

Dynamic Power Dissipation (cont.) Assumption

Capacitor is initially discharged Non-linear resistive element continues to

deliver current until the voltage across it reaches zero (ex: a depletion-mode load)

Switch closes at t = 0 Capacitor charges toward its final value Total energy delivered by the source VDD

2)(

)0(

000

)(

)()()(

DD

v

v CDD

CDDDDD

CVtdvCV

dtdt

tdvCVdttiVdttPE

C

C

Chapter 6

2015년 7월 10일

Dynamic Power Dissipation (cont.)

2)()(

)()()()()(

2)(

)0(

000

DDv

v CC

CCCS

CVtdvtvC

dtdt

tdvCtvdttitvdttPE

C

C

22

222 DDDD

DDSDLCVCVCVEEE

The energy stored in capacitor C

The energy lost in the resistive element

Chapter 6

2015년 7월 10일

Dynamic Power Dissipation (cont.)

222

22 DDDDDD

SLTD CVCVCVEEE

Assumption The capacitor is initially charged to VDD

Switch closes at t’ = 0 The capacitor discharges toward zero

through another nonlinear resistive element (ex: enhancement-mode NMOS transistor)

The capacitor is completely discharged and reaches its final value VC = 0V

The energy stored on the capacitor has been completely dissipated in the resistor

22DDS CVE

The total energy dissipated in the process of charging and discharging

Chapter 6

2015년 7월 10일

Dynamic Power Dissipation (cont.) Dynamic power dissipated by the logic gate

Every time a logic gate goes through a complete switching cycle (frequency) : Assume that the gate logic state is changed in every cycle

The transistors within the gate dissipate an energy equal ETD

Logic gates switch states at some relatively high frequency f, and the dynamic power dissipated by the logic gate is then..

fCVP DDD2

Chapter 6

2015년 7월 10일

Power Scaling in MOS Logic Gates The power supplied to the logic gate

P = VDD × ID If vO = VL, drain current IDL = IDS

For fixed voltages, both currents are directly proportional to their respective W/L ratio.

Power scaling : If the W/L ratio of ML and MS are changed by some factor, the power level of the gate can easily be scaled up and down without affecting the values of VH and VL.

DSSDSS

TNSGSSS

nDS

TNLGSLL

nDL

VVVVL

WKI

VVL

WKI

)2

(

)(2

'

2'

Chapter 6

2015년 7월 10일

a) Original saturated-load inverter b) Saturated Load inverter designed to operate at one-third the power

Power Scaling in MOS Logic Gates (cont.)

Chapter 6



2015년 7월 10일

Power Scaling in MOS Logic Gates (cont.)

Chapter 6


2015년 7월 10일

The time domain response plays an extremely important role in the logic applications

There exists the delay between input change and output transitions in logic circuits Every node is shunted by capacitance to ground These capacitance is not able to change voltage instantaneously

We will explore the dynamic or time-varying behavior of logic gates

Dynamic Behavior of MOS Logic Gates

Chapter 6


2015년 7월 10일

Dynamic Behavior of MOS Logic Gates (cont.) The MOS device has the various

capacitances

Each device has capacitances CSB, CGS, CDB, and CGD

Some of the capacitances are shorted out by the terminal connections ( ex : CSB1, CGS2, CSB3, CGS4 )

Capacitances associated with an inverter pair

Chapter 6



2015년 7월 10일

Dynamic Behavior of MOS Logic Gates (cont.)

Chapter 6


2015년 7월 10일

Dynamic Response of the NMOS Inverterwith a Resistive Load

Calculation of tr and τPLH

VF : Final capacitor voltage

VI : initial capacitor voltage

)exp()()(RCtVVVtv IFFO

Chapter 6


2015년 7월 10일

Dynamic Response of the NMOS Inverterwith a Resistive Load (cont.)

Calculation of the rise time tr

The rise time tr is measured at the 10% and 90% points on the transitions between the two states as shown by the right-side expressions :

RCRCttt

RCtRC

tVVVV

RCtRC

tVVVV

r

FI

FI

2.29ln

1.0ln , )exp(9.0

9.0ln , )exp(1.0

12

22

11

Chapter 6


2015년 7월 10일

Calculation of the propagation delay low to high τPLH

5.0ln , )exp(5.0

5.0)exp(

5.0)(

RCRC

VVRC

VV

VVv

PLHPLH

IPLH

F

IPLHO


RCPLH 69.0

Chapter 6


2015년 7월 10일

Calculation of τPHL and tf


nonlinear R and C network

iC = iD - iR

when iD = iR, capacitor is almost discharged

discharging current is larger than charging current

faster transition

Chapter 6


2015년 7월 10일

Calculation of τPHL and tf is complicated therefore simplify the model iC >> iR except for vO very near VL

iR is neglected


Chapter 6


2015년 7월 10일

Dynamic Response of the NMOS Inverter with a Resistive Load (cont.)

There are four important times that need to be considered

When characterizing the dynamic response of a logic circuit which are denote t1 – t4 in the figure t1 : output is dropped by 10% t2 : MS is changed the operation

from saturation region to triode region vO = VDD – VTNS

t3 : output is 50% of VF – VI

t4 : output is dropped by 90%

Chapter 6


2015년 7월 10일


Piecewise analysis of τPHL at t = 0+, MS is operating in saturation region

when vC = VGS – VTNS, MS is enter the linear region

HCC

TNSGSS Vv

dttdvCVVK

)0( , )()(2

2

)VV(KV)VVV(K

VR

)VV(VCR

)VV(KCVt

tV)VV(C

t)t(vC

dt)t(dvC)VV(K

TNSHSDSS

DSSTNSGSSS

DSSONS

TNSH

TNSONS

TNSHS

TNS

HTNSHCCTNSH

S

1

2

when

2202

22

2

2

Chapter 6


2015년 7월 10일


Piecewise analysis of τPHL (cont.) MS is operating in the linear region

Integrating both side from t2 to t3

where,

)(5.0)()( 3322 OLDDCTNSDDC VVtv , V-VVtvV

x

axaxxa

dxFormuladtC

Ktv-v-VV

tdv t

tS

CCTNSDD

C ln1)(

: , 2)()(2

)( 3

2

3

2

V

V

dtC

Ktv-v-VV

tdvdt

tdvCtvtvVVKtvtvVVK

S

CCTNSDD

C

CC

CTNSHSC

CTNSGSS

2)()(2)(

)()()2

)(()()2

)((

Chapter 6


2015년 7월 10일


Piecewise analysis of τPHL(cont.)

Propagation delay for high to low τPHL

)(21

)()(4ln

)(21

)()(4ln

223

TNSDD

TNS

OLDD

TNSDDONSPHL

TNSDD

TNSONS

OLDD

TNSDDONS

PHL

VVV

VVVVCR

VVVCR

VVVVCR

ttt

1)()(4ln

1)()(4ln

)(23

OLDD

TNSDDONS

OLDD

TNSDD

TNSDDS

VVVVCR

VVVV

VVKCtt

Chapter 6


2015년 7월 10일


Piecewise analysis of tf The fall time tf is measured at the 90% and 10% points on the transitions

between the two states :tf = t4 – t1 = (t4 – t2) – (t2 – t1)

MS is operating in saturation region in (t1, t2)

MS is operating in linear region in (t2, t4)

TNSH

TNSONS VV

VVCRtt

1.0212

VVVVVCRtt

H

TNSHONS 9.0

9.02ln24

Chapter 6


2015년 7월 10일


Piecewise analysis of tf (cont.) fall time tf

TNSH

TNS

H

TNSHONSf

TNSH

TNSONS

H

TNSHONS

f

VVVV

VVVVVCRt

VVVVCR

VVVVVCR

ttttt

1.029.0

9.02ln

1.029.0

9.02ln

)()( 1224

Chapter 6


2015년 7월 10일

Dynamic Response of the NMOS Inverter with a Depletion-mode Load

Just as in the resistive load inverter, the depletion-mode load inverter has the same dynamic response characteristics that need to be considered, and has four times t1 ~ t4 that needed for calculations t1 : output is increased by 10% t2 : MS is changed the operation

from saturation region to triode region vO = VDD + VTNL

t3 : output is 50% of VH – VL

t4 : output is increased by 90%

Chapter 6


2015년 7월 10일

The following are the basic equations for calculating dynamic response characteristics

TNL

LTNLHTNLonLr

TNSH

TNS

H

TNSHonSf

TNL

LTNLH

LH

TNLonLPLH

TNSH

TNS

LH

TNSHonSPHL

VVVVV

VVCRttt

VVVV

VVVVVCRt

VVVV

VVVCRttt

VVV

VVVVCRtttt

1.02120ln

1.029.0

9.02ln

214ln

214ln)(

14

223

2233

Dynamic Response of the NMOS Inverter with a Depletion-mode Load

Chapter 6


2015년 7월 10일

Final Comparison of Load Devices

Chapter 6


2015년 7월 10일

A Final Comparison of Load Devices (cont.)

Chapter 6


2015년 7월 10일

A Final Comparison of Load Devices (cont.) Body effect degrades the performance of the load device

The saturated load devices have the poorest τPLH since they have the lowest load current delivery

The saturated load devices also reach zero current before the output reaches 5 V vO cannot reaches VDD

The linear load device is faster than the saturated load device, but still slower than the resistive load inverter

The fastest τPLH is from the depletion-mode device

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