전자회로 II

제8주 1강

Chapter 7

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2015년 7월 10일

Minimum Size Gate Design and Performance All transistors are implemented with

minimum size. Let’s estimate the worst-case propagation delay

In NMOS network Worst-case path contains 2 devices REQ is two times larger than reference inverter

τPLH x 2

In PMOS network Worst-case path contains 3 devices REQ is 7.5 times larger than reference inverter

τPHL x 7.5

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7.8 Dynamic Domino CMOS Logic Dynamic logic circuits were first developed as a means of

reducing power in PMOS and NMOS logic

Dynamic logic uses different precharge and evaluation phasesthat are controlled by a system clock signal to eliminate the dc current path in single channel logic circuits

Merits of dynamic logic circuits Reducing the power consumption Reducing the silicon area

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Dynamic Domino CMOS Logic (cont.)

When clock is low

MNC is off No DC current path to VSS

MPC is on Pulling node 4 high to VDD and

forcing the inverter output to be low

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Single input Domino CMOS Gate When clock is low

MNC is off : no DC current path to VSS

MPC is on Pulling node 4 high to VDD and forcing

the inverter output to be low

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Single input Domino CMOS Gate (cont.)

Single input domino CMOS gate ( the case of F = A ) When clock is high

MPC is off , MNC is on If A is logic high, then the output of the

inverter charged to VDD

If A is logic low, then the output of the inverter remains at a 0

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2015년 7월 10일

Multi input Domino CMOS Gate Two examples of domino CMOS logic gates

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Multi input Domino CMOS Gate (cont.)

A major advantage of the domino CMOS circuit is the requirement for only two PMOS transistors per logic stage

Domino CMOS gates do not form a complete logic family because only true output functions are available. But this problem can be overcome by the following

Chapter 7

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Problem of Domino CMOS Gate Domino CMOS logic design offers smaller area and faster speed

than conventional CMOS logic design

However, domino CMOS logic suffers several design problems

In the pre-charge phase, if charge sharing is occur in output capacitor and junction capacitors, it may degrade output voltage level

Chapter 7

Lecture Homepage : http://signal.korea.ac.kr

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7.9 Cascade Buffers The input capacitance of a logic gate may be in the range of only 10 to

100 fF

However, there are many case in which a much higher load capacitance (10 to 50 pF) is encountered The word lines in RAMs and ROMs ( Chapter 8 ) Long interconnection lines and internal data buses in microprocessors

Load capacitance increased Increasing propagation delay

We want to reduce propagation delay by reducing load capacitance by reducing on-resistance of transistors (by increasing W/L ratio )

LonP CR

Chapter 7

Lecture Homepage : http://signal.korea.ac.kr

2015년 7월 10일

Cascade Buffers (cont.)

If the inverter is scaled up in size to reduce its own delay, then its input capacitance increases, slowing down the propagation delay of previous stage. W/L ratio is increased (on-resistance is decreased) propagation delay is decreased internal parasitic capacitance is increased input capacitance is increased

W/L ratio is increased by β times

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2015년 7월 10일

7.9.1 Cascade Buffer Delay Model By cascading an even number of inverters, it is possible to drive a

large load

The scaling factor β determines the increase of the cascaded inverter’s size

Stage Current

Stage Next

)/()/(

LWLW