p09311 interface for multipurpose driver/ data acquisition system
Post on 20-Dec-2015
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P09311Interface for Multipurpose Driver/
Data Acquisition System
Team• Adam Van Fleet (EE)
– DAQ Hardware Development– FPGA/DAQ Hardware Interface Development– Project Leader
• David Howe (EE)– DAQ Interfacing & USB Hardware Development– FPGA/DAQ Hardware Interface Development
• Michael Doroski (CE)– DAQ Interface Development (software)– Custom FPGA logic
• Thomas (TJ) Antonoff (CE)– USB interface development (software)
• Andrew Weida (CE)– FPGA Bluetooth interface development (UART)– GUI Development and PC Serial Communication
Customer Needs
Customer Need #
Importance Description Comments/Status
CN1 High Interfaces DAQ to FPGA
CN2 High Interfaces FPGA to PC
CN3 High Utilizes USB interface
CN4 Moderate Utilizes Bluetooth Wireless interface
CN5 Low USB Transfer rate minimum of 1.5Mbits/s and 12Mbits/s Depends on bottleneck limitations.
CN6 Low Bluetooth transfer rate minimum of 3Mbits/s Depends on bottleneck limitations.
CN7 Low 100% message transfer percentage (no lost packets)
CN8 High Capable of transferring numerical data
CN9 High GUI - Connection settings available
CN10 High GUI - Connection speed and status displayed
CN11 Low GUI - Displays GUI on Windows Operating System
CN12 High GUI - Data Storage System Ask Lukowiak - Does it need to store or only stream?
CN14 Low Interchangeable FPGA's Design for 1, but needs to work for others.
CN15 Low C# programming language Chosen for portability, no restrictions on language.
Project SpecificationsEngr.
Spec. #Importance Source Specification (description)
Unit of Measure
Marginal Value
Ideal Value Comments/Status
ES1 MED CN5USB Transfer rate min of 1.5Mbits/s and max 12Mbits/s Mb/s 1.5/12 1.5-12
ES2 MED CN6 Bluetooth Transfer rate min of 3Mbits/s Mb/s 3 3
ES3 MED CN8 100% message transfer percentage (no lost packets) Packets 0 100%
ES4 LOW CN2 Utilizes Ethernet Interface Mb/s N/A N/A TBD in MSD II
ES5 LOW CN2 Utilizes Wireless USB Interface Mb/s N/A N/A TBD in MSD II
ES6 LOW CN10 Ethernet Transfer Rate min: Mb/s N/A N/A TBD in MSD II
ES7 LOW CN9 USB Wireless Transfer Rate min 3Mbits/s Mb/s 3 3
ES8 LOW CN11 Option for Multiple Bluetooth Connections # of modules 3 3
ES9 LOW CN11 Option for Multiple USB Connections # of modules 3 3
ES10 MED CN2 FPGA Programming Language Language VHDL VHDL
Feat. # Importance Source Feature Description
F1 HIGH CN2 Utilizes USB Interface
F2 HIGH CN2 Utilizes Bluetooth Wireless Interface
F3 HIGH CN3 Capable of transferring data collected from the DAQ
F4 HIGH CN4 GUI-Connection settings available
F5 HIGH CN1 GUI-Connection speed and status displayed
F6 MED CN7 Interchangeable FPGAs to Meet CN2:ES13 & ES14
F7 HIGH CN4 GUI-Displays GUI on Windows Operating System
F8 HIGH CN4 GUI-Data Storage System
F9 LOW CN4 GUI Programming Language
Hardware-Level System Overview
RS-232
RS-232
USB
Parani ESD210SK Bluetooth Dev. Kit
Digilent Spartan-3 Board
DLP-USB245M USB Adapter
Windows-Based PC
P08311 DAQ Board
32-pin
(500 kbps xfer)
ASIC or Robotics Input
12-pin(up to 1MB/s xfer)
Pin-Outs for Additional Hardware
7
FPGA_D_OUT_9
FPGA_D_OUT_2
IDIN
FPGA_D_OUT_4
FPGA_D_OUT_5
5V
FPGA_D_OUT_3
C720.1uF
CLR_COUNTER
FPGA_D_IN_6
NOT_CP
0
FPGA_D_IN_5
FPGA_D_OUT_7
SDATA2
FPGA_D_IN_11
FPGA_D_IN_7
FPGA_D_IN_4
FPGA_D_IN_9
FPGA_D_IN_2
FPGA_D_OUT_0
FPGA_D_OUT_6
U13
SN74LVC1G04
1
2
3
5
4
NC
A
GND
Vcc
Y
FPGA_D_OUT_1
FPGA_D_OUT_8
SDATA1
VDIN
0
FPGA_D_OUT_11
CONNECTOR TO FPGA
0
FPGA_D_IN_10
LDAC
FPGA_D_IN_3
SYNC
FPGA_D_IN_8
J8
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
61 62
6463
1 2
3 4
5 6
7 8
9 10
11 12
13 14
15 16
17 18
19 20
21 22
23 24
25 26
27 28
29 30
31 32
33 34
35 36
37 38
39 40
41 42
43 44
45 46
47 48
49 50
51 52
53 54
55 56
57 58
59 60
61 62
6463
FPGA_D_IN_1
SCLK
FPGA_D_IN_0
FPGA_D_OUT_10
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
5
6
First 30 pins from connector A2
Second 2 pins from connector A1
1
2
3
4
5
6
7
8
9
10
11
12 13
14
15
16
17
18
19
20
21
22
23
24 I/O
I/O
I/O
I/O
I/O
I/O
I/O
RD
I/O
WR
TXE
RXF
DLP-USB245M
Pins 13-24 are connected to FPGA pins 7 through 18 of
connector A1
Data Flow Chart
DAQ
FPGA
Dual-Input Buffer
CustomLogic
Dual-Output Buffer
Dual-Input Buffer
Dual-Output Buffer
USB Data Routing Logic
Dual-Output Buffer
Dual-Input Buffer
USB FIFO
UART
USB Cable
Bluetooth Modules
Rx
Tx
Rx
Tx
RS2321.2 - 230 kbps
Bluetooth
Wireless Serial
Top Level: USB & Bluetooth Architecture Design
PC
500 kbps
8 Mbps
A/D Conversion on DAQ
100ns (10MHz)
Z2
Z1
SCLK
CS(start conversion)
T1 T2 T3
Z0
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20T19 T20
Hold Sample
SDATA2(serial output)
Sample
T17 T18
Z2
Z1
Z0
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0SDATA1(serial output)
D/A Conversion on DAQ
100ns (10MHz)
DB14
DB13
CLK
SYNC(begin transmission)
T1 T2 T3
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15 T16 T17 T18 T19 T20T19 T20
DIN1
LDAC(synchronous load)
DB15
Load output voltage data into DAC buffer
DB14
DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0DIN2
DB15
Data Path from DAQ to FPGA (Serial to Parallel Conversion)
Data Path from FPGA to DAQ(Parallel to Serial Conversion)
Custom Logic Diagram
Custom Logic FSM State Diagrams
FSM_In FSM_Out
Dual Buffer Layout
USB Read State Diagram
ID LE
SEN D
R ELO AD
EM PTY
State Title Signals Description
1 Idle RXF = 1, RD = 1, Write EN = 0, ACK = 0, Control = 1
RXF buffer is empty or filling (less than 1 byte in USB RXF buffer)
2 Sending RXF = 0, RD = 0, Write EN = 1, ACK = 0, Control = 0
One byte of data sent in parallel to buffer on FPGA.
3 Reload RXF = 0, RD = 1, Write EN = 1, ACK = 1, Control = 1
Write acknowledge forces the USB buffer to load next byte into position for read.
4 Empty RXF = 1, RD = 1, Write EN = 0, ACK = 1, Control = 1
When USB RXF buffer empty, go back to idle state
USB Write State Diagram
State Title Signals Description
1 IDLE EN = 0, TXE = 0, WR = 1 FPGA buffer doesn’t have enough information to send to USB yet or USB buffer is full and needs to wait for space to be made.
2 WRITE EN = 1, TXE = 0, WR = 0 FPGA is ready to write to USB. USB takes 1 bye in parallel from the FPGA buffer to the USB TXE buffer.
3 RELOAD / DELAY
EN = 1, TXE = 1, WR = 1 Write from USB goes high to allow for storage of byte just written.
ID LE
W R ITE
R ELO AD / D ELAY
EN = 1W R = 0
W R = 1TX E = 1
Pin Name Direction Description
1 CD «— Carrier Detect
2 RXD «— Receive Data
3 TXD —» Transmit Data
4 DTR —»Data Terminal
Ready
5 GND System Ground
6 DSR «— Data Set Ready
7 RTS —» Request to Send
8 CTS «— Clear to Send
9 RI «— Ring Indicator
• Hardware flow control is not supported on the connector. The port’s CD, DTR, and DSR signals connect together. Similarly, the port’s RTS and CTS signals connect together.
• The Parani-ESD has configurable hardware flow control. When hardware flow control is not being used, the Parani-ESD clears the buffer to secure room for the next data when the buffer becomes full. Loss of data may occur. As the transmission data becomes large, the possibility of data loss becomes greater.
Spartan-3 Starter Board – RS232 Interface
Signal Description
CLK System Clock
RST Asynchronous active-high reset.
Din[7:0] Eight-bits Data From Buffer
LD Load pulse to load Din in the Transmitter and start the transmission
Rx RS232 receive signal input. Is ’1’ when the line is idle.
Tx RS232 transmit signal output. Is ’1’ when the line is idle.
Dout[7:0] Data received.
RxRDY A ‘1’ pulse (one system clock cycle long) indicates that a character is received and is available at Dout.
TxBusy Indicates that the UART is busy sending data. Will ignore any LD request.
SDin[7:0] / SDout[7:0] Data received from RS-232
BuffDin[7:0] / BuffDout[7:0] Data From dual buffer, to be transmitted by UART
WriteBuff / ReadBuff Control signal to write or read to/from Dual Buffer
BuffFull / BuffEmpty Indicates if Buffers are Full or Empty.
UART System
idle
stop_tx
load_tx_data
Tx_data
UART Transmit State Machine
Put data in correct format:start+data bits
tx_tick = 1
tx_tick= 1tx_bit_cnt = 1
-Shift out data bit by bit-Decrement tx_bit_cnt
Stop_bit:
When LD = ‘1’ Latch input data
LD = ‘1’
Keep TxBusy asserted
UART Receive State Machine
shift_rx
stop_rx
idle
start_rx
rx_ovf
edge_rx
Wait on Rx_d falling edge (start bit occurs)
Wait on start bit:- Synchronize with rx_tick - Sample RX at mid-bit and verify the Start bit
Sample Data: -shift rx into a register-increment bit counter
Here during stop bitLatch data to outputRX_RDY = ‘1’
rx_tick = 1
Framing error
RxBitCnt = 8
rx_tick = 1
Rx_d = 0Rx_d = 1
rx_tick = 1
Should be near Rx _d edge
rx_tick = 1
Data StorageFormat:
<data>,timestamp;
GUIData Manager
Control
Signals
Data
Data
Connection Info
PC
USB Cable
PC Architecture Design (C#)
Connection Handler
Serial Cable
Connection Media
Connection Handler usingSystem.IO.Ports: SerialPort Class
GUI Class Diagram
GUI Concept Design
Risk Item Level Owner Status and/or Contingency Plans Decision Date
Transfer of knowledge from work of P08311 will be necessary for full
system understanding
LOW Adam Meet with Andrew Fitzgerald (P08311 Team Lead) to gather prior knowledge
10/3/08
Technological understanding of hardware / software to be used will
be critical to success
HIGH All Team Members
Personal research / professional help will be required Ongoing
Transition from embedded processor may pose problems
LOW All Team Members
Will require knowledge of P08311’s shortcomings 10/17/08
Possibility for data transmission bottlenecks at FPGA interfaces
CRIT Adam, Andrew, TJ,
Dave
Develop alternative method for data transmission (multiple devices in parallel, controlling the DAQ clock speed, memory storage of
data, etc.)
10/17/08
No background in Bluetooth or USB; interface will require
considerable time to produce
MED Adam, Andrew, TJ,
Dave
Extensive research of modes of data transfer will be required End of Quarter
Shortcomings of P08311’s work (Compact flash memory, embedded PowerPC processor, etc.) will need
to be evaluated
MED All Team Members
Research into previous data bottlenecks and possible solutions 10/17/08
Interfacing FPGA to DAQ without any I/O expansion will pose a
problem (Spartan-3 board)
HIGH Adam, Dave Research of FPGA’s containing enough I/O’s to handle all inputs/outputs from the DAQ board
10/17/08
Interfacing FPGA to Bluetooth / USB without any I/O expansion will pose a problem (Spartan-3
board)
HIGH Adam, Dave Research of FPGA’s containing enough I/O’s to handle all inputs/outputs from the DAQ board
10/17/08
VHDL knowledge (3 members have basic knowledge, 2 members
have almost no knowledge)
HIGH All Team Members
All team members will need to educate themselves in this area, as majority of software side of project revolves around VHDL
End of Quarter
Accurate monitoring of connection speed and status via GUI
LOW Mike Decrease refresh rate to allow for better calculation End of Quarter
Risk Assessment
Appendix
Spartan-3 Board Reference Materialhttp://www.digilentinc.com/Products/Detail.cfm?Prod=S3BOARD&Nav1=Products&Nav2=Programmable
DLP-USB245M USB Adapterhttp://www.dlpdesign.com/usb/usb245.shtml
Parani ESD210SK Bluetooth Dev. Kithttp://www.rfphone.com/files/ESD110.pdf